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of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / arch / avr32 / mach-at32ap / at32ap700x.c
blobb4cb3bd89d8ace17f50b509101b0e2e2e82a176f
1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/platform_data/dma-dw.h>
11 #include <linux/fb.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/gpio.h>
17 #include <linux/spi/spi.h>
18 #include <linux/usb/atmel_usba_udc.h>
19
20 #include <linux/platform_data/mmc-atmel-mci.h>
21 #include <linux/atmel-mci.h>
22
23 #include <asm/io.h>
24 #include <asm/irq.h>
25
26 #include <mach/at32ap700x.h>
27 #include <mach/board.h>
28 #include <mach/hmatrix.h>
29 #include <mach/portmux.h>
30 #include <mach/sram.h>
31
32 #include <sound/atmel-abdac.h>
33 #include <sound/atmel-ac97c.h>
34
35 #include <video/atmel_lcdc.h>
36
37 #include "clock.h"
38 #include "pio.h"
39 #include "pm.h"
40
41
42 #define PBMEM(base) \
43 { \
44 .start = base, \
45 .end = base + 0x3ff, \
46 .flags = IORESOURCE_MEM, \
47 }
48 #define IRQ(num) \
49 { \
50 .start = num, \
51 .end = num, \
52 .flags = IORESOURCE_IRQ, \
53 }
54 #define NAMED_IRQ(num, _name) \
55 { \
56 .start = num, \
57 .end = num, \
58 .name = _name, \
59 .flags = IORESOURCE_IRQ, \
60 }
61
62 /* REVISIT these assume *every* device supports DMA, but several
63 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
64 */
65 #define DEFINE_DEV(_name, _id) \
66 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
67 static struct platform_device _name##_id##_device = { \
68 .name = #_name, \
69 .id = _id, \
70 .dev = { \
71 .dma_mask = &_name##_id##_dma_mask, \
72 .coherent_dma_mask = DMA_BIT_MASK(32), \
73 }, \
74 .resource = _name##_id##_resource, \
75 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
76 }
77 #define DEFINE_DEV_DATA(_name, _id) \
78 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
79 static struct platform_device _name##_id##_device = { \
80 .name = #_name, \
81 .id = _id, \
82 .dev = { \
83 .dma_mask = &_name##_id##_dma_mask, \
84 .platform_data = &_name##_id##_data, \
85 .coherent_dma_mask = DMA_BIT_MASK(32), \
86 }, \
87 .resource = _name##_id##_resource, \
88 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
89 }
90
91 #define select_peripheral(port, pin_mask, periph, flags) \
92 at32_select_periph(GPIO_##port##_BASE, pin_mask, \
93 GPIO_##periph, flags)
94
95 #define DEV_CLK(_name, devname, bus, _index) \
96 static struct clk devname##_##_name = { \
97 .name = #_name, \
98 .dev = &devname##_device.dev, \
99 .parent = &bus##_clk, \
100 .mode = bus##_clk_mode, \
101 .get_rate = bus##_clk_get_rate, \
102 .index = _index, \
103 }
104
105 static DEFINE_SPINLOCK(pm_lock);
106
107 static struct clk osc0;
108 static struct clk osc1;
109
110 static unsigned long osc_get_rate(struct clk *clk)
111 {
112 return at32_board_osc_rates[clk->index];
113 }
114
115 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
116 {
117 unsigned long div, mul, rate;
118
119 div = PM_BFEXT(PLLDIV, control) + 1;
120 mul = PM_BFEXT(PLLMUL, control) + 1;
121
122 rate = clk->parent->get_rate(clk->parent);
123 rate = (rate + div / 2) / div;
124 rate *= mul;
125
126 return rate;
127 }
128
129 static long pll_set_rate(struct clk *clk, unsigned long rate,
130 u32 *pll_ctrl)
131 {
132 unsigned long mul;
133 unsigned long mul_best_fit = 0;
134 unsigned long div;
135 unsigned long div_min;
136 unsigned long div_max;
137 unsigned long div_best_fit = 0;
138 unsigned long base;
139 unsigned long pll_in;
140 unsigned long actual = 0;
141 unsigned long rate_error;
142 unsigned long rate_error_prev = ~0UL;
143 u32 ctrl;
144
145 /* Rate must be between 80 MHz and 200 Mhz. */
146 if (rate < 80000000UL || rate > 200000000UL)
147 return -EINVAL;
148
149 ctrl = PM_BF(PLLOPT, 4);
150 base = clk->parent->get_rate(clk->parent);
151
152 /* PLL input frequency must be between 6 MHz and 32 MHz. */
153 div_min = DIV_ROUND_UP(base, 32000000UL);
154 div_max = base / 6000000UL;
155
156 if (div_max < div_min)
157 return -EINVAL;
158
159 for (div = div_min; div <= div_max; div++) {
160 pll_in = (base + div / 2) / div;
161 mul = (rate + pll_in / 2) / pll_in;
162
163 if (mul == 0)
164 continue;
165
166 actual = pll_in * mul;
167 rate_error = abs(actual - rate);
168
169 if (rate_error < rate_error_prev) {
170 mul_best_fit = mul;
171 div_best_fit = div;
172 rate_error_prev = rate_error;
173 }
174
175 if (rate_error == 0)
176 break;
177 }
178
179 if (div_best_fit == 0)
180 return -EINVAL;
181
182 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
183 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
184 ctrl |= PM_BF(PLLCOUNT, 16);
185
186 if (clk->parent == &osc1)
187 ctrl |= PM_BIT(PLLOSC);
188
189 *pll_ctrl = ctrl;
190
191 return actual;
192 }
193
194 static unsigned long pll0_get_rate(struct clk *clk)
195 {
196 u32 control;
197
198 control = pm_readl(PLL0);
199
200 return pll_get_rate(clk, control);
201 }
202
203 static void pll1_mode(struct clk *clk, int enabled)
204 {
205 unsigned long timeout;
206 u32 status;
207 u32 ctrl;
208
209 ctrl = pm_readl(PLL1);
210
211 if (enabled) {
212 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
213 pr_debug("clk %s: failed to enable, rate not set\n",
214 clk->name);
215 return;
216 }
217
218 ctrl |= PM_BIT(PLLEN);
219 pm_writel(PLL1, ctrl);
220
221 /* Wait for PLL lock. */
222 for (timeout = 10000; timeout; timeout--) {
223 status = pm_readl(ISR);
224 if (status & PM_BIT(LOCK1))
225 break;
226 udelay(10);
227 }
228
229 if (!(status & PM_BIT(LOCK1)))
230 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
231 clk->name);
232 } else {
233 ctrl &= ~PM_BIT(PLLEN);
234 pm_writel(PLL1, ctrl);
235 }
236 }
237
238 static unsigned long pll1_get_rate(struct clk *clk)
239 {
240 u32 control;
241
242 control = pm_readl(PLL1);
243
244 return pll_get_rate(clk, control);
245 }
246
247 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
248 {
249 u32 ctrl = 0;
250 unsigned long actual_rate;
251
252 actual_rate = pll_set_rate(clk, rate, &ctrl);
253
254 if (apply) {
255 if (actual_rate != rate)
256 return -EINVAL;
257 if (clk->users > 0)
258 return -EBUSY;
259 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
260 clk->name, rate, actual_rate);
261 pm_writel(PLL1, ctrl);
262 }
263
264 return actual_rate;
265 }
266
267 static int pll1_set_parent(struct clk *clk, struct clk *parent)
268 {
269 u32 ctrl;
270
271 if (clk->users > 0)
272 return -EBUSY;
273
274 ctrl = pm_readl(PLL1);
275 WARN_ON(ctrl & PM_BIT(PLLEN));
276
277 if (parent == &osc0)
278 ctrl &= ~PM_BIT(PLLOSC);
279 else if (parent == &osc1)
280 ctrl |= PM_BIT(PLLOSC);
281 else
282 return -EINVAL;
283
284 pm_writel(PLL1, ctrl);
285 clk->parent = parent;
286
287 return 0;
288 }
289
290 /*
291 * The AT32AP7000 has five primary clock sources: One 32kHz
292 * oscillator, two crystal oscillators and two PLLs.
293 */
294 static struct clk osc32k = {
295 .name = "osc32k",
296 .get_rate = osc_get_rate,
297 .users = 1,
298 .index = 0,
299 };
300 static struct clk osc0 = {
301 .name = "osc0",
302 .get_rate = osc_get_rate,
303 .users = 1,
304 .index = 1,
305 };
306 static struct clk osc1 = {
307 .name = "osc1",
308 .get_rate = osc_get_rate,
309 .index = 2,
310 };
311 static struct clk pll0 = {
312 .name = "pll0",
313 .get_rate = pll0_get_rate,
314 .parent = &osc0,
315 };
316 static struct clk pll1 = {
317 .name = "pll1",
318 .mode = pll1_mode,
319 .get_rate = pll1_get_rate,
320 .set_rate = pll1_set_rate,
321 .set_parent = pll1_set_parent,
322 .parent = &osc0,
323 };
324
325 /*
326 * The main clock can be either osc0 or pll0. The boot loader may
327 * have chosen one for us, so we don't really know which one until we
328 * have a look at the SM.
329 */
330 static struct clk *main_clock;
331
332 /*
333 * Synchronous clocks are generated from the main clock. The clocks
334 * must satisfy the constraint
335 * fCPU >= fHSB >= fPB
336 * i.e. each clock must not be faster than its parent.
337 */
338 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
339 {
340 return main_clock->get_rate(main_clock) >> shift;
341 };
342
343 static void cpu_clk_mode(struct clk *clk, int enabled)
344 {
345 unsigned long flags;
346 u32 mask;
347
348 spin_lock_irqsave(&pm_lock, flags);
349 mask = pm_readl(CPU_MASK);
350 if (enabled)
351 mask |= 1 << clk->index;
352 else
353 mask &= ~(1 << clk->index);
354 pm_writel(CPU_MASK, mask);
355 spin_unlock_irqrestore(&pm_lock, flags);
356 }
357
358 static unsigned long cpu_clk_get_rate(struct clk *clk)
359 {
360 unsigned long cksel, shift = 0;
361
362 cksel = pm_readl(CKSEL);
363 if (cksel & PM_BIT(CPUDIV))
364 shift = PM_BFEXT(CPUSEL, cksel) + 1;
365
366 return bus_clk_get_rate(clk, shift);
367 }
368
369 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
370 {
371 u32 control;
372 unsigned long parent_rate, child_div, actual_rate, div;
373
374 parent_rate = clk->parent->get_rate(clk->parent);
375 control = pm_readl(CKSEL);
376
377 if (control & PM_BIT(HSBDIV))
378 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
379 else
380 child_div = 1;
381
382 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
383 actual_rate = parent_rate;
384 control &= ~PM_BIT(CPUDIV);
385 } else {
386 unsigned int cpusel;
387 div = (parent_rate + rate / 2) / rate;
388 if (div > child_div)
389 div = child_div;
390 cpusel = (div > 1) ? (fls(div) - 2) : 0;
391 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
392 actual_rate = parent_rate / (1 << (cpusel + 1));
393 }
394
395 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
396 clk->name, rate, actual_rate);
397
398 if (apply)
399 pm_writel(CKSEL, control);
400
401 return actual_rate;
402 }
403
404 static void hsb_clk_mode(struct clk *clk, int enabled)
405 {
406 unsigned long flags;
407 u32 mask;
408
409 spin_lock_irqsave(&pm_lock, flags);
410 mask = pm_readl(HSB_MASK);
411 if (enabled)
412 mask |= 1 << clk->index;
413 else
414 mask &= ~(1 << clk->index);
415 pm_writel(HSB_MASK, mask);
416 spin_unlock_irqrestore(&pm_lock, flags);
417 }
418
419 static unsigned long hsb_clk_get_rate(struct clk *clk)
420 {
421 unsigned long cksel, shift = 0;
422
423 cksel = pm_readl(CKSEL);
424 if (cksel & PM_BIT(HSBDIV))
425 shift = PM_BFEXT(HSBSEL, cksel) + 1;
426
427 return bus_clk_get_rate(clk, shift);
428 }
429
430 void pba_clk_mode(struct clk *clk, int enabled)
431 {
432 unsigned long flags;
433 u32 mask;
434
435 spin_lock_irqsave(&pm_lock, flags);
436 mask = pm_readl(PBA_MASK);
437 if (enabled)
438 mask |= 1 << clk->index;
439 else
440 mask &= ~(1 << clk->index);
441 pm_writel(PBA_MASK, mask);
442 spin_unlock_irqrestore(&pm_lock, flags);
443 }
444
445 unsigned long pba_clk_get_rate(struct clk *clk)
446 {
447 unsigned long cksel, shift = 0;
448
449 cksel = pm_readl(CKSEL);
450 if (cksel & PM_BIT(PBADIV))
451 shift = PM_BFEXT(PBASEL, cksel) + 1;
452
453 return bus_clk_get_rate(clk, shift);
454 }
455
456 static void pbb_clk_mode(struct clk *clk, int enabled)
457 {
458 unsigned long flags;
459 u32 mask;
460
461 spin_lock_irqsave(&pm_lock, flags);
462 mask = pm_readl(PBB_MASK);
463 if (enabled)
464 mask |= 1 << clk->index;
465 else
466 mask &= ~(1 << clk->index);
467 pm_writel(PBB_MASK, mask);
468 spin_unlock_irqrestore(&pm_lock, flags);
469 }
470
471 static unsigned long pbb_clk_get_rate(struct clk *clk)
472 {
473 unsigned long cksel, shift = 0;
474
475 cksel = pm_readl(CKSEL);
476 if (cksel & PM_BIT(PBBDIV))
477 shift = PM_BFEXT(PBBSEL, cksel) + 1;
478
479 return bus_clk_get_rate(clk, shift);
480 }
481
482 static struct clk cpu_clk = {
483 .name = "cpu",
484 .get_rate = cpu_clk_get_rate,
485 .set_rate = cpu_clk_set_rate,
486 .users = 1,
487 };
488 static struct clk hsb_clk = {
489 .name = "hsb",
490 .parent = &cpu_clk,
491 .get_rate = hsb_clk_get_rate,
492 };
493 static struct clk pba_clk = {
494 .name = "pba",
495 .parent = &hsb_clk,
496 .mode = hsb_clk_mode,
497 .get_rate = pba_clk_get_rate,
498 .index = 1,
499 };
500 static struct clk pbb_clk = {
501 .name = "pbb",
502 .parent = &hsb_clk,
503 .mode = hsb_clk_mode,
504 .get_rate = pbb_clk_get_rate,
505 .users = 1,
506 .index = 2,
507 };
508
509 /* --------------------------------------------------------------------
510 * Generic Clock operations
511 * -------------------------------------------------------------------- */
512
513 static void genclk_mode(struct clk *clk, int enabled)
514 {
515 u32 control;
516
517 control = pm_readl(GCCTRL(clk->index));
518 if (enabled)
519 control |= PM_BIT(CEN);
520 else
521 control &= ~PM_BIT(CEN);
522 pm_writel(GCCTRL(clk->index), control);
523 }
524
525 static unsigned long genclk_get_rate(struct clk *clk)
526 {
527 u32 control;
528 unsigned long div = 1;
529
530 control = pm_readl(GCCTRL(clk->index));
531 if (control & PM_BIT(DIVEN))
532 div = 2 * (PM_BFEXT(DIV, control) + 1);
533
534 return clk->parent->get_rate(clk->parent) / div;
535 }
536
537 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
538 {
539 u32 control;
540 unsigned long parent_rate, actual_rate, div;
541
542 parent_rate = clk->parent->get_rate(clk->parent);
543 control = pm_readl(GCCTRL(clk->index));
544
545 if (rate > 3 * parent_rate / 4) {
546 actual_rate = parent_rate;
547 control &= ~PM_BIT(DIVEN);
548 } else {
549 div = (parent_rate + rate) / (2 * rate) - 1;
550 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
551 actual_rate = parent_rate / (2 * (div + 1));
552 }
553
554 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
555 clk->name, rate, actual_rate);
556
557 if (apply)
558 pm_writel(GCCTRL(clk->index), control);
559
560 return actual_rate;
561 }
562
563 int genclk_set_parent(struct clk *clk, struct clk *parent)
564 {
565 u32 control;
566
567 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
568 clk->name, parent->name, clk->parent->name);
569
570 control = pm_readl(GCCTRL(clk->index));
571
572 if (parent == &osc1 || parent == &pll1)
573 control |= PM_BIT(OSCSEL);
574 else if (parent == &osc0 || parent == &pll0)
575 control &= ~PM_BIT(OSCSEL);
576 else
577 return -EINVAL;
578
579 if (parent == &pll0 || parent == &pll1)
580 control |= PM_BIT(PLLSEL);
581 else
582 control &= ~PM_BIT(PLLSEL);
583
584 pm_writel(GCCTRL(clk->index), control);
585 clk->parent = parent;
586
587 return 0;
588 }
589
590 static void __init genclk_init_parent(struct clk *clk)
591 {
592 u32 control;
593 struct clk *parent;
594
595 BUG_ON(clk->index > 7);
596
597 control = pm_readl(GCCTRL(clk->index));
598 if (control & PM_BIT(OSCSEL))
599 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
600 else
601 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
602
603 clk->parent = parent;
604 }
605
606 static struct resource dw_dmac0_resource[] = {
607 PBMEM(0xff200000),
608 IRQ(2),
609 };
610 DEFINE_DEV(dw_dmac, 0);
611 DEV_CLK(hclk, dw_dmac0, hsb, 10);
612
613 /* --------------------------------------------------------------------
614 * System peripherals
615 * -------------------------------------------------------------------- */
616 static struct resource at32_pm0_resource[] = {
617 {
618 .start = 0xfff00000,
619 .end = 0xfff0007f,
620 .flags = IORESOURCE_MEM,
621 },
622 IRQ(20),
623 };
624
625 static struct resource at32ap700x_rtc0_resource[] = {
626 {
627 .start = 0xfff00080,
628 .end = 0xfff000af,
629 .flags = IORESOURCE_MEM,
630 },
631 IRQ(21),
632 };
633
634 static struct resource at32_wdt0_resource[] = {
635 {
636 .start = 0xfff000b0,
637 .end = 0xfff000cf,
638 .flags = IORESOURCE_MEM,
639 },
640 };
641
642 static struct resource at32_eic0_resource[] = {
643 {
644 .start = 0xfff00100,
645 .end = 0xfff0013f,
646 .flags = IORESOURCE_MEM,
647 },
648 IRQ(19),
649 };
650
651 DEFINE_DEV(at32_pm, 0);
652 DEFINE_DEV(at32ap700x_rtc, 0);
653 DEFINE_DEV(at32_wdt, 0);
654 DEFINE_DEV(at32_eic, 0);
655
656 /*
657 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
658 * is always running.
659 */
660 static struct clk at32_pm_pclk = {
661 .name = "pclk",
662 .dev = &at32_pm0_device.dev,
663 .parent = &pbb_clk,
664 .mode = pbb_clk_mode,
665 .get_rate = pbb_clk_get_rate,
666 .users = 1,
667 .index = 0,
668 };
669
670 static struct resource intc0_resource[] = {
671 PBMEM(0xfff00400),
672 };
673 struct platform_device at32_intc0_device = {
674 .name = "intc",
675 .id = 0,
676 .resource = intc0_resource,
677 .num_resources = ARRAY_SIZE(intc0_resource),
678 };
679 DEV_CLK(pclk, at32_intc0, pbb, 1);
680
681 static struct clk ebi_clk = {
682 .name = "ebi",
683 .parent = &hsb_clk,
684 .mode = hsb_clk_mode,
685 .get_rate = hsb_clk_get_rate,
686 .users = 1,
687 };
688 static struct clk hramc_clk = {
689 .name = "hramc",
690 .parent = &hsb_clk,
691 .mode = hsb_clk_mode,
692 .get_rate = hsb_clk_get_rate,
693 .users = 1,
694 .index = 3,
695 };
696 static struct clk sdramc_clk = {
697 .name = "sdramc_clk",
698 .parent = &pbb_clk,
699 .mode = pbb_clk_mode,
700 .get_rate = pbb_clk_get_rate,
701 .users = 1,
702 .index = 14,
703 };
704
705 static struct resource smc0_resource[] = {
706 PBMEM(0xfff03400),
707 };
708 DEFINE_DEV(smc, 0);
709 DEV_CLK(pclk, smc0, pbb, 13);
710 DEV_CLK(mck, smc0, hsb, 0);
711
712 static struct platform_device pdc_device = {
713 .name = "pdc",
714 .id = 0,
715 };
716 DEV_CLK(hclk, pdc, hsb, 4);
717 DEV_CLK(pclk, pdc, pba, 16);
718
719 static struct clk pico_clk = {
720 .name = "pico",
721 .parent = &cpu_clk,
722 .mode = cpu_clk_mode,
723 .get_rate = cpu_clk_get_rate,
724 .users = 1,
725 };
726
727 /* --------------------------------------------------------------------
728 * HMATRIX
729 * -------------------------------------------------------------------- */
730
731 struct clk at32_hmatrix_clk = {
732 .name = "hmatrix_clk",
733 .parent = &pbb_clk,
734 .mode = pbb_clk_mode,
735 .get_rate = pbb_clk_get_rate,
736 .index = 2,
737 .users = 1,
738 };
739
740 /*
741 * Set bits in the HMATRIX Special Function Register (SFR) used by the
742 * External Bus Interface (EBI). This can be used to enable special
743 * features like CompactFlash support, NAND Flash support, etc. on
744 * certain chipselects.
745 */
746 static inline void set_ebi_sfr_bits(u32 mask)
747 {
748 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
749 }
750
751 /* --------------------------------------------------------------------
752 * Timer/Counter (TC)
753 * -------------------------------------------------------------------- */
754
755 static struct resource at32_tcb0_resource[] = {
756 PBMEM(0xfff00c00),
757 IRQ(22),
758 };
759 static struct platform_device at32_tcb0_device = {
760 .name = "atmel_tcb",
761 .id = 0,
762 .resource = at32_tcb0_resource,
763 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
764 };
765 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
766
767 static struct resource at32_tcb1_resource[] = {
768 PBMEM(0xfff01000),
769 IRQ(23),
770 };
771 static struct platform_device at32_tcb1_device = {
772 .name = "atmel_tcb",
773 .id = 1,
774 .resource = at32_tcb1_resource,
775 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
776 };
777 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
778
779 /* --------------------------------------------------------------------
780 * PIO
781 * -------------------------------------------------------------------- */
782
783 static struct resource pio0_resource[] = {
784 PBMEM(0xffe02800),
785 IRQ(13),
786 };
787 DEFINE_DEV(pio, 0);
788 DEV_CLK(mck, pio0, pba, 10);
789
790 static struct resource pio1_resource[] = {
791 PBMEM(0xffe02c00),
792 IRQ(14),
793 };
794 DEFINE_DEV(pio, 1);
795 DEV_CLK(mck, pio1, pba, 11);
796
797 static struct resource pio2_resource[] = {
798 PBMEM(0xffe03000),
799 IRQ(15),
800 };
801 DEFINE_DEV(pio, 2);
802 DEV_CLK(mck, pio2, pba, 12);
803
804 static struct resource pio3_resource[] = {
805 PBMEM(0xffe03400),
806 IRQ(16),
807 };
808 DEFINE_DEV(pio, 3);
809 DEV_CLK(mck, pio3, pba, 13);
810
811 static struct resource pio4_resource[] = {
812 PBMEM(0xffe03800),
813 IRQ(17),
814 };
815 DEFINE_DEV(pio, 4);
816 DEV_CLK(mck, pio4, pba, 14);
817
818 static int __init system_device_init(void)
819 {
820 platform_device_register(&at32_pm0_device);
821 platform_device_register(&at32_intc0_device);
822 platform_device_register(&at32ap700x_rtc0_device);
823 platform_device_register(&at32_wdt0_device);
824 platform_device_register(&at32_eic0_device);
825 platform_device_register(&smc0_device);
826 platform_device_register(&pdc_device);
827 platform_device_register(&dw_dmac0_device);
828
829 platform_device_register(&at32_tcb0_device);
830 platform_device_register(&at32_tcb1_device);
831
832 platform_device_register(&pio0_device);
833 platform_device_register(&pio1_device);
834 platform_device_register(&pio2_device);
835 platform_device_register(&pio3_device);
836 platform_device_register(&pio4_device);
837
838 return 0;
839 }
840 core_initcall(system_device_init);
841
842 /* --------------------------------------------------------------------
843 * PSIF
844 * -------------------------------------------------------------------- */
845 static struct resource atmel_psif0_resource[] __initdata = {
846 {
847 .start = 0xffe03c00,
848 .end = 0xffe03cff,
849 .flags = IORESOURCE_MEM,
850 },
851 IRQ(18),
852 };
853 static struct clk atmel_psif0_pclk = {
854 .name = "pclk",
855 .parent = &pba_clk,
856 .mode = pba_clk_mode,
857 .get_rate = pba_clk_get_rate,
858 .index = 15,
859 };
860
861 static struct resource atmel_psif1_resource[] __initdata = {
862 {
863 .start = 0xffe03d00,
864 .end = 0xffe03dff,
865 .flags = IORESOURCE_MEM,
866 },
867 IRQ(18),
868 };
869 static struct clk atmel_psif1_pclk = {
870 .name = "pclk",
871 .parent = &pba_clk,
872 .mode = pba_clk_mode,
873 .get_rate = pba_clk_get_rate,
874 .index = 15,
875 };
876
877 struct platform_device *__init at32_add_device_psif(unsigned int id)
878 {
879 struct platform_device *pdev;
880 u32 pin_mask;
881
882 if (!(id == 0 || id == 1))
883 return NULL;
884
885 pdev = platform_device_alloc("atmel_psif", id);
886 if (!pdev)
887 return NULL;
888
889 switch (id) {
890 case 0:
891 pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */
892
893 if (platform_device_add_resources(pdev, atmel_psif0_resource,
894 ARRAY_SIZE(atmel_psif0_resource)))
895 goto err_add_resources;
896 atmel_psif0_pclk.dev = &pdev->dev;
897 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
898 break;
899 case 1:
900 pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */
901
902 if (platform_device_add_resources(pdev, atmel_psif1_resource,
903 ARRAY_SIZE(atmel_psif1_resource)))
904 goto err_add_resources;
905 atmel_psif1_pclk.dev = &pdev->dev;
906 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
907 break;
908 default:
909 return NULL;
910 }
911
912 platform_device_add(pdev);
913 return pdev;
914
915 err_add_resources:
916 platform_device_put(pdev);
917 return NULL;
918 }
919
920 /* --------------------------------------------------------------------
921 * USART
922 * -------------------------------------------------------------------- */
923
924 static struct atmel_uart_data atmel_usart0_data = {
925 .use_dma_tx = 1,
926 .use_dma_rx = 1,
927 };
928 static struct resource atmel_usart0_resource[] = {
929 PBMEM(0xffe00c00),
930 IRQ(6),
931 };
932 DEFINE_DEV_DATA(atmel_usart, 0);
933 DEV_CLK(usart, atmel_usart0, pba, 3);
934
935 static struct atmel_uart_data atmel_usart1_data = {
936 .use_dma_tx = 1,
937 .use_dma_rx = 1,
938 };
939 static struct resource atmel_usart1_resource[] = {
940 PBMEM(0xffe01000),
941 IRQ(7),
942 };
943 DEFINE_DEV_DATA(atmel_usart, 1);
944 DEV_CLK(usart, atmel_usart1, pba, 4);
945
946 static struct atmel_uart_data atmel_usart2_data = {
947 .use_dma_tx = 1,
948 .use_dma_rx = 1,
949 };
950 static struct resource atmel_usart2_resource[] = {
951 PBMEM(0xffe01400),
952 IRQ(8),
953 };
954 DEFINE_DEV_DATA(atmel_usart, 2);
955 DEV_CLK(usart, atmel_usart2, pba, 5);
956
957 static struct atmel_uart_data atmel_usart3_data = {
958 .use_dma_tx = 1,
959 .use_dma_rx = 1,
960 };
961 static struct resource atmel_usart3_resource[] = {
962 PBMEM(0xffe01800),
963 IRQ(9),
964 };
965 DEFINE_DEV_DATA(atmel_usart, 3);
966 DEV_CLK(usart, atmel_usart3, pba, 6);
967
968 static inline void configure_usart0_pins(int flags)
969 {
970 u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
971 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 6);
972 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 7);
973 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 10);
974
975 select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
976 }
977
978 static inline void configure_usart1_pins(int flags)
979 {
980 u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
981 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 19);
982 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 20);
983 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 16);
984
985 select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
986 }
987
988 static inline void configure_usart2_pins(int flags)
989 {
990 u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
991 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 30);
992 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 29);
993 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 28);
994
995 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
996 }
997
998 static inline void configure_usart3_pins(int flags)
999 {
1000 u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
1001 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 16);
1002 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 15);
1003 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 19);
1004
1005 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1006 }
1007
1008 static struct platform_device *__initdata at32_usarts[4];
1009
1010 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1011 {
1012 struct platform_device *pdev;
1013 struct atmel_uart_data *pdata;
1014
1015 switch (hw_id) {
1016 case 0:
1017 pdev = &atmel_usart0_device;
1018 configure_usart0_pins(flags);
1019 break;
1020 case 1:
1021 pdev = &atmel_usart1_device;
1022 configure_usart1_pins(flags);
1023 break;
1024 case 2:
1025 pdev = &atmel_usart2_device;
1026 configure_usart2_pins(flags);
1027 break;
1028 case 3:
1029 pdev = &atmel_usart3_device;
1030 configure_usart3_pins(flags);
1031 break;
1032 default:
1033 return;
1034 }
1035
1036 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1037 /* Addresses in the P4 segment are permanently mapped 1:1 */
1038 struct atmel_uart_data *data = pdev->dev.platform_data;
1039 data->regs = (void __iomem *)pdev->resource[0].start;
1040 }
1041
1042 pdev->id = line;
1043 pdata = pdev->dev.platform_data;
1044 pdata->num = line;
1045 at32_usarts[line] = pdev;
1046 }
1047
1048 struct platform_device *__init at32_add_device_usart(unsigned int id)
1049 {
1050 platform_device_register(at32_usarts[id]);
1051 return at32_usarts[id];
1052 }
1053
1054 void __init at32_setup_serial_console(unsigned int usart_id)
1055 {
1056 #ifdef CONFIG_SERIAL_ATMEL
1057 atmel_default_console_device = at32_usarts[usart_id];
1058 #endif
1059 }
1060
1061 /* --------------------------------------------------------------------
1062 * Ethernet
1063 * -------------------------------------------------------------------- */
1064
1065 #ifdef CONFIG_CPU_AT32AP7000
1066 static struct macb_platform_data macb0_data;
1067 static struct resource macb0_resource[] = {
1068 PBMEM(0xfff01800),
1069 IRQ(25),
1070 };
1071 DEFINE_DEV_DATA(macb, 0);
1072 DEV_CLK(hclk, macb0, hsb, 8);
1073 DEV_CLK(pclk, macb0, pbb, 6);
1074
1075 static struct macb_platform_data macb1_data;
1076 static struct resource macb1_resource[] = {
1077 PBMEM(0xfff01c00),
1078 IRQ(26),
1079 };
1080 DEFINE_DEV_DATA(macb, 1);
1081 DEV_CLK(hclk, macb1, hsb, 9);
1082 DEV_CLK(pclk, macb1, pbb, 7);
1083
1084 struct platform_device *__init
1085 at32_add_device_eth(unsigned int id, struct macb_platform_data *data)
1086 {
1087 struct platform_device *pdev;
1088 u32 pin_mask;
1089
1090 switch (id) {
1091 case 0:
1092 pdev = &macb0_device;
1093
1094 pin_mask = (1 << 3); /* TXD0 */
1095 pin_mask |= (1 << 4); /* TXD1 */
1096 pin_mask |= (1 << 7); /* TXEN */
1097 pin_mask |= (1 << 8); /* TXCK */
1098 pin_mask |= (1 << 9); /* RXD0 */
1099 pin_mask |= (1 << 10); /* RXD1 */
1100 pin_mask |= (1 << 13); /* RXER */
1101 pin_mask |= (1 << 15); /* RXDV */
1102 pin_mask |= (1 << 16); /* MDC */
1103 pin_mask |= (1 << 17); /* MDIO */
1104
1105 if (!data->is_rmii) {
1106 pin_mask |= (1 << 0); /* COL */
1107 pin_mask |= (1 << 1); /* CRS */
1108 pin_mask |= (1 << 2); /* TXER */
1109 pin_mask |= (1 << 5); /* TXD2 */
1110 pin_mask |= (1 << 6); /* TXD3 */
1111 pin_mask |= (1 << 11); /* RXD2 */
1112 pin_mask |= (1 << 12); /* RXD3 */
1113 pin_mask |= (1 << 14); /* RXCK */
1114 #ifndef CONFIG_BOARD_MIMC200
1115 pin_mask |= (1 << 18); /* SPD */
1116 #endif
1117 }
1118
1119 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1120
1121 break;
1122
1123 case 1:
1124 pdev = &macb1_device;
1125
1126 pin_mask = (1 << 13); /* TXD0 */
1127 pin_mask |= (1 << 14); /* TXD1 */
1128 pin_mask |= (1 << 11); /* TXEN */
1129 pin_mask |= (1 << 12); /* TXCK */
1130 pin_mask |= (1 << 10); /* RXD0 */
1131 pin_mask |= (1 << 6); /* RXD1 */
1132 pin_mask |= (1 << 5); /* RXER */
1133 pin_mask |= (1 << 4); /* RXDV */
1134 pin_mask |= (1 << 3); /* MDC */
1135 pin_mask |= (1 << 2); /* MDIO */
1136
1137 #ifndef CONFIG_BOARD_MIMC200
1138 if (!data->is_rmii)
1139 pin_mask |= (1 << 15); /* SPD */
1140 #endif
1141
1142 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1143
1144 if (!data->is_rmii) {
1145 pin_mask = (1 << 19); /* COL */
1146 pin_mask |= (1 << 23); /* CRS */
1147 pin_mask |= (1 << 26); /* TXER */
1148 pin_mask |= (1 << 27); /* TXD2 */
1149 pin_mask |= (1 << 28); /* TXD3 */
1150 pin_mask |= (1 << 29); /* RXD2 */
1151 pin_mask |= (1 << 30); /* RXD3 */
1152 pin_mask |= (1 << 24); /* RXCK */
1153
1154 select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1155 }
1156 break;
1157
1158 default:
1159 return NULL;
1160 }
1161
1162 memcpy(pdev->dev.platform_data, data, sizeof(struct macb_platform_data));
1163 platform_device_register(pdev);
1164
1165 return pdev;
1166 }
1167 #endif
1168
1169 /* --------------------------------------------------------------------
1170 * SPI
1171 * -------------------------------------------------------------------- */
1172 static struct resource atmel_spi0_resource[] = {
1173 PBMEM(0xffe00000),
1174 IRQ(3),
1175 };
1176 DEFINE_DEV(atmel_spi, 0);
1177 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1178
1179 static struct resource atmel_spi1_resource[] = {
1180 PBMEM(0xffe00400),
1181 IRQ(4),
1182 };
1183 DEFINE_DEV(atmel_spi, 1);
1184 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1185
1186 void __init
1187 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
1188 {
1189 /*
1190 * Manage the chipselects as GPIOs, normally using the same pins
1191 * the SPI controller expects; but boards can use other pins.
1192 */
1193 static u8 __initdata spi_pins[][4] = {
1194 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1195 GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
1196 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1197 GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
1198 };
1199 unsigned int pin, mode;
1200
1201 /* There are only 2 SPI controllers */
1202 if (bus_num > 1)
1203 return;
1204
1205 for (; n; n--, b++) {
1206 b->bus_num = bus_num;
1207 if (b->chip_select >= 4)
1208 continue;
1209 pin = (unsigned)b->controller_data;
1210 if (!pin) {
1211 pin = spi_pins[bus_num][b->chip_select];
1212 b->controller_data = (void *)pin;
1213 }
1214 mode = AT32_GPIOF_OUTPUT;
1215 if (!(b->mode & SPI_CS_HIGH))
1216 mode |= AT32_GPIOF_HIGH;
1217 at32_select_gpio(pin, mode);
1218 }
1219 }
1220
1221 struct platform_device *__init
1222 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1223 {
1224 struct platform_device *pdev;
1225 u32 pin_mask;
1226
1227 switch (id) {
1228 case 0:
1229 pdev = &atmel_spi0_device;
1230 pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */
1231
1232 /* pullup MISO so a level is always defined */
1233 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1234 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1235
1236 at32_spi_setup_slaves(0, b, n);
1237 break;
1238
1239 case 1:
1240 pdev = &atmel_spi1_device;
1241 pin_mask = (1 << 1) | (1 << 5); /* MOSI */
1242
1243 /* pullup MISO so a level is always defined */
1244 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1245 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1246
1247 at32_spi_setup_slaves(1, b, n);
1248 break;
1249
1250 default:
1251 return NULL;
1252 }
1253
1254 spi_register_board_info(b, n);
1255 platform_device_register(pdev);
1256 return pdev;
1257 }
1258
1259 /* --------------------------------------------------------------------
1260 * TWI
1261 * -------------------------------------------------------------------- */
1262 static struct resource atmel_twi0_resource[] __initdata = {
1263 PBMEM(0xffe00800),
1264 IRQ(5),
1265 };
1266 static struct clk atmel_twi0_pclk = {
1267 .name = "twi_pclk",
1268 .parent = &pba_clk,
1269 .mode = pba_clk_mode,
1270 .get_rate = pba_clk_get_rate,
1271 .index = 2,
1272 };
1273
1274 struct platform_device *__init at32_add_device_twi(unsigned int id,
1275 struct i2c_board_info *b,
1276 unsigned int n)
1277 {
1278 struct platform_device *pdev;
1279 u32 pin_mask;
1280
1281 if (id != 0)
1282 return NULL;
1283
1284 pdev = platform_device_alloc("atmel_twi", id);
1285 if (!pdev)
1286 return NULL;
1287
1288 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1289 ARRAY_SIZE(atmel_twi0_resource)))
1290 goto err_add_resources;
1291
1292 pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */
1293
1294 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1295
1296 atmel_twi0_pclk.dev = &pdev->dev;
1297
1298 if (b)
1299 i2c_register_board_info(id, b, n);
1300
1301 platform_device_add(pdev);
1302 return pdev;
1303
1304 err_add_resources:
1305 platform_device_put(pdev);
1306 return NULL;
1307 }
1308
1309 /* --------------------------------------------------------------------
1310 * MMC
1311 * -------------------------------------------------------------------- */
1312 static struct resource atmel_mci0_resource[] __initdata = {
1313 PBMEM(0xfff02400),
1314 IRQ(28),
1315 };
1316 static struct clk atmel_mci0_pclk = {
1317 .name = "mci_clk",
1318 .parent = &pbb_clk,
1319 .mode = pbb_clk_mode,
1320 .get_rate = pbb_clk_get_rate,
1321 .index = 9,
1322 };
1323
1324 struct platform_device *__init
1325 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1326 {
1327 struct platform_device *pdev;
1328 struct mci_dma_data *slave;
1329 u32 pioa_mask;
1330 u32 piob_mask;
1331
1332 if (id != 0 || !data)
1333 return NULL;
1334
1335 /* Must have at least one usable slot */
1336 if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1337 return NULL;
1338
1339 pdev = platform_device_alloc("atmel_mci", id);
1340 if (!pdev)
1341 goto fail;
1342
1343 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1344 ARRAY_SIZE(atmel_mci0_resource)))
1345 goto fail;
1346
1347 slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
1348 if (!slave)
1349 goto fail;
1350
1351 slave->sdata.dma_dev = &dw_dmac0_device.dev;
1352 slave->sdata.src_id = 0;
1353 slave->sdata.dst_id = 1;
1354 slave->sdata.src_master = 1;
1355 slave->sdata.dst_master = 0;
1356
1357 data->dma_slave = slave;
1358
1359 if (platform_device_add_data(pdev, data,
1360 sizeof(struct mci_platform_data)))
1361 goto fail_free;
1362
1363 /* CLK line is common to both slots */
1364 pioa_mask = 1 << 10;
1365
1366 switch (data->slot[0].bus_width) {
1367 case 4:
1368 pioa_mask |= 1 << 13; /* DATA1 */
1369 pioa_mask |= 1 << 14; /* DATA2 */
1370 pioa_mask |= 1 << 15; /* DATA3 */
1371 /* fall through */
1372 case 1:
1373 pioa_mask |= 1 << 11; /* CMD */
1374 pioa_mask |= 1 << 12; /* DATA0 */
1375
1376 if (gpio_is_valid(data->slot[0].detect_pin))
1377 at32_select_gpio(data->slot[0].detect_pin, 0);
1378 if (gpio_is_valid(data->slot[0].wp_pin))
1379 at32_select_gpio(data->slot[0].wp_pin, 0);
1380 break;
1381 case 0:
1382 /* Slot is unused */
1383 break;
1384 default:
1385 goto fail_free;
1386 }
1387
1388 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1389 piob_mask = 0;
1390
1391 switch (data->slot[1].bus_width) {
1392 case 4:
1393 piob_mask |= 1 << 8; /* DATA1 */
1394 piob_mask |= 1 << 9; /* DATA2 */
1395 piob_mask |= 1 << 10; /* DATA3 */
1396 /* fall through */
1397 case 1:
1398 piob_mask |= 1 << 6; /* CMD */
1399 piob_mask |= 1 << 7; /* DATA0 */
1400 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1401
1402 if (gpio_is_valid(data->slot[1].detect_pin))
1403 at32_select_gpio(data->slot[1].detect_pin, 0);
1404 if (gpio_is_valid(data->slot[1].wp_pin))
1405 at32_select_gpio(data->slot[1].wp_pin, 0);
1406 break;
1407 case 0:
1408 /* Slot is unused */
1409 break;
1410 default:
1411 if (!data->slot[0].bus_width)
1412 goto fail_free;
1413
1414 data->slot[1].bus_width = 0;
1415 break;
1416 }
1417
1418 atmel_mci0_pclk.dev = &pdev->dev;
1419
1420 platform_device_add(pdev);
1421 return pdev;
1422
1423 fail_free:
1424 kfree(slave);
1425 fail:
1426 data->dma_slave = NULL;
1427 platform_device_put(pdev);
1428 return NULL;
1429 }
1430
1431 /* --------------------------------------------------------------------
1432 * LCDC
1433 * -------------------------------------------------------------------- */
1434 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1435 static struct atmel_lcdfb_pdata atmel_lcdfb0_data;
1436 static struct resource atmel_lcdfb0_resource[] = {
1437 {
1438 .start = 0xff000000,
1439 .end = 0xff000fff,
1440 .flags = IORESOURCE_MEM,
1441 },
1442 IRQ(1),
1443 {
1444 /* Placeholder for pre-allocated fb memory */
1445 .start = 0x00000000,
1446 .end = 0x00000000,
1447 .flags = 0,
1448 },
1449 };
1450 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1451 DEV_CLK(hclk, atmel_lcdfb0, hsb, 7);
1452 static struct clk atmel_lcdfb0_pixclk = {
1453 .name = "lcdc_clk",
1454 .dev = &atmel_lcdfb0_device.dev,
1455 .mode = genclk_mode,
1456 .get_rate = genclk_get_rate,
1457 .set_rate = genclk_set_rate,
1458 .set_parent = genclk_set_parent,
1459 .index = 7,
1460 };
1461
1462 struct platform_device *__init
1463 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_pdata *data,
1464 unsigned long fbmem_start, unsigned long fbmem_len,
1465 u64 pin_mask)
1466 {
1467 struct platform_device *pdev;
1468 struct atmel_lcdfb_pdata *info;
1469 struct fb_monspecs *monspecs;
1470 struct fb_videomode *modedb;
1471 unsigned int modedb_size;
1472 u32 portc_mask, portd_mask, porte_mask;
1473
1474 /*
1475 * Do a deep copy of the fb data, monspecs and modedb. Make
1476 * sure all allocations are done before setting up the
1477 * portmux.
1478 */
1479 monspecs = kmemdup(data->default_monspecs,
1480 sizeof(struct fb_monspecs), GFP_KERNEL);
1481 if (!monspecs)
1482 return NULL;
1483
1484 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1485 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1486 if (!modedb)
1487 goto err_dup_modedb;
1488 monspecs->modedb = modedb;
1489
1490 switch (id) {
1491 case 0:
1492 pdev = &atmel_lcdfb0_device;
1493
1494 if (pin_mask == 0ULL)
1495 /* Default to "full" lcdc control signals and 24bit */
1496 pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1497
1498 /* LCDC on port C */
1499 portc_mask = pin_mask & 0xfff80000;
1500 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1501
1502 /* LCDC on port D */
1503 portd_mask = pin_mask & 0x0003ffff;
1504 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1505
1506 /* LCDC on port E */
1507 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1508 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1509
1510 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1511 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1512 break;
1513
1514 default:
1515 goto err_invalid_id;
1516 }
1517
1518 if (fbmem_len) {
1519 pdev->resource[2].start = fbmem_start;
1520 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1521 pdev->resource[2].flags = IORESOURCE_MEM;
1522 }
1523
1524 info = pdev->dev.platform_data;
1525 memcpy(info, data, sizeof(struct atmel_lcdfb_pdata));
1526 info->default_monspecs = monspecs;
1527
1528 pdev->name = "at32ap-lcdfb";
1529
1530 platform_device_register(pdev);
1531 return pdev;
1532
1533 err_invalid_id:
1534 kfree(modedb);
1535 err_dup_modedb:
1536 kfree(monspecs);
1537 return NULL;
1538 }
1539 #endif
1540
1541 /* --------------------------------------------------------------------
1542 * PWM
1543 * -------------------------------------------------------------------- */
1544 static struct resource atmel_pwm0_resource[] __initdata = {
1545 PBMEM(0xfff01400),
1546 IRQ(24),
1547 };
1548 static struct clk atmel_pwm0_mck = {
1549 .name = "at91sam9rl-pwm",
1550 .parent = &pbb_clk,
1551 .mode = pbb_clk_mode,
1552 .get_rate = pbb_clk_get_rate,
1553 .index = 5,
1554 };
1555
1556 struct platform_device *__init at32_add_device_pwm(u32 mask)
1557 {
1558 struct platform_device *pdev;
1559 u32 pin_mask;
1560
1561 if (!mask)
1562 return NULL;
1563
1564 pdev = platform_device_alloc("at91sam9rl-pwm", 0);
1565 if (!pdev)
1566 return NULL;
1567
1568 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1569 ARRAY_SIZE(atmel_pwm0_resource)))
1570 goto out_free_pdev;
1571
1572 pin_mask = 0;
1573 if (mask & (1 << 0))
1574 pin_mask |= (1 << 28);
1575 if (mask & (1 << 1))
1576 pin_mask |= (1 << 29);
1577 if (pin_mask > 0)
1578 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1579
1580 pin_mask = 0;
1581 if (mask & (1 << 2))
1582 pin_mask |= (1 << 21);
1583 if (mask & (1 << 3))
1584 pin_mask |= (1 << 22);
1585 if (pin_mask > 0)
1586 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1587
1588 atmel_pwm0_mck.dev = &pdev->dev;
1589
1590 platform_device_add(pdev);
1591
1592 return pdev;
1593
1594 out_free_pdev:
1595 platform_device_put(pdev);
1596 return NULL;
1597 }
1598
1599 /* --------------------------------------------------------------------
1600 * SSC
1601 * -------------------------------------------------------------------- */
1602 static struct resource ssc0_resource[] = {
1603 PBMEM(0xffe01c00),
1604 IRQ(10),
1605 };
1606 DEFINE_DEV(ssc, 0);
1607 DEV_CLK(pclk, ssc0, pba, 7);
1608
1609 static struct resource ssc1_resource[] = {
1610 PBMEM(0xffe02000),
1611 IRQ(11),
1612 };
1613 DEFINE_DEV(ssc, 1);
1614 DEV_CLK(pclk, ssc1, pba, 8);
1615
1616 static struct resource ssc2_resource[] = {
1617 PBMEM(0xffe02400),
1618 IRQ(12),
1619 };
1620 DEFINE_DEV(ssc, 2);
1621 DEV_CLK(pclk, ssc2, pba, 9);
1622
1623 struct platform_device *__init
1624 at32_add_device_ssc(unsigned int id, unsigned int flags)
1625 {
1626 struct platform_device *pdev;
1627 u32 pin_mask = 0;
1628
1629 switch (id) {
1630 case 0:
1631 pdev = &ssc0_device;
1632 if (flags & ATMEL_SSC_RF)
1633 pin_mask |= (1 << 21); /* RF */
1634 if (flags & ATMEL_SSC_RK)
1635 pin_mask |= (1 << 22); /* RK */
1636 if (flags & ATMEL_SSC_TK)
1637 pin_mask |= (1 << 23); /* TK */
1638 if (flags & ATMEL_SSC_TF)
1639 pin_mask |= (1 << 24); /* TF */
1640 if (flags & ATMEL_SSC_TD)
1641 pin_mask |= (1 << 25); /* TD */
1642 if (flags & ATMEL_SSC_RD)
1643 pin_mask |= (1 << 26); /* RD */
1644
1645 if (pin_mask > 0)
1646 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1647
1648 break;
1649 case 1:
1650 pdev = &ssc1_device;
1651 if (flags & ATMEL_SSC_RF)
1652 pin_mask |= (1 << 0); /* RF */
1653 if (flags & ATMEL_SSC_RK)
1654 pin_mask |= (1 << 1); /* RK */
1655 if (flags & ATMEL_SSC_TK)
1656 pin_mask |= (1 << 2); /* TK */
1657 if (flags & ATMEL_SSC_TF)
1658 pin_mask |= (1 << 3); /* TF */
1659 if (flags & ATMEL_SSC_TD)
1660 pin_mask |= (1 << 4); /* TD */
1661 if (flags & ATMEL_SSC_RD)
1662 pin_mask |= (1 << 5); /* RD */
1663
1664 if (pin_mask > 0)
1665 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1666
1667 break;
1668 case 2:
1669 pdev = &ssc2_device;
1670 if (flags & ATMEL_SSC_TD)
1671 pin_mask |= (1 << 13); /* TD */
1672 if (flags & ATMEL_SSC_RD)
1673 pin_mask |= (1 << 14); /* RD */
1674 if (flags & ATMEL_SSC_TK)
1675 pin_mask |= (1 << 15); /* TK */
1676 if (flags & ATMEL_SSC_TF)
1677 pin_mask |= (1 << 16); /* TF */
1678 if (flags & ATMEL_SSC_RF)
1679 pin_mask |= (1 << 17); /* RF */
1680 if (flags & ATMEL_SSC_RK)
1681 pin_mask |= (1 << 18); /* RK */
1682
1683 if (pin_mask > 0)
1684 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1685
1686 break;
1687 default:
1688 return NULL;
1689 }
1690
1691 platform_device_register(pdev);
1692 return pdev;
1693 }
1694
1695 /* --------------------------------------------------------------------
1696 * USB Device Controller
1697 * -------------------------------------------------------------------- */
1698 static struct resource usba0_resource[] __initdata = {
1699 {
1700 .start = 0xff300000,
1701 .end = 0xff3fffff,
1702 .flags = IORESOURCE_MEM,
1703 }, {
1704 .start = 0xfff03000,
1705 .end = 0xfff033ff,
1706 .flags = IORESOURCE_MEM,
1707 },
1708 IRQ(31),
1709 };
1710 static struct clk usba0_pclk = {
1711 .name = "pclk",
1712 .parent = &pbb_clk,
1713 .mode = pbb_clk_mode,
1714 .get_rate = pbb_clk_get_rate,
1715 .index = 12,
1716 };
1717 static struct clk usba0_hclk = {
1718 .name = "hclk",
1719 .parent = &hsb_clk,
1720 .mode = hsb_clk_mode,
1721 .get_rate = hsb_clk_get_rate,
1722 .index = 6,
1723 };
1724
1725 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1726 [idx] = { \
1727 .name = nam, \
1728 .index = idx, \
1729 .fifo_size = maxpkt, \
1730 .nr_banks = maxbk, \
1731 .can_dma = dma, \
1732 .can_isoc = isoc, \
1733 }
1734
1735 static struct usba_ep_data at32_usba_ep[] __initdata = {
1736 EP("ep0", 0, 64, 1, 0, 0),
1737 EP("ep1", 1, 512, 2, 1, 1),
1738 EP("ep2", 2, 512, 2, 1, 1),
1739 EP("ep3-int", 3, 64, 3, 1, 0),
1740 EP("ep4-int", 4, 64, 3, 1, 0),
1741 EP("ep5", 5, 1024, 3, 1, 1),
1742 EP("ep6", 6, 1024, 3, 1, 1),
1743 };
1744
1745 #undef EP
1746
1747 struct platform_device *__init
1748 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1749 {
1750 /*
1751 * pdata doesn't have room for any endpoints, so we need to
1752 * append room for the ones we need right after it.
1753 */
1754 struct {
1755 struct usba_platform_data pdata;
1756 struct usba_ep_data ep[7];
1757 } usba_data;
1758 struct platform_device *pdev;
1759
1760 if (id != 0)
1761 return NULL;
1762
1763 pdev = platform_device_alloc("atmel_usba_udc", 0);
1764 if (!pdev)
1765 return NULL;
1766
1767 if (platform_device_add_resources(pdev, usba0_resource,
1768 ARRAY_SIZE(usba0_resource)))
1769 goto out_free_pdev;
1770
1771 if (data) {
1772 usba_data.pdata.vbus_pin = data->vbus_pin;
1773 usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted;
1774 } else {
1775 usba_data.pdata.vbus_pin = -EINVAL;
1776 usba_data.pdata.vbus_pin_inverted = -EINVAL;
1777 }
1778
1779 data = &usba_data.pdata;
1780 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1781 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1782
1783 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1784 goto out_free_pdev;
1785
1786 if (gpio_is_valid(data->vbus_pin))
1787 at32_select_gpio(data->vbus_pin, 0);
1788
1789 usba0_pclk.dev = &pdev->dev;
1790 usba0_hclk.dev = &pdev->dev;
1791
1792 platform_device_add(pdev);
1793
1794 return pdev;
1795
1796 out_free_pdev:
1797 platform_device_put(pdev);
1798 return NULL;
1799 }
1800
1801 /* --------------------------------------------------------------------
1802 * IDE / CompactFlash
1803 * -------------------------------------------------------------------- */
1804 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1805 static struct resource at32_smc_cs4_resource[] __initdata = {
1806 {
1807 .start = 0x04000000,
1808 .end = 0x07ffffff,
1809 .flags = IORESOURCE_MEM,
1810 },
1811 IRQ(~0UL), /* Magic IRQ will be overridden */
1812 };
1813 static struct resource at32_smc_cs5_resource[] __initdata = {
1814 {
1815 .start = 0x20000000,
1816 .end = 0x23ffffff,
1817 .flags = IORESOURCE_MEM,
1818 },
1819 IRQ(~0UL), /* Magic IRQ will be overridden */
1820 };
1821
1822 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1823 unsigned int cs, unsigned int extint)
1824 {
1825 static unsigned int extint_pin_map[4] __initdata = {
1826 (1 << 25),
1827 (1 << 26),
1828 (1 << 27),
1829 (1 << 28),
1830 };
1831 static bool common_pins_initialized __initdata = false;
1832 unsigned int extint_pin;
1833 int ret;
1834 u32 pin_mask;
1835
1836 if (extint >= ARRAY_SIZE(extint_pin_map))
1837 return -EINVAL;
1838 extint_pin = extint_pin_map[extint];
1839
1840 switch (cs) {
1841 case 4:
1842 ret = platform_device_add_resources(pdev,
1843 at32_smc_cs4_resource,
1844 ARRAY_SIZE(at32_smc_cs4_resource));
1845 if (ret)
1846 return ret;
1847
1848 /* NCS4 -> OE_N */
1849 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1850 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1851 break;
1852 case 5:
1853 ret = platform_device_add_resources(pdev,
1854 at32_smc_cs5_resource,
1855 ARRAY_SIZE(at32_smc_cs5_resource));
1856 if (ret)
1857 return ret;
1858
1859 /* NCS5 -> OE_N */
1860 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1861 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1862 break;
1863 default:
1864 return -EINVAL;
1865 }
1866
1867 if (!common_pins_initialized) {
1868 pin_mask = (1 << 19); /* CFCE1 -> CS0_N */
1869 pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */
1870 pin_mask |= (1 << 23); /* CFRNW -> DIR */
1871 pin_mask |= (1 << 24); /* NWAIT <- IORDY */
1872
1873 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1874
1875 common_pins_initialized = true;
1876 }
1877
1878 select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1879
1880 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1881 pdev->resource[1].end = pdev->resource[1].start;
1882
1883 return 0;
1884 }
1885
1886 struct platform_device *__init
1887 at32_add_device_ide(unsigned int id, unsigned int extint,
1888 struct ide_platform_data *data)
1889 {
1890 struct platform_device *pdev;
1891
1892 pdev = platform_device_alloc("at32_ide", id);
1893 if (!pdev)
1894 goto fail;
1895
1896 if (platform_device_add_data(pdev, data,
1897 sizeof(struct ide_platform_data)))
1898 goto fail;
1899
1900 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1901 goto fail;
1902
1903 platform_device_add(pdev);
1904 return pdev;
1905
1906 fail:
1907 platform_device_put(pdev);
1908 return NULL;
1909 }
1910
1911 struct platform_device *__init
1912 at32_add_device_cf(unsigned int id, unsigned int extint,
1913 struct cf_platform_data *data)
1914 {
1915 struct platform_device *pdev;
1916
1917 pdev = platform_device_alloc("at32_cf", id);
1918 if (!pdev)
1919 goto fail;
1920
1921 if (platform_device_add_data(pdev, data,
1922 sizeof(struct cf_platform_data)))
1923 goto fail;
1924
1925 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1926 goto fail;
1927
1928 if (gpio_is_valid(data->detect_pin))
1929 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1930 if (gpio_is_valid(data->reset_pin))
1931 at32_select_gpio(data->reset_pin, 0);
1932 if (gpio_is_valid(data->vcc_pin))
1933 at32_select_gpio(data->vcc_pin, 0);
1934 /* READY is used as extint, so we can't select it as gpio */
1935
1936 platform_device_add(pdev);
1937 return pdev;
1938
1939 fail:
1940 platform_device_put(pdev);
1941 return NULL;
1942 }
1943 #endif
1944
1945 /* --------------------------------------------------------------------
1946 * NAND Flash / SmartMedia
1947 * -------------------------------------------------------------------- */
1948 static struct resource smc_cs3_resource[] __initdata = {
1949 {
1950 .start = 0x0c000000,
1951 .end = 0x0fffffff,
1952 .flags = IORESOURCE_MEM,
1953 }, {
1954 .start = 0xfff03c00,
1955 .end = 0xfff03fff,
1956 .flags = IORESOURCE_MEM,
1957 },
1958 };
1959
1960 struct platform_device *__init
1961 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1962 {
1963 struct platform_device *pdev;
1964
1965 if (id != 0 || !data)
1966 return NULL;
1967
1968 pdev = platform_device_alloc("atmel_nand", id);
1969 if (!pdev)
1970 goto fail;
1971
1972 if (platform_device_add_resources(pdev, smc_cs3_resource,
1973 ARRAY_SIZE(smc_cs3_resource)))
1974 goto fail;
1975
1976 /* For at32ap7000, we use the reset workaround for nand driver */
1977 data->need_reset_workaround = true;
1978
1979 if (platform_device_add_data(pdev, data,
1980 sizeof(struct atmel_nand_data)))
1981 goto fail;
1982
1983 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1984 if (data->enable_pin)
1985 at32_select_gpio(data->enable_pin,
1986 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1987 if (data->rdy_pin)
1988 at32_select_gpio(data->rdy_pin, 0);
1989 if (data->det_pin)
1990 at32_select_gpio(data->det_pin, 0);
1991
1992 platform_device_add(pdev);
1993 return pdev;
1994
1995 fail:
1996 platform_device_put(pdev);
1997 return NULL;
1998 }
1999
2000 /* --------------------------------------------------------------------
2001 * AC97C
2002 * -------------------------------------------------------------------- */
2003 static struct resource atmel_ac97c0_resource[] __initdata = {
2004 PBMEM(0xfff02800),
2005 IRQ(29),
2006 };
2007 static struct clk atmel_ac97c0_pclk = {
2008 .name = "pclk",
2009 .parent = &pbb_clk,
2010 .mode = pbb_clk_mode,
2011 .get_rate = pbb_clk_get_rate,
2012 .index = 10,
2013 };
2014
2015 struct platform_device *__init
2016 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2017 unsigned int flags)
2018 {
2019 struct platform_device *pdev;
2020 struct dw_dma_slave *rx_dws;
2021 struct dw_dma_slave *tx_dws;
2022 struct ac97c_platform_data _data;
2023 u32 pin_mask;
2024
2025 if (id != 0)
2026 return NULL;
2027
2028 pdev = platform_device_alloc("atmel_ac97c", id);
2029 if (!pdev)
2030 return NULL;
2031
2032 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2033 ARRAY_SIZE(atmel_ac97c0_resource)))
2034 goto out_free_resources;
2035
2036 if (!data) {
2037 data = &_data;
2038 memset(data, 0, sizeof(struct ac97c_platform_data));
2039 data->reset_pin = -ENODEV;
2040 }
2041
2042 rx_dws = &data->rx_dws;
2043 tx_dws = &data->tx_dws;
2044
2045 /* Check if DMA slave interface for capture should be configured. */
2046 if (flags & AC97C_CAPTURE) {
2047 rx_dws->dma_dev = &dw_dmac0_device.dev;
2048 rx_dws->src_id = 3;
2049 rx_dws->src_master = 0;
2050 rx_dws->dst_master = 1;
2051 }
2052
2053 /* Check if DMA slave interface for playback should be configured. */
2054 if (flags & AC97C_PLAYBACK) {
2055 tx_dws->dma_dev = &dw_dmac0_device.dev;
2056 tx_dws->dst_id = 4;
2057 tx_dws->src_master = 0;
2058 tx_dws->dst_master = 1;
2059 }
2060
2061 if (platform_device_add_data(pdev, data,
2062 sizeof(struct ac97c_platform_data)))
2063 goto out_free_resources;
2064
2065 /* SDO | SYNC | SCLK | SDI */
2066 pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2067
2068 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2069
2070 if (gpio_is_valid(data->reset_pin))
2071 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2072 | AT32_GPIOF_HIGH);
2073
2074 atmel_ac97c0_pclk.dev = &pdev->dev;
2075
2076 platform_device_add(pdev);
2077 return pdev;
2078
2079 out_free_resources:
2080 platform_device_put(pdev);
2081 return NULL;
2082 }
2083
2084 /* --------------------------------------------------------------------
2085 * ABDAC
2086 * -------------------------------------------------------------------- */
2087 static struct resource abdac0_resource[] __initdata = {
2088 PBMEM(0xfff02000),
2089 IRQ(27),
2090 };
2091 static struct clk abdac0_pclk = {
2092 .name = "pclk",
2093 .parent = &pbb_clk,
2094 .mode = pbb_clk_mode,
2095 .get_rate = pbb_clk_get_rate,
2096 .index = 8,
2097 };
2098 static struct clk abdac0_sample_clk = {
2099 .name = "sample_clk",
2100 .mode = genclk_mode,
2101 .get_rate = genclk_get_rate,
2102 .set_rate = genclk_set_rate,
2103 .set_parent = genclk_set_parent,
2104 .index = 6,
2105 };
2106
2107 struct platform_device *__init
2108 at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2109 {
2110 struct platform_device *pdev;
2111 struct dw_dma_slave *dws;
2112 u32 pin_mask;
2113
2114 if (id != 0 || !data)
2115 return NULL;
2116
2117 pdev = platform_device_alloc("atmel_abdac", id);
2118 if (!pdev)
2119 return NULL;
2120
2121 if (platform_device_add_resources(pdev, abdac0_resource,
2122 ARRAY_SIZE(abdac0_resource)))
2123 goto out_free_resources;
2124
2125 dws = &data->dws;
2126
2127 dws->dma_dev = &dw_dmac0_device.dev;
2128 dws->dst_id = 2;
2129 dws->src_master = 0;
2130 dws->dst_master = 1;
2131
2132 if (platform_device_add_data(pdev, data,
2133 sizeof(struct atmel_abdac_pdata)))
2134 goto out_free_resources;
2135
2136 pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */
2137 pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */
2138
2139 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2140
2141 abdac0_pclk.dev = &pdev->dev;
2142 abdac0_sample_clk.dev = &pdev->dev;
2143
2144 platform_device_add(pdev);
2145 return pdev;
2146
2147 out_free_resources:
2148 platform_device_put(pdev);
2149 return NULL;
2150 }
2151
2152 /* --------------------------------------------------------------------
2153 * GCLK
2154 * -------------------------------------------------------------------- */
2155 static struct clk gclk0 = {
2156 .name = "gclk0",
2157 .mode = genclk_mode,
2158 .get_rate = genclk_get_rate,
2159 .set_rate = genclk_set_rate,
2160 .set_parent = genclk_set_parent,
2161 .index = 0,
2162 };
2163 static struct clk gclk1 = {
2164 .name = "gclk1",
2165 .mode = genclk_mode,
2166 .get_rate = genclk_get_rate,
2167 .set_rate = genclk_set_rate,
2168 .set_parent = genclk_set_parent,
2169 .index = 1,
2170 };
2171 static struct clk gclk2 = {
2172 .name = "gclk2",
2173 .mode = genclk_mode,
2174 .get_rate = genclk_get_rate,
2175 .set_rate = genclk_set_rate,
2176 .set_parent = genclk_set_parent,
2177 .index = 2,
2178 };
2179 static struct clk gclk3 = {
2180 .name = "gclk3",
2181 .mode = genclk_mode,
2182 .get_rate = genclk_get_rate,
2183 .set_rate = genclk_set_rate,
2184 .set_parent = genclk_set_parent,
2185 .index = 3,
2186 };
2187 static struct clk gclk4 = {
2188 .name = "gclk4",
2189 .mode = genclk_mode,
2190 .get_rate = genclk_get_rate,
2191 .set_rate = genclk_set_rate,
2192 .set_parent = genclk_set_parent,
2193 .index = 4,
2194 };
2195
2196 static __initdata struct clk *init_clocks[] = {
2197 &osc32k,
2198 &osc0,
2199 &osc1,
2200 &pll0,
2201 &pll1,
2202 &cpu_clk,
2203 &hsb_clk,
2204 &pba_clk,
2205 &pbb_clk,
2206 &at32_pm_pclk,
2207 &at32_intc0_pclk,
2208 &at32_hmatrix_clk,
2209 &ebi_clk,
2210 &hramc_clk,
2211 &sdramc_clk,
2212 &smc0_pclk,
2213 &smc0_mck,
2214 &pdc_hclk,
2215 &pdc_pclk,
2216 &dw_dmac0_hclk,
2217 &pico_clk,
2218 &pio0_mck,
2219 &pio1_mck,
2220 &pio2_mck,
2221 &pio3_mck,
2222 &pio4_mck,
2223 &at32_tcb0_t0_clk,
2224 &at32_tcb1_t0_clk,
2225 &atmel_psif0_pclk,
2226 &atmel_psif1_pclk,
2227 &atmel_usart0_usart,
2228 &atmel_usart1_usart,
2229 &atmel_usart2_usart,
2230 &atmel_usart3_usart,
2231 &atmel_pwm0_mck,
2232 #if defined(CONFIG_CPU_AT32AP7000)
2233 &macb0_hclk,
2234 &macb0_pclk,
2235 &macb1_hclk,
2236 &macb1_pclk,
2237 #endif
2238 &atmel_spi0_spi_clk,
2239 &atmel_spi1_spi_clk,
2240 &atmel_twi0_pclk,
2241 &atmel_mci0_pclk,
2242 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2243 &atmel_lcdfb0_hclk,
2244 &atmel_lcdfb0_pixclk,
2245 #endif
2246 &ssc0_pclk,
2247 &ssc1_pclk,
2248 &ssc2_pclk,
2249 &usba0_hclk,
2250 &usba0_pclk,
2251 &atmel_ac97c0_pclk,
2252 &abdac0_pclk,
2253 &abdac0_sample_clk,
2254 &gclk0,
2255 &gclk1,
2256 &gclk2,
2257 &gclk3,
2258 &gclk4,
2259 };
2260
2261 void __init setup_platform(void)
2262 {
2263 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2264 int i;
2265
2266 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2267 main_clock = &pll0;
2268 cpu_clk.parent = &pll0;
2269 } else {
2270 main_clock = &osc0;
2271 cpu_clk.parent = &osc0;
2272 }
2273
2274 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2275 pll0.parent = &osc1;
2276 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2277 pll1.parent = &osc1;
2278
2279 genclk_init_parent(&gclk0);
2280 genclk_init_parent(&gclk1);
2281 genclk_init_parent(&gclk2);
2282 genclk_init_parent(&gclk3);
2283 genclk_init_parent(&gclk4);
2284 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2285 genclk_init_parent(&atmel_lcdfb0_pixclk);
2286 #endif
2287 genclk_init_parent(&abdac0_sample_clk);
2288
2289 /*
2290 * Build initial dynamic clock list by registering all clocks
2291 * from the array.
2292 * At the same time, turn on all clocks that have at least one
2293 * user already, and turn off everything else. We only do this
2294 * for module clocks, and even though it isn't particularly
2295 * pretty to check the address of the mode function, it should
2296 * do the trick...
2297 */
2298 for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2299 struct clk *clk = init_clocks[i];
2300
2301 /* first, register clock */
2302 at32_clk_register(clk);
2303
2304 if (clk->users == 0)
2305 continue;
2306
2307 if (clk->mode == &cpu_clk_mode)
2308 cpu_mask |= 1 << clk->index;
2309 else if (clk->mode == &hsb_clk_mode)
2310 hsb_mask |= 1 << clk->index;
2311 else if (clk->mode == &pba_clk_mode)
2312 pba_mask |= 1 << clk->index;
2313 else if (clk->mode == &pbb_clk_mode)
2314 pbb_mask |= 1 << clk->index;
2315 }
2316
2317 pm_writel(CPU_MASK, cpu_mask);
2318 pm_writel(HSB_MASK, hsb_mask);
2319 pm_writel(PBA_MASK, pba_mask);
2320 pm_writel(PBB_MASK, pbb_mask);
2321
2322 /* Initialize the port muxes */
2323 at32_init_pio(&pio0_device);
2324 at32_init_pio(&pio1_device);
2325 at32_init_pio(&pio2_device);
2326 at32_init_pio(&pio3_device);
2327 at32_init_pio(&pio4_device);
2328 }
2329
2330 struct gen_pool *sram_pool;
2331
2332 static int __init sram_init(void)
2333 {
2334 struct gen_pool *pool;
2335
2336 /* 1KiB granularity */
2337 pool = gen_pool_create(10, -1);
2338 if (!pool)
2339 goto fail;
2340
2341 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2342 goto err_pool_add;
2343
2344 sram_pool = pool;
2345 return 0;
2346
2347 err_pool_add:
2348 gen_pool_destroy(pool);
2349 fail:
2350 pr_err("Failed to create SRAM pool\n");
2351 return -ENOMEM;
2352 }
2353 core_initcall(sram_init);
Linux with added FPC-III support