1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2010 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #include <asm/octeon/octeon.h>
30 enum octeon_feature_bits __octeon_feature_bits __read_mostly
;
31 EXPORT_SYMBOL_GPL(__octeon_feature_bits
);
34 * Read a byte of fuse data
35 * @byte_addr: address to read
37 * Returns fuse value: 0 or 1
39 static uint8_t __init
cvmx_fuse_read_byte(int byte_addr
)
41 union cvmx_mio_fus_rcmd read_cmd
;
44 read_cmd
.s
.addr
= byte_addr
;
46 cvmx_write_csr(CVMX_MIO_FUS_RCMD
, read_cmd
.u64
);
47 while ((read_cmd
.u64
= cvmx_read_csr(CVMX_MIO_FUS_RCMD
))
50 return read_cmd
.s
.dat
;
54 * Version of octeon_model_get_string() that takes buffer as argument,
55 * as running early in u-boot static/global variables don't work when
58 static const char *__init
octeon_model_get_string_buffer(uint32_t chip_id
,
62 const char *core_model
;
66 union cvmx_l2d_fus3 fus3
;
68 union cvmx_mio_fus_dat2 fus_dat2
;
69 union cvmx_mio_fus_dat3 fus_dat3
;
71 uint32_t fuse_data
= 0;
74 if (!OCTEON_IS_MODEL(OCTEON_CN6XXX
))
75 fus3
.u64
= cvmx_read_csr(CVMX_L2D_FUS3
);
76 fus_dat2
.u64
= cvmx_read_csr(CVMX_MIO_FUS_DAT2
);
77 fus_dat3
.u64
= cvmx_read_csr(CVMX_MIO_FUS_DAT3
);
78 num_cores
= cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE
));
80 /* Make sure the non existent devices look disabled */
81 switch ((chip_id
>> 8) & 0xff) {
84 fus_dat3
.s
.nodfa_dte
= 1;
87 case 4: /* CN57XX or CN56XX */
88 fus_dat3
.s
.nodfa_dte
= 1;
94 /* Make a guess at the suffix */
95 /* NSP = everything */
97 /* SCP = No DFA, No zip */
98 /* CP = No DFA, No crypto, No zip */
99 if (fus_dat3
.s
.nodfa_dte
) {
100 if (fus_dat2
.s
.nocrypto
)
104 } else if (fus_dat2
.s
.nocrypto
)
109 if (!fus_dat2
.s
.nocrypto
)
110 __octeon_feature_bits
|= OCTEON_HAS_CRYPTO
;
113 * Assume pass number is encoded using <5:3><2:0>. Exceptions
114 * will be fixed later.
116 sprintf(pass
, "%d.%d", (int)((chip_id
>> 3) & 7) + 1, (int)chip_id
& 7);
119 * Use the number of cores to determine the last 2 digits of
120 * the model number. There are some exceptions that are fixed
183 /* Now figure out the family, the first two digits */
184 switch ((chip_id
>> 8) & 0xff) {
185 case 0: /* CN38XX, CN37XX or CN36XX */
186 if (fus3
.cn38xx
.crip_512k
) {
188 * For some unknown reason, the 16 core one is
189 * called 37 instead of 36.
198 * This series of chips didn't follow the standard
201 switch (chip_id
& 0xf) {
216 case 1: /* CN31XX or CN3020 */
217 if ((chip_id
& 0x10) || fus3
.cn31xx
.crip_128k
)
222 * This series of chips didn't follow the standard
225 switch (chip_id
& 0xf) {
237 case 2: /* CN3010 or CN3005 */
239 /* A chip with half cache is an 05 */
240 if (fus3
.cn30xx
.crip_64k
)
243 * This series of chips didn't follow the standard
246 switch (chip_id
& 0xf) {
260 /* Special case. 4 core, half cache (CP with half cache) */
261 if ((num_cores
== 4) && fus3
.cn58xx
.crip_1024k
&& !strncmp(suffix
, "CP", 2))
264 /* Pass 1 uses different encodings for pass numbers */
265 if ((chip_id
& 0xFF) < 0x8) {
266 switch (chip_id
& 0x3) {
282 case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */
283 if (fus_dat2
.cn56xx
.raid_en
) {
284 if (fus3
.cn56xx
.crip_1024k
)
288 if (fus_dat2
.cn56xx
.nocrypto
)
293 if (fus_dat2
.cn56xx
.nocrypto
)
297 if (fus_dat3
.s
.nozip
)
300 if (fus_dat3
.s
.bar2_en
)
303 if (fus3
.cn56xx
.crip_1024k
)
313 if (fus3
.cn52xx
.crip_256k
)
318 case 0x93: /* CN61XX */
320 if (fus_dat2
.cn61xx
.nocrypto
&& fus_dat2
.cn61xx
.dorm_crypto
)
322 if (fus_dat2
.cn61xx
.nocrypto
)
324 else if (fus_dat2
.cn61xx
.dorm_crypto
)
326 else if (fus_dat3
.cn61xx
.nozip
)
329 case 0x90: /* CN63XX */
331 if (fus_dat3
.s
.l2c_crip
== 2)
333 if (num_cores
== 6) /* Other core counts match generic */
335 if (fus_dat2
.cn63xx
.nocrypto
)
337 else if (fus_dat2
.cn63xx
.dorm_crypto
)
339 else if (fus_dat3
.cn63xx
.nozip
)
344 case 0x92: /* CN66XX */
346 if (num_cores
== 6) /* Other core counts match generic */
348 if (fus_dat2
.cn66xx
.nocrypto
&& fus_dat2
.cn66xx
.dorm_crypto
)
350 if (fus_dat2
.cn66xx
.nocrypto
)
352 else if (fus_dat2
.cn66xx
.dorm_crypto
)
354 else if (fus_dat3
.cn66xx
.nozip
)
359 case 0x91: /* CN68XX */
361 if (fus_dat2
.cn68xx
.nocrypto
&& fus_dat3
.cn68xx
.nozip
)
363 else if (fus_dat2
.cn68xx
.dorm_crypto
)
365 else if (fus_dat3
.cn68xx
.nozip
)
367 else if (fus_dat2
.cn68xx
.nocrypto
)
380 clock_mhz
= octeon_get_clock_rate() / 1000000;
381 if (family
[0] != '3') {
382 int fuse_base
= 384 / 8;
383 if (family
[0] == '6')
386 /* Check for model in fuses, overrides normal decode */
387 /* This is _not_ valid for Octeon CN3XXX models */
388 fuse_data
|= cvmx_fuse_read_byte(fuse_base
+ 3);
389 fuse_data
= fuse_data
<< 8;
390 fuse_data
|= cvmx_fuse_read_byte(fuse_base
+ 2);
391 fuse_data
= fuse_data
<< 8;
392 fuse_data
|= cvmx_fuse_read_byte(fuse_base
+ 1);
393 fuse_data
= fuse_data
<< 8;
394 fuse_data
|= cvmx_fuse_read_byte(fuse_base
);
395 if (fuse_data
& 0x7ffff) {
396 int model
= fuse_data
& 0x3fff;
397 int suffix
= (fuse_data
>> 14) & 0x1f;
398 if (suffix
&& model
) {
399 /* Have both number and suffix in fuses, so both */
400 sprintf(fuse_model
, "%d%c", model
, 'A' + suffix
- 1);
403 } else if (suffix
&& !model
) {
404 /* Only have suffix, so add suffix to 'normal' model number */
405 sprintf(fuse_model
, "%s%c", core_model
, 'A' + suffix
- 1);
406 core_model
= fuse_model
;
408 /* Don't have suffix, so just use model from fuses */
409 sprintf(fuse_model
, "%d", model
);
415 sprintf(buffer
, "CN%s%sp%s-%d-%s", family
, core_model
, pass
, clock_mhz
, suffix
);
420 * Given the chip processor ID from COP0, this function returns a
421 * string representing the chip model number. The string is of the
422 * form CNXXXXpX.X-FREQ-SUFFIX.
423 * - XXXX = The chip model number
424 * - X.X = Chip pass number
425 * - FREQ = Current frequency in Mhz
426 * - SUFFIX = NSP, EXP, SCP, SSP, or CP
430 * Returns Model string
432 const char *__init
octeon_model_get_string(uint32_t chip_id
)
434 static char buffer
[32];
435 return octeon_model_get_string_buffer(chip_id
, buffer
);