arch/mips/include/uapi/asm/inst.h

   1 /*
   2  * Format of an instruction in memory.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1996, 2000 by Ralf Baechle
   9  * Copyright (C) 2006 by Thiemo Seufer
  10  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
  11  * Copyright (C) 2014 Imagination Technologies Ltd.
  12  */
  13 #ifndef _UAPI_ASM_INST_H
  14 #define _UAPI_ASM_INST_H
  15
  16 #include <asm/bitfield.h>
  17
  18 /*
  19  * Major opcodes; before MIPS IV cop1x was called cop3.
  20  */
  21 enum major_op {
  22         spec_op, bcond_op, j_op, jal_op,
  23         beq_op, bne_op, blez_op, bgtz_op,
  24         addi_op, cbcond0_op = addi_op, addiu_op, slti_op, sltiu_op,
  25         andi_op, ori_op, xori_op, lui_op,
  26         cop0_op, cop1_op, cop2_op, cop1x_op,
  27         beql_op, bnel_op, blezl_op, bgtzl_op,
  28         daddi_op, cbcond1_op = daddi_op, daddiu_op, ldl_op, ldr_op,
  29         spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op,
  30         lb_op, lh_op, lwl_op, lw_op,
  31         lbu_op, lhu_op, lwr_op, lwu_op,
  32         sb_op, sh_op, swl_op, sw_op,
  33         sdl_op, sdr_op, swr_op, cache_op,
  34         ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
  35         lld_op, ldc1_op, ldc2_op, beqzcjic_op = ldc2_op, ld_op,
  36         sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
  37         scd_op, sdc1_op, sdc2_op, bnezcjialc_op = sdc2_op, sd_op
  38 };
  39
  40 /*
  41  * func field of spec opcode.
  42  */
  43 enum spec_op {
  44         sll_op, movc_op, srl_op, sra_op,
  45         sllv_op, pmon_op, srlv_op, srav_op,
  46         jr_op, jalr_op, movz_op, movn_op,
  47         syscall_op, break_op, spim_op, sync_op,
  48         mfhi_op, mthi_op, mflo_op, mtlo_op,
  49         dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
  50         mult_op, multu_op, div_op, divu_op,
  51         dmult_op, dmultu_op, ddiv_op, ddivu_op,
  52         add_op, addu_op, sub_op, subu_op,
  53         and_op, or_op, xor_op, nor_op,
  54         spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
  55         dadd_op, daddu_op, dsub_op, dsubu_op,
  56         tge_op, tgeu_op, tlt_op, tltu_op,
  57         teq_op, spec5_unused_op, tne_op, spec6_unused_op,
  58         dsll_op, spec7_unused_op, dsrl_op, dsra_op,
  59         dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
  60 };
  61
  62 /*
  63  * func field of spec2 opcode.
  64  */
  65 enum spec2_op {
  66         madd_op, maddu_op, mul_op, spec2_3_unused_op,
  67         msub_op, msubu_op, /* more unused ops */
  68         clz_op = 0x20, clo_op,
  69         dclz_op = 0x24, dclo_op,
  70         sdbpp_op = 0x3f
  71 };
  72
  73 /*
  74  * func field of spec3 opcode.
  75  */
  76 enum spec3_op {
  77         ext_op, dextm_op, dextu_op, dext_op,
  78         ins_op, dinsm_op, dinsu_op, dins_op,
  79         yield_op  = 0x09, lx_op     = 0x0a,
  80         lwle_op   = 0x19, lwre_op   = 0x1a,
  81         cachee_op = 0x1b, sbe_op    = 0x1c,
  82         she_op    = 0x1d, sce_op    = 0x1e,
  83         swe_op    = 0x1f, bshfl_op  = 0x20,
  84         swle_op   = 0x21, swre_op   = 0x22,
  85         prefe_op  = 0x23, dbshfl_op = 0x24,
  86         cache6_op = 0x25, sc6_op    = 0x26,
  87         scd6_op   = 0x27, lbue_op   = 0x28,
  88         lhue_op   = 0x29, lbe_op    = 0x2c,
  89         lhe_op    = 0x2d, lle_op    = 0x2e,
  90         lwe_op    = 0x2f, pref6_op  = 0x35,
  91         ll6_op    = 0x36, lld6_op   = 0x37,
  92         rdhwr_op  = 0x3b
  93 };
  94
  95 /*
  96  * rt field of bcond opcodes.
  97  */
  98 enum rt_op {
  99         bltz_op, bgez_op, bltzl_op, bgezl_op,
 100         spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
 101         tgei_op, tgeiu_op, tlti_op, tltiu_op,
 102         teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
 103         bltzal_op, bgezal_op, bltzall_op, bgezall_op,
 104         rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
 105         rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
 106         bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
 107 };
 108
 109 /*
 110  * rs field of cop opcodes.
 111  */
 112 enum cop_op {
 113         mfc_op        = 0x00, dmfc_op       = 0x01,
 114         cfc_op        = 0x02, mfhc0_op      = 0x02,
 115         mfhc_op       = 0x03, mtc_op        = 0x04,
 116         dmtc_op       = 0x05, ctc_op        = 0x06,
 117         mthc0_op      = 0x06, mthc_op       = 0x07,
 118         bc_op         = 0x08, bc1eqz_op     = 0x09,
 119         bc1nez_op     = 0x0d, cop_op        = 0x10,
 120         copm_op       = 0x18
 121 };
 122
 123 /*
 124  * rt field of cop.bc_op opcodes
 125  */
 126 enum bcop_op {
 127         bcf_op, bct_op, bcfl_op, bctl_op
 128 };
 129
 130 /*
 131  * func field of cop0 coi opcodes.
 132  */
 133 enum cop0_coi_func {
 134         tlbr_op       = 0x01, tlbwi_op      = 0x02,
 135         tlbwr_op      = 0x06, tlbp_op       = 0x08,
 136         rfe_op        = 0x10, eret_op       = 0x18,
 137         wait_op       = 0x20,
 138 };
 139
 140 /*
 141  * func field of cop0 com opcodes.
 142  */
 143 enum cop0_com_func {
 144         tlbr1_op      = 0x01, tlbw_op       = 0x02,
 145         tlbp1_op      = 0x08, dctr_op       = 0x09,
 146         dctw_op       = 0x0a
 147 };
 148
 149 /*
 150  * fmt field of cop1 opcodes.
 151  */
 152 enum cop1_fmt {
 153         s_fmt, d_fmt, e_fmt, q_fmt,
 154         w_fmt, l_fmt
 155 };
 156
 157 /*
 158  * func field of cop1 instructions using d, s or w format.
 159  */
 160 enum cop1_sdw_func {
 161         fadd_op      =  0x00, fsub_op      =  0x01,
 162         fmul_op      =  0x02, fdiv_op      =  0x03,
 163         fsqrt_op     =  0x04, fabs_op      =  0x05,
 164         fmov_op      =  0x06, fneg_op      =  0x07,
 165         froundl_op   =  0x08, ftruncl_op   =  0x09,
 166         fceill_op    =  0x0a, ffloorl_op   =  0x0b,
 167         fround_op    =  0x0c, ftrunc_op    =  0x0d,
 168         fceil_op     =  0x0e, ffloor_op    =  0x0f,
 169         fmovc_op     =  0x11, fmovz_op     =  0x12,
 170         fmovn_op     =  0x13, fseleqz_op   =  0x14,
 171         frecip_op    =  0x15, frsqrt_op    =  0x16,
 172         fselnez_op   =  0x17, fmaddf_op    =  0x18,
 173         fmsubf_op    =  0x19, frint_op     =  0x1a,
 174         fclass_op    =  0x1b, fmin_op      =  0x1c,
 175         fmina_op     =  0x1d, fmax_op      =  0x1e,
 176         fmaxa_op     =  0x1f, fcvts_op     =  0x20,
 177         fcvtd_op     =  0x21, fcvte_op     =  0x22,
 178         fcvtw_op     =  0x24, fcvtl_op     =  0x25,
 179         fcmp_op      =  0x30
 180 };
 181
 182 /*
 183  * func field of cop1x opcodes (MIPS IV).
 184  */
 185 enum cop1x_func {
 186         lwxc1_op     =  0x00, ldxc1_op     =  0x01,
 187         swxc1_op     =  0x08, sdxc1_op     =  0x09,
 188         pfetch_op    =  0x0f, madd_s_op    =  0x20,
 189         madd_d_op    =  0x21, madd_e_op    =  0x22,
 190         msub_s_op    =  0x28, msub_d_op    =  0x29,
 191         msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
 192         nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
 193         nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
 194         nmsub_e_op   =  0x3a
 195 };
 196
 197 /*
 198  * func field for mad opcodes (MIPS IV).
 199  */
 200 enum mad_func {
 201         madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
 202         nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
 203 };
 204
 205 /*
 206  * func field for special3 lx opcodes (Cavium Octeon).
 207  */
 208 enum lx_func {
 209         lwx_op  = 0x00,
 210         lhx_op  = 0x04,
 211         lbux_op = 0x06,
 212         ldx_op  = 0x08,
 213         lwux_op = 0x10,
 214         lhux_op = 0x14,
 215         lbx_op  = 0x16,
 216 };
 217
 218 /*
 219  * BSHFL opcodes
 220  */
 221 enum bshfl_func {
 222         wsbh_op = 0x2,
 223         dshd_op = 0x5,
 224         seb_op  = 0x10,
 225         seh_op  = 0x18,
 226 };
 227
 228 /*
 229  * func field for MSA MI10 format.
 230  */
 231 enum msa_mi10_func {
 232         msa_ld_op = 8,
 233         msa_st_op = 9,
 234 };
 235
 236 /*
 237  * MSA 2 bit format fields.
 238  */
 239 enum msa_2b_fmt {
 240         msa_fmt_b = 0,
 241         msa_fmt_h = 1,
 242         msa_fmt_w = 2,
 243         msa_fmt_d = 3,
 244 };
 245
 246 /*
 247  * (microMIPS) Major opcodes.
 248  */
 249 enum mm_major_op {
 250         mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
 251         mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
 252         mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
 253         mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
 254         mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
 255         mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
 256         mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
 257         mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
 258         mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
 259         mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
 260         mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
 261         mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
 262         mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
 263         mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
 264         mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
 265         mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
 266 };
 267
 268 /*
 269  * (microMIPS) POOL32I minor opcodes.
 270  */
 271 enum mm_32i_minor_op {
 272         mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
 273         mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
 274         mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
 275         mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
 276         mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
 277         mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
 278         mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
 279         mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
 280         mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
 281 };
 282
 283 /*
 284  * (microMIPS) POOL32A minor opcodes.
 285  */
 286 enum mm_32a_minor_op {
 287         mm_sll32_op = 0x000,
 288         mm_ins_op = 0x00c,
 289         mm_sllv32_op = 0x010,
 290         mm_ext_op = 0x02c,
 291         mm_pool32axf_op = 0x03c,
 292         mm_srl32_op = 0x040,
 293         mm_sra_op = 0x080,
 294         mm_srlv32_op = 0x090,
 295         mm_rotr_op = 0x0c0,
 296         mm_lwxs_op = 0x118,
 297         mm_addu32_op = 0x150,
 298         mm_subu32_op = 0x1d0,
 299         mm_wsbh_op = 0x1ec,
 300         mm_mul_op = 0x210,
 301         mm_and_op = 0x250,
 302         mm_or32_op = 0x290,
 303         mm_xor32_op = 0x310,
 304         mm_slt_op = 0x350,
 305         mm_sltu_op = 0x390,
 306 };
 307
 308 /*
 309  * (microMIPS) POOL32B functions.
 310  */
 311 enum mm_32b_func {
 312         mm_lwc2_func = 0x0,
 313         mm_lwp_func = 0x1,
 314         mm_ldc2_func = 0x2,
 315         mm_ldp_func = 0x4,
 316         mm_lwm32_func = 0x5,
 317         mm_cache_func = 0x6,
 318         mm_ldm_func = 0x7,
 319         mm_swc2_func = 0x8,
 320         mm_swp_func = 0x9,
 321         mm_sdc2_func = 0xa,
 322         mm_sdp_func = 0xc,
 323         mm_swm32_func = 0xd,
 324         mm_sdm_func = 0xf,
 325 };
 326
 327 /*
 328  * (microMIPS) POOL32C functions.
 329  */
 330 enum mm_32c_func {
 331         mm_pref_func = 0x2,
 332         mm_ll_func = 0x3,
 333         mm_swr_func = 0x9,
 334         mm_sc_func = 0xb,
 335         mm_lwu_func = 0xe,
 336 };
 337
 338 /*
 339  * (microMIPS) POOL32AXF minor opcodes.
 340  */
 341 enum mm_32axf_minor_op {
 342         mm_mfc0_op = 0x003,
 343         mm_mtc0_op = 0x00b,
 344         mm_tlbp_op = 0x00d,
 345         mm_mfhi32_op = 0x035,
 346         mm_jalr_op = 0x03c,
 347         mm_tlbr_op = 0x04d,
 348         mm_mflo32_op = 0x075,
 349         mm_jalrhb_op = 0x07c,
 350         mm_tlbwi_op = 0x08d,
 351         mm_tlbwr_op = 0x0cd,
 352         mm_jalrs_op = 0x13c,
 353         mm_jalrshb_op = 0x17c,
 354         mm_sync_op = 0x1ad,
 355         mm_syscall_op = 0x22d,
 356         mm_wait_op = 0x24d,
 357         mm_eret_op = 0x3cd,
 358         mm_divu_op = 0x5dc,
 359 };
 360
 361 /*
 362  * (microMIPS) POOL32F minor opcodes.
 363  */
 364 enum mm_32f_minor_op {
 365         mm_32f_00_op = 0x00,
 366         mm_32f_01_op = 0x01,
 367         mm_32f_02_op = 0x02,
 368         mm_32f_10_op = 0x08,
 369         mm_32f_11_op = 0x09,
 370         mm_32f_12_op = 0x0a,
 371         mm_32f_20_op = 0x10,
 372         mm_32f_30_op = 0x18,
 373         mm_32f_40_op = 0x20,
 374         mm_32f_41_op = 0x21,
 375         mm_32f_42_op = 0x22,
 376         mm_32f_50_op = 0x28,
 377         mm_32f_51_op = 0x29,
 378         mm_32f_52_op = 0x2a,
 379         mm_32f_60_op = 0x30,
 380         mm_32f_70_op = 0x38,
 381         mm_32f_73_op = 0x3b,
 382         mm_32f_74_op = 0x3c,
 383 };
 384
 385 /*
 386  * (microMIPS) POOL32F secondary minor opcodes.
 387  */
 388 enum mm_32f_10_minor_op {
 389         mm_lwxc1_op = 0x1,
 390         mm_swxc1_op,
 391         mm_ldxc1_op,
 392         mm_sdxc1_op,
 393         mm_luxc1_op,
 394         mm_suxc1_op,
 395 };
 396
 397 enum mm_32f_func {
 398         mm_lwxc1_func = 0x048,
 399         mm_swxc1_func = 0x088,
 400         mm_ldxc1_func = 0x0c8,
 401         mm_sdxc1_func = 0x108,
 402 };
 403
 404 /*
 405  * (microMIPS) POOL32F secondary minor opcodes.
 406  */
 407 enum mm_32f_40_minor_op {
 408         mm_fmovf_op,
 409         mm_fmovt_op,
 410 };
 411
 412 /*
 413  * (microMIPS) POOL32F secondary minor opcodes.
 414  */
 415 enum mm_32f_60_minor_op {
 416         mm_fadd_op,
 417         mm_fsub_op,
 418         mm_fmul_op,
 419         mm_fdiv_op,
 420 };
 421
 422 /*
 423  * (microMIPS) POOL32F secondary minor opcodes.
 424  */
 425 enum mm_32f_70_minor_op {
 426         mm_fmovn_op,
 427         mm_fmovz_op,
 428 };
 429
 430 /*
 431  * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
 432  */
 433 enum mm_32f_73_minor_op {
 434         mm_fmov0_op = 0x01,
 435         mm_fcvtl_op = 0x04,
 436         mm_movf0_op = 0x05,
 437         mm_frsqrt_op = 0x08,
 438         mm_ffloorl_op = 0x0c,
 439         mm_fabs0_op = 0x0d,
 440         mm_fcvtw_op = 0x24,
 441         mm_movt0_op = 0x25,
 442         mm_fsqrt_op = 0x28,
 443         mm_ffloorw_op = 0x2c,
 444         mm_fneg0_op = 0x2d,
 445         mm_cfc1_op = 0x40,
 446         mm_frecip_op = 0x48,
 447         mm_fceill_op = 0x4c,
 448         mm_fcvtd0_op = 0x4d,
 449         mm_ctc1_op = 0x60,
 450         mm_fceilw_op = 0x6c,
 451         mm_fcvts0_op = 0x6d,
 452         mm_mfc1_op = 0x80,
 453         mm_fmov1_op = 0x81,
 454         mm_movf1_op = 0x85,
 455         mm_ftruncl_op = 0x8c,
 456         mm_fabs1_op = 0x8d,
 457         mm_mtc1_op = 0xa0,
 458         mm_movt1_op = 0xa5,
 459         mm_ftruncw_op = 0xac,
 460         mm_fneg1_op = 0xad,
 461         mm_mfhc1_op = 0xc0,
 462         mm_froundl_op = 0xcc,
 463         mm_fcvtd1_op = 0xcd,
 464         mm_mthc1_op = 0xe0,
 465         mm_froundw_op = 0xec,
 466         mm_fcvts1_op = 0xed,
 467 };
 468
 469 /*
 470  * (microMIPS) POOL16C minor opcodes.
 471  */
 472 enum mm_16c_minor_op {
 473         mm_lwm16_op = 0x04,
 474         mm_swm16_op = 0x05,
 475         mm_jr16_op = 0x0c,
 476         mm_jrc_op = 0x0d,
 477         mm_jalr16_op = 0x0e,
 478         mm_jalrs16_op = 0x0f,
 479         mm_jraddiusp_op = 0x18,
 480 };
 481
 482 /*
 483  * (microMIPS) POOL16D minor opcodes.
 484  */
 485 enum mm_16d_minor_op {
 486         mm_addius5_func,
 487         mm_addiusp_func,
 488 };
 489
 490 /*
 491  * (MIPS16e) opcodes.
 492  */
 493 enum MIPS16e_ops {
 494         MIPS16e_jal_op = 003,
 495         MIPS16e_ld_op = 007,
 496         MIPS16e_i8_op = 014,
 497         MIPS16e_sd_op = 017,
 498         MIPS16e_lb_op = 020,
 499         MIPS16e_lh_op = 021,
 500         MIPS16e_lwsp_op = 022,
 501         MIPS16e_lw_op = 023,
 502         MIPS16e_lbu_op = 024,
 503         MIPS16e_lhu_op = 025,
 504         MIPS16e_lwpc_op = 026,
 505         MIPS16e_lwu_op = 027,
 506         MIPS16e_sb_op = 030,
 507         MIPS16e_sh_op = 031,
 508         MIPS16e_swsp_op = 032,
 509         MIPS16e_sw_op = 033,
 510         MIPS16e_rr_op = 035,
 511         MIPS16e_extend_op = 036,
 512         MIPS16e_i64_op = 037,
 513 };
 514
 515 enum MIPS16e_i64_func {
 516         MIPS16e_ldsp_func,
 517         MIPS16e_sdsp_func,
 518         MIPS16e_sdrasp_func,
 519         MIPS16e_dadjsp_func,
 520         MIPS16e_ldpc_func,
 521 };
 522
 523 enum MIPS16e_rr_func {
 524         MIPS16e_jr_func,
 525 };
 526
 527 enum MIPS6e_i8_func {
 528         MIPS16e_swrasp_func = 02,
 529 };
 530
 531 /*
 532  * (microMIPS & MIPS16e) NOP instruction.
 533  */
 534 #define MM_NOP16        0x0c00
 535
 536 struct j_format {
 537         __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
 538         __BITFIELD_FIELD(unsigned int target : 26,
 539         ;))
 540 };
 541
 542 struct i_format {                       /* signed immediate format */
 543         __BITFIELD_FIELD(unsigned int opcode : 6,
 544         __BITFIELD_FIELD(unsigned int rs : 5,
 545         __BITFIELD_FIELD(unsigned int rt : 5,
 546         __BITFIELD_FIELD(signed int simmediate : 16,
 547         ;))))
 548 };
 549
 550 struct u_format {                       /* unsigned immediate format */
 551         __BITFIELD_FIELD(unsigned int opcode : 6,
 552         __BITFIELD_FIELD(unsigned int rs : 5,
 553         __BITFIELD_FIELD(unsigned int rt : 5,
 554         __BITFIELD_FIELD(unsigned int uimmediate : 16,
 555         ;))))
 556 };
 557
 558 struct c_format {                       /* Cache (>= R6000) format */
 559         __BITFIELD_FIELD(unsigned int opcode : 6,
 560         __BITFIELD_FIELD(unsigned int rs : 5,
 561         __BITFIELD_FIELD(unsigned int c_op : 3,
 562         __BITFIELD_FIELD(unsigned int cache : 2,
 563         __BITFIELD_FIELD(unsigned int simmediate : 16,
 564         ;)))))
 565 };
 566
 567 struct r_format {                       /* Register format */
 568         __BITFIELD_FIELD(unsigned int opcode : 6,
 569         __BITFIELD_FIELD(unsigned int rs : 5,
 570         __BITFIELD_FIELD(unsigned int rt : 5,
 571         __BITFIELD_FIELD(unsigned int rd : 5,
 572         __BITFIELD_FIELD(unsigned int re : 5,
 573         __BITFIELD_FIELD(unsigned int func : 6,
 574         ;))))))
 575 };
 576
 577 struct p_format {               /* Performance counter format (R10000) */
 578         __BITFIELD_FIELD(unsigned int opcode : 6,
 579         __BITFIELD_FIELD(unsigned int rs : 5,
 580         __BITFIELD_FIELD(unsigned int rt : 5,
 581         __BITFIELD_FIELD(unsigned int rd : 5,
 582         __BITFIELD_FIELD(unsigned int re : 5,
 583         __BITFIELD_FIELD(unsigned int func : 6,
 584         ;))))))
 585 };
 586
 587 struct f_format {                       /* FPU register format */
 588         __BITFIELD_FIELD(unsigned int opcode : 6,
 589         __BITFIELD_FIELD(unsigned int : 1,
 590         __BITFIELD_FIELD(unsigned int fmt : 4,
 591         __BITFIELD_FIELD(unsigned int rt : 5,
 592         __BITFIELD_FIELD(unsigned int rd : 5,
 593         __BITFIELD_FIELD(unsigned int re : 5,
 594         __BITFIELD_FIELD(unsigned int func : 6,
 595         ;)))))))
 596 };
 597
 598 struct ma_format {              /* FPU multiply and add format (MIPS IV) */
 599         __BITFIELD_FIELD(unsigned int opcode : 6,
 600         __BITFIELD_FIELD(unsigned int fr : 5,
 601         __BITFIELD_FIELD(unsigned int ft : 5,
 602         __BITFIELD_FIELD(unsigned int fs : 5,
 603         __BITFIELD_FIELD(unsigned int fd : 5,
 604         __BITFIELD_FIELD(unsigned int func : 4,
 605         __BITFIELD_FIELD(unsigned int fmt : 2,
 606         ;)))))))
 607 };
 608
 609 struct b_format {                       /* BREAK and SYSCALL */
 610         __BITFIELD_FIELD(unsigned int opcode : 6,
 611         __BITFIELD_FIELD(unsigned int code : 20,
 612         __BITFIELD_FIELD(unsigned int func : 6,
 613         ;)))
 614 };
 615
 616 struct ps_format {                      /* MIPS-3D / paired single format */
 617         __BITFIELD_FIELD(unsigned int opcode : 6,
 618         __BITFIELD_FIELD(unsigned int rs : 5,
 619         __BITFIELD_FIELD(unsigned int ft : 5,
 620         __BITFIELD_FIELD(unsigned int fs : 5,
 621         __BITFIELD_FIELD(unsigned int fd : 5,
 622         __BITFIELD_FIELD(unsigned int func : 6,
 623         ;))))))
 624 };
 625
 626 struct v_format {                               /* MDMX vector format */
 627         __BITFIELD_FIELD(unsigned int opcode : 6,
 628         __BITFIELD_FIELD(unsigned int sel : 4,
 629         __BITFIELD_FIELD(unsigned int fmt : 1,
 630         __BITFIELD_FIELD(unsigned int vt : 5,
 631         __BITFIELD_FIELD(unsigned int vs : 5,
 632         __BITFIELD_FIELD(unsigned int vd : 5,
 633         __BITFIELD_FIELD(unsigned int func : 6,
 634         ;)))))))
 635 };
 636
 637 struct msa_mi10_format {                /* MSA MI10 */
 638         __BITFIELD_FIELD(unsigned int opcode : 6,
 639         __BITFIELD_FIELD(signed int s10 : 10,
 640         __BITFIELD_FIELD(unsigned int rs : 5,
 641         __BITFIELD_FIELD(unsigned int wd : 5,
 642         __BITFIELD_FIELD(unsigned int func : 4,
 643         __BITFIELD_FIELD(unsigned int df : 2,
 644         ;))))))
 645 };
 646
 647 struct spec3_format {   /* SPEC3 */
 648         __BITFIELD_FIELD(unsigned int opcode:6,
 649         __BITFIELD_FIELD(unsigned int rs:5,
 650         __BITFIELD_FIELD(unsigned int rt:5,
 651         __BITFIELD_FIELD(signed int simmediate:9,
 652         __BITFIELD_FIELD(unsigned int func:7,
 653         ;)))))
 654 };
 655
 656 /*
 657  * microMIPS instruction formats (32-bit length)
 658  *
 659  * NOTE:
 660  *      Parenthesis denote whether the format is a microMIPS instruction or
 661  *      if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
 662  */
 663 struct fb_format {              /* FPU branch format (MIPS32) */
 664         __BITFIELD_FIELD(unsigned int opcode : 6,
 665         __BITFIELD_FIELD(unsigned int bc : 5,
 666         __BITFIELD_FIELD(unsigned int cc : 3,
 667         __BITFIELD_FIELD(unsigned int flag : 2,
 668         __BITFIELD_FIELD(signed int simmediate : 16,
 669         ;)))))
 670 };
 671
 672 struct fp0_format {             /* FPU multiply and add format (MIPS32) */
 673         __BITFIELD_FIELD(unsigned int opcode : 6,
 674         __BITFIELD_FIELD(unsigned int fmt : 5,
 675         __BITFIELD_FIELD(unsigned int ft : 5,
 676         __BITFIELD_FIELD(unsigned int fs : 5,
 677         __BITFIELD_FIELD(unsigned int fd : 5,
 678         __BITFIELD_FIELD(unsigned int func : 6,
 679         ;))))))
 680 };
 681
 682 struct mm_fp0_format {          /* FPU multipy and add format (microMIPS) */
 683         __BITFIELD_FIELD(unsigned int opcode : 6,
 684         __BITFIELD_FIELD(unsigned int ft : 5,
 685         __BITFIELD_FIELD(unsigned int fs : 5,
 686         __BITFIELD_FIELD(unsigned int fd : 5,
 687         __BITFIELD_FIELD(unsigned int fmt : 3,
 688         __BITFIELD_FIELD(unsigned int op : 2,
 689         __BITFIELD_FIELD(unsigned int func : 6,
 690         ;)))))))
 691 };
 692
 693 struct fp1_format {             /* FPU mfc1 and cfc1 format (MIPS32) */
 694         __BITFIELD_FIELD(unsigned int opcode : 6,
 695         __BITFIELD_FIELD(unsigned int op : 5,
 696         __BITFIELD_FIELD(unsigned int rt : 5,
 697         __BITFIELD_FIELD(unsigned int fs : 5,
 698         __BITFIELD_FIELD(unsigned int fd : 5,
 699         __BITFIELD_FIELD(unsigned int func : 6,
 700         ;))))))
 701 };
 702
 703 struct mm_fp1_format {          /* FPU mfc1 and cfc1 format (microMIPS) */
 704         __BITFIELD_FIELD(unsigned int opcode : 6,
 705         __BITFIELD_FIELD(unsigned int rt : 5,
 706         __BITFIELD_FIELD(unsigned int fs : 5,
 707         __BITFIELD_FIELD(unsigned int fmt : 2,
 708         __BITFIELD_FIELD(unsigned int op : 8,
 709         __BITFIELD_FIELD(unsigned int func : 6,
 710         ;))))))
 711 };
 712
 713 struct mm_fp2_format {          /* FPU movt and movf format (microMIPS) */
 714         __BITFIELD_FIELD(unsigned int opcode : 6,
 715         __BITFIELD_FIELD(unsigned int fd : 5,
 716         __BITFIELD_FIELD(unsigned int fs : 5,
 717         __BITFIELD_FIELD(unsigned int cc : 3,
 718         __BITFIELD_FIELD(unsigned int zero : 2,
 719         __BITFIELD_FIELD(unsigned int fmt : 2,
 720         __BITFIELD_FIELD(unsigned int op : 3,
 721         __BITFIELD_FIELD(unsigned int func : 6,
 722         ;))))))))
 723 };
 724
 725 struct mm_fp3_format {          /* FPU abs and neg format (microMIPS) */
 726         __BITFIELD_FIELD(unsigned int opcode : 6,
 727         __BITFIELD_FIELD(unsigned int rt : 5,
 728         __BITFIELD_FIELD(unsigned int fs : 5,
 729         __BITFIELD_FIELD(unsigned int fmt : 3,
 730         __BITFIELD_FIELD(unsigned int op : 7,
 731         __BITFIELD_FIELD(unsigned int func : 6,
 732         ;))))))
 733 };
 734
 735 struct mm_fp4_format {          /* FPU c.cond format (microMIPS) */
 736         __BITFIELD_FIELD(unsigned int opcode : 6,
 737         __BITFIELD_FIELD(unsigned int rt : 5,
 738         __BITFIELD_FIELD(unsigned int fs : 5,
 739         __BITFIELD_FIELD(unsigned int cc : 3,
 740         __BITFIELD_FIELD(unsigned int fmt : 3,
 741         __BITFIELD_FIELD(unsigned int cond : 4,
 742         __BITFIELD_FIELD(unsigned int func : 6,
 743         ;)))))))
 744 };
 745
 746 struct mm_fp5_format {          /* FPU lwxc1 and swxc1 format (microMIPS) */
 747         __BITFIELD_FIELD(unsigned int opcode : 6,
 748         __BITFIELD_FIELD(unsigned int index : 5,
 749         __BITFIELD_FIELD(unsigned int base : 5,
 750         __BITFIELD_FIELD(unsigned int fd : 5,
 751         __BITFIELD_FIELD(unsigned int op : 5,
 752         __BITFIELD_FIELD(unsigned int func : 6,
 753         ;))))))
 754 };
 755
 756 struct fp6_format {             /* FPU madd and msub format (MIPS IV) */
 757         __BITFIELD_FIELD(unsigned int opcode : 6,
 758         __BITFIELD_FIELD(unsigned int fr : 5,
 759         __BITFIELD_FIELD(unsigned int ft : 5,
 760         __BITFIELD_FIELD(unsigned int fs : 5,
 761         __BITFIELD_FIELD(unsigned int fd : 5,
 762         __BITFIELD_FIELD(unsigned int func : 6,
 763         ;))))))
 764 };
 765
 766 struct mm_fp6_format {          /* FPU madd and msub format (microMIPS) */
 767         __BITFIELD_FIELD(unsigned int opcode : 6,
 768         __BITFIELD_FIELD(unsigned int ft : 5,
 769         __BITFIELD_FIELD(unsigned int fs : 5,
 770         __BITFIELD_FIELD(unsigned int fd : 5,
 771         __BITFIELD_FIELD(unsigned int fr : 5,
 772         __BITFIELD_FIELD(unsigned int func : 6,
 773         ;))))))
 774 };
 775
 776 struct mm_i_format {            /* Immediate format (microMIPS) */
 777         __BITFIELD_FIELD(unsigned int opcode : 6,
 778         __BITFIELD_FIELD(unsigned int rt : 5,
 779         __BITFIELD_FIELD(unsigned int rs : 5,
 780         __BITFIELD_FIELD(signed int simmediate : 16,
 781         ;))))
 782 };
 783
 784 struct mm_m_format {            /* Multi-word load/store format (microMIPS) */
 785         __BITFIELD_FIELD(unsigned int opcode : 6,
 786         __BITFIELD_FIELD(unsigned int rd : 5,
 787         __BITFIELD_FIELD(unsigned int base : 5,
 788         __BITFIELD_FIELD(unsigned int func : 4,
 789         __BITFIELD_FIELD(signed int simmediate : 12,
 790         ;)))))
 791 };
 792
 793 struct mm_x_format {            /* Scaled indexed load format (microMIPS) */
 794         __BITFIELD_FIELD(unsigned int opcode : 6,
 795         __BITFIELD_FIELD(unsigned int index : 5,
 796         __BITFIELD_FIELD(unsigned int base : 5,
 797         __BITFIELD_FIELD(unsigned int rd : 5,
 798         __BITFIELD_FIELD(unsigned int func : 11,
 799         ;)))))
 800 };
 801
 802 /*
 803  * microMIPS instruction formats (16-bit length)
 804  */
 805 struct mm_b0_format {           /* Unconditional branch format (microMIPS) */
 806         __BITFIELD_FIELD(unsigned int opcode : 6,
 807         __BITFIELD_FIELD(signed int simmediate : 10,
 808         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 809         ;)))
 810 };
 811
 812 struct mm_b1_format {           /* Conditional branch format (microMIPS) */
 813         __BITFIELD_FIELD(unsigned int opcode : 6,
 814         __BITFIELD_FIELD(unsigned int rs : 3,
 815         __BITFIELD_FIELD(signed int simmediate : 7,
 816         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 817         ;))))
 818 };
 819
 820 struct mm16_m_format {          /* Multi-word load/store format */
 821         __BITFIELD_FIELD(unsigned int opcode : 6,
 822         __BITFIELD_FIELD(unsigned int func : 4,
 823         __BITFIELD_FIELD(unsigned int rlist : 2,
 824         __BITFIELD_FIELD(unsigned int imm : 4,
 825         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 826         ;)))))
 827 };
 828
 829 struct mm16_rb_format {         /* Signed immediate format */
 830         __BITFIELD_FIELD(unsigned int opcode : 6,
 831         __BITFIELD_FIELD(unsigned int rt : 3,
 832         __BITFIELD_FIELD(unsigned int base : 3,
 833         __BITFIELD_FIELD(signed int simmediate : 4,
 834         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 835         ;)))))
 836 };
 837
 838 struct mm16_r3_format {         /* Load from global pointer format */
 839         __BITFIELD_FIELD(unsigned int opcode : 6,
 840         __BITFIELD_FIELD(unsigned int rt : 3,
 841         __BITFIELD_FIELD(signed int simmediate : 7,
 842         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 843         ;))))
 844 };
 845
 846 struct mm16_r5_format {         /* Load/store from stack pointer format */
 847         __BITFIELD_FIELD(unsigned int opcode : 6,
 848         __BITFIELD_FIELD(unsigned int rt : 5,
 849         __BITFIELD_FIELD(signed int simmediate : 5,
 850         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
 851         ;))))
 852 };
 853
 854 /*
 855  * MIPS16e instruction formats (16-bit length)
 856  */
 857 struct m16e_rr {
 858         __BITFIELD_FIELD(unsigned int opcode : 5,
 859         __BITFIELD_FIELD(unsigned int rx : 3,
 860         __BITFIELD_FIELD(unsigned int nd : 1,
 861         __BITFIELD_FIELD(unsigned int l : 1,
 862         __BITFIELD_FIELD(unsigned int ra : 1,
 863         __BITFIELD_FIELD(unsigned int func : 5,
 864         ;))))))
 865 };
 866
 867 struct m16e_jal {
 868         __BITFIELD_FIELD(unsigned int opcode : 5,
 869         __BITFIELD_FIELD(unsigned int x : 1,
 870         __BITFIELD_FIELD(unsigned int imm20_16 : 5,
 871         __BITFIELD_FIELD(signed int imm25_21 : 5,
 872         ;))))
 873 };
 874
 875 struct m16e_i64 {
 876         __BITFIELD_FIELD(unsigned int opcode : 5,
 877         __BITFIELD_FIELD(unsigned int func : 3,
 878         __BITFIELD_FIELD(unsigned int imm : 8,
 879         ;)))
 880 };
 881
 882 struct m16e_ri64 {
 883         __BITFIELD_FIELD(unsigned int opcode : 5,
 884         __BITFIELD_FIELD(unsigned int func : 3,
 885         __BITFIELD_FIELD(unsigned int ry : 3,
 886         __BITFIELD_FIELD(unsigned int imm : 5,
 887         ;))))
 888 };
 889
 890 struct m16e_ri {
 891         __BITFIELD_FIELD(unsigned int opcode : 5,
 892         __BITFIELD_FIELD(unsigned int rx : 3,
 893         __BITFIELD_FIELD(unsigned int imm : 8,
 894         ;)))
 895 };
 896
 897 struct m16e_rri {
 898         __BITFIELD_FIELD(unsigned int opcode : 5,
 899         __BITFIELD_FIELD(unsigned int rx : 3,
 900         __BITFIELD_FIELD(unsigned int ry : 3,
 901         __BITFIELD_FIELD(unsigned int imm : 5,
 902         ;))))
 903 };
 904
 905 struct m16e_i8 {
 906         __BITFIELD_FIELD(unsigned int opcode : 5,
 907         __BITFIELD_FIELD(unsigned int func : 3,
 908         __BITFIELD_FIELD(unsigned int imm : 8,
 909         ;)))
 910 };
 911
 912 union mips_instruction {
 913         unsigned int word;
 914         unsigned short halfword[2];
 915         unsigned char byte[4];
 916         struct j_format j_format;
 917         struct i_format i_format;
 918         struct u_format u_format;
 919         struct c_format c_format;
 920         struct r_format r_format;
 921         struct p_format p_format;
 922         struct f_format f_format;
 923         struct ma_format ma_format;
 924         struct msa_mi10_format msa_mi10_format;
 925         struct b_format b_format;
 926         struct ps_format ps_format;
 927         struct v_format v_format;
 928         struct spec3_format spec3_format;
 929         struct fb_format fb_format;
 930         struct fp0_format fp0_format;
 931         struct mm_fp0_format mm_fp0_format;
 932         struct fp1_format fp1_format;
 933         struct mm_fp1_format mm_fp1_format;
 934         struct mm_fp2_format mm_fp2_format;
 935         struct mm_fp3_format mm_fp3_format;
 936         struct mm_fp4_format mm_fp4_format;
 937         struct mm_fp5_format mm_fp5_format;
 938         struct fp6_format fp6_format;
 939         struct mm_fp6_format mm_fp6_format;
 940         struct mm_i_format mm_i_format;
 941         struct mm_m_format mm_m_format;
 942         struct mm_x_format mm_x_format;
 943         struct mm_b0_format mm_b0_format;
 944         struct mm_b1_format mm_b1_format;
 945         struct mm16_m_format mm16_m_format ;
 946         struct mm16_rb_format mm16_rb_format;
 947         struct mm16_r3_format mm16_r3_format;
 948         struct mm16_r5_format mm16_r5_format;
 949 };
 950
 951 union mips16e_instruction {
 952         unsigned int full : 16;
 953         struct m16e_rr rr;
 954         struct m16e_jal jal;
 955         struct m16e_i64 i64;
 956         struct m16e_ri64 ri64;
 957         struct m16e_ri ri;
 958         struct m16e_rri rri;
 959         struct m16e_i8 i8;
 960 };
 961
 962 #endif /* _UAPI_ASM_INST_H */