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of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / arch / mips / kernel / cpu-probe.c
blob6b9064499bd3dfb49ef0c09ad3da48034dea0ff2
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
25 #include <asm/fpu.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
28 #include <asm/msa.h>
29 #include <asm/watch.h>
30 #include <asm/elf.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
34
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly;
37
38 /*
39 * Get the FPU Implementation/Revision.
40 */
41 static inline unsigned long cpu_get_fpu_id(void)
42 {
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50 }
51
52 /*
53 * Check if the CPU has an external FPU.
54 */
55 static inline int __cpu_has_fpu(void)
56 {
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58 }
59
60 static inline unsigned long cpu_get_msa_id(void)
61 {
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71 }
72
73 /*
74 * Determine the FCSR mask for FPU hardware.
75 */
76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77 {
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
80 fcsr = c->fpu_csr31;
81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99 }
100
101 /*
102 * Set the FIR feature flags for the FPU emulator.
103 */
104 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
105 {
106 u32 value;
107
108 value = 0;
109 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
110 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
111 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
112 value |= MIPS_FPIR_D | MIPS_FPIR_S;
113 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
114 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
115 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
116 c->fpu_id = value;
117 }
118
119 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
120 static unsigned int mips_nofpu_msk31;
121
122 /*
123 * Set options for FPU hardware.
124 */
125 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
126 {
127 c->fpu_id = cpu_get_fpu_id();
128 mips_nofpu_msk31 = c->fpu_msk31;
129
130 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
131 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
132 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
133 if (c->fpu_id & MIPS_FPIR_3D)
134 c->ases |= MIPS_ASE_MIPS3D;
135 if (c->fpu_id & MIPS_FPIR_FREP)
136 c->options |= MIPS_CPU_FRE;
137 }
138
139 cpu_set_fpu_fcsr_mask(c);
140 }
141
142 /*
143 * Set options for the FPU emulator.
144 */
145 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
146 {
147 c->options &= ~MIPS_CPU_FPU;
148 c->fpu_msk31 = mips_nofpu_msk31;
149
150 cpu_set_nofpu_id(c);
151 }
152
153 static int mips_fpu_disabled;
154
155 static int __init fpu_disable(char *s)
156 {
157 cpu_set_nofpu_opts(&boot_cpu_data);
158 mips_fpu_disabled = 1;
159
160 return 1;
161 }
162
163 __setup("nofpu", fpu_disable);
164
165 int mips_dsp_disabled;
166
167 static int __init dsp_disable(char *s)
168 {
169 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
170 mips_dsp_disabled = 1;
171
172 return 1;
173 }
174
175 __setup("nodsp", dsp_disable);
176
177 static int mips_htw_disabled;
178
179 static int __init htw_disable(char *s)
180 {
181 mips_htw_disabled = 1;
182 cpu_data[0].options &= ~MIPS_CPU_HTW;
183 write_c0_pwctl(read_c0_pwctl() &
184 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
185
186 return 1;
187 }
188
189 __setup("nohtw", htw_disable);
190
191 static int mips_ftlb_disabled;
192 static int mips_has_ftlb_configured;
193
194 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
195
196 static int __init ftlb_disable(char *s)
197 {
198 unsigned int config4, mmuextdef;
199
200 /*
201 * If the core hasn't done any FTLB configuration, there is nothing
202 * for us to do here.
203 */
204 if (!mips_has_ftlb_configured)
205 return 1;
206
207 /* Disable it in the boot cpu */
208 if (set_ftlb_enable(&cpu_data[0], 0)) {
209 pr_warn("Can't turn FTLB off\n");
210 return 1;
211 }
212
213 back_to_back_c0_hazard();
214
215 config4 = read_c0_config4();
216
217 /* Check that FTLB has been disabled */
218 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
219 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
220 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
221 /* This should never happen */
222 pr_warn("FTLB could not be disabled!\n");
223 return 1;
224 }
225
226 mips_ftlb_disabled = 1;
227 mips_has_ftlb_configured = 0;
228
229 /*
230 * noftlb is mainly used for debug purposes so print
231 * an informative message instead of using pr_debug()
232 */
233 pr_info("FTLB has been disabled\n");
234
235 /*
236 * Some of these bits are duplicated in the decode_config4.
237 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
238 * once FTLB has been disabled so undo what decode_config4 did.
239 */
240 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
241 cpu_data[0].tlbsizeftlbsets;
242 cpu_data[0].tlbsizeftlbsets = 0;
243 cpu_data[0].tlbsizeftlbways = 0;
244
245 return 1;
246 }
247
248 __setup("noftlb", ftlb_disable);
249
250
251 static inline void check_errata(void)
252 {
253 struct cpuinfo_mips *c = &current_cpu_data;
254
255 switch (current_cpu_type()) {
256 case CPU_34K:
257 /*
258 * Erratum "RPS May Cause Incorrect Instruction Execution"
259 * This code only handles VPE0, any SMP/RTOS code
260 * making use of VPE1 will be responsable for that VPE.
261 */
262 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
263 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
264 break;
265 default:
266 break;
267 }
268 }
269
270 void __init check_bugs32(void)
271 {
272 check_errata();
273 }
274
275 /*
276 * Probe whether cpu has config register by trying to play with
277 * alternate cache bit and see whether it matters.
278 * It's used by cpu_probe to distinguish between R3000A and R3081.
279 */
280 static inline int cpu_has_confreg(void)
281 {
282 #ifdef CONFIG_CPU_R3000
283 extern unsigned long r3k_cache_size(unsigned long);
284 unsigned long size1, size2;
285 unsigned long cfg = read_c0_conf();
286
287 size1 = r3k_cache_size(ST0_ISC);
288 write_c0_conf(cfg ^ R30XX_CONF_AC);
289 size2 = r3k_cache_size(ST0_ISC);
290 write_c0_conf(cfg);
291 return size1 != size2;
292 #else
293 return 0;
294 #endif
295 }
296
297 static inline void set_elf_platform(int cpu, const char *plat)
298 {
299 if (cpu == 0)
300 __elf_platform = plat;
301 }
302
303 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
304 {
305 #ifdef __NEED_VMBITS_PROBE
306 write_c0_entryhi(0x3fffffffffffe000ULL);
307 back_to_back_c0_hazard();
308 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
309 #endif
310 }
311
312 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
313 {
314 switch (isa) {
315 case MIPS_CPU_ISA_M64R2:
316 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
317 case MIPS_CPU_ISA_M64R1:
318 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
319 case MIPS_CPU_ISA_V:
320 c->isa_level |= MIPS_CPU_ISA_V;
321 case MIPS_CPU_ISA_IV:
322 c->isa_level |= MIPS_CPU_ISA_IV;
323 case MIPS_CPU_ISA_III:
324 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
325 break;
326
327 /* R6 incompatible with everything else */
328 case MIPS_CPU_ISA_M64R6:
329 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
330 case MIPS_CPU_ISA_M32R6:
331 c->isa_level |= MIPS_CPU_ISA_M32R6;
332 /* Break here so we don't add incompatible ISAs */
333 break;
334 case MIPS_CPU_ISA_M32R2:
335 c->isa_level |= MIPS_CPU_ISA_M32R2;
336 case MIPS_CPU_ISA_M32R1:
337 c->isa_level |= MIPS_CPU_ISA_M32R1;
338 case MIPS_CPU_ISA_II:
339 c->isa_level |= MIPS_CPU_ISA_II;
340 break;
341 }
342 }
343
344 static char unknown_isa[] = KERN_ERR \
345 "Unsupported ISA type, c0.config0: %d.";
346
347 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
348 {
349
350 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
351
352 /*
353 * 0 = All TLBWR instructions go to FTLB
354 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
355 * FTLB and 1 goes to the VTLB.
356 * 2 = 7:1: As above with 7:1 ratio.
357 * 3 = 3:1: As above with 3:1 ratio.
358 *
359 * Use the linear midpoint as the probability threshold.
360 */
361 if (probability >= 12)
362 return 1;
363 else if (probability >= 6)
364 return 2;
365 else
366 /*
367 * So FTLB is less than 4 times bigger than VTLB.
368 * A 3:1 ratio can still be useful though.
369 */
370 return 3;
371 }
372
373 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
374 {
375 unsigned int config;
376
377 /* It's implementation dependent how the FTLB can be enabled */
378 switch (c->cputype) {
379 case CPU_PROAPTIV:
380 case CPU_P5600:
381 /* proAptiv & related cores use Config6 to enable the FTLB */
382 config = read_c0_config6();
383 /* Clear the old probability value */
384 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
385 if (enable)
386 /* Enable FTLB */
387 write_c0_config6(config |
388 (calculate_ftlb_probability(c)
389 << MIPS_CONF6_FTLBP_SHIFT)
390 | MIPS_CONF6_FTLBEN);
391 else
392 /* Disable FTLB */
393 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
394 break;
395 case CPU_I6400:
396 /* I6400 & related cores use Config7 to configure FTLB */
397 config = read_c0_config7();
398 /* Clear the old probability value */
399 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
400 write_c0_config7(config | (calculate_ftlb_probability(c)
401 << MIPS_CONF7_FTLBP_SHIFT));
402 break;
403 default:
404 return 1;
405 }
406
407 return 0;
408 }
409
410 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
411 {
412 unsigned int config0;
413 int isa, mt;
414
415 config0 = read_c0_config();
416
417 /*
418 * Look for Standard TLB or Dual VTLB and FTLB
419 */
420 mt = config0 & MIPS_CONF_MT;
421 if (mt == MIPS_CONF_MT_TLB)
422 c->options |= MIPS_CPU_TLB;
423 else if (mt == MIPS_CONF_MT_FTLB)
424 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
425
426 isa = (config0 & MIPS_CONF_AT) >> 13;
427 switch (isa) {
428 case 0:
429 switch ((config0 & MIPS_CONF_AR) >> 10) {
430 case 0:
431 set_isa(c, MIPS_CPU_ISA_M32R1);
432 break;
433 case 1:
434 set_isa(c, MIPS_CPU_ISA_M32R2);
435 break;
436 case 2:
437 set_isa(c, MIPS_CPU_ISA_M32R6);
438 break;
439 default:
440 goto unknown;
441 }
442 break;
443 case 2:
444 switch ((config0 & MIPS_CONF_AR) >> 10) {
445 case 0:
446 set_isa(c, MIPS_CPU_ISA_M64R1);
447 break;
448 case 1:
449 set_isa(c, MIPS_CPU_ISA_M64R2);
450 break;
451 case 2:
452 set_isa(c, MIPS_CPU_ISA_M64R6);
453 break;
454 default:
455 goto unknown;
456 }
457 break;
458 default:
459 goto unknown;
460 }
461
462 return config0 & MIPS_CONF_M;
463
464 unknown:
465 panic(unknown_isa, config0);
466 }
467
468 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
469 {
470 unsigned int config1;
471
472 config1 = read_c0_config1();
473
474 if (config1 & MIPS_CONF1_MD)
475 c->ases |= MIPS_ASE_MDMX;
476 if (config1 & MIPS_CONF1_WR)
477 c->options |= MIPS_CPU_WATCH;
478 if (config1 & MIPS_CONF1_CA)
479 c->ases |= MIPS_ASE_MIPS16;
480 if (config1 & MIPS_CONF1_EP)
481 c->options |= MIPS_CPU_EJTAG;
482 if (config1 & MIPS_CONF1_FP) {
483 c->options |= MIPS_CPU_FPU;
484 c->options |= MIPS_CPU_32FPR;
485 }
486 if (cpu_has_tlb) {
487 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
488 c->tlbsizevtlb = c->tlbsize;
489 c->tlbsizeftlbsets = 0;
490 }
491
492 return config1 & MIPS_CONF_M;
493 }
494
495 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
496 {
497 unsigned int config2;
498
499 config2 = read_c0_config2();
500
501 if (config2 & MIPS_CONF2_SL)
502 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
503
504 return config2 & MIPS_CONF_M;
505 }
506
507 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
508 {
509 unsigned int config3;
510
511 config3 = read_c0_config3();
512
513 if (config3 & MIPS_CONF3_SM) {
514 c->ases |= MIPS_ASE_SMARTMIPS;
515 c->options |= MIPS_CPU_RIXI;
516 }
517 if (config3 & MIPS_CONF3_RXI)
518 c->options |= MIPS_CPU_RIXI;
519 if (config3 & MIPS_CONF3_DSP)
520 c->ases |= MIPS_ASE_DSP;
521 if (config3 & MIPS_CONF3_DSP2P)
522 c->ases |= MIPS_ASE_DSP2P;
523 if (config3 & MIPS_CONF3_VINT)
524 c->options |= MIPS_CPU_VINT;
525 if (config3 & MIPS_CONF3_VEIC)
526 c->options |= MIPS_CPU_VEIC;
527 if (config3 & MIPS_CONF3_MT)
528 c->ases |= MIPS_ASE_MIPSMT;
529 if (config3 & MIPS_CONF3_ULRI)
530 c->options |= MIPS_CPU_ULRI;
531 if (config3 & MIPS_CONF3_ISA)
532 c->options |= MIPS_CPU_MICROMIPS;
533 if (config3 & MIPS_CONF3_VZ)
534 c->ases |= MIPS_ASE_VZ;
535 if (config3 & MIPS_CONF3_SC)
536 c->options |= MIPS_CPU_SEGMENTS;
537 if (config3 & MIPS_CONF3_MSA)
538 c->ases |= MIPS_ASE_MSA;
539 if (config3 & MIPS_CONF3_PW) {
540 c->htw_seq = 0;
541 c->options |= MIPS_CPU_HTW;
542 }
543 if (config3 & MIPS_CONF3_CDMM)
544 c->options |= MIPS_CPU_CDMM;
545 if (config3 & MIPS_CONF3_SP)
546 c->options |= MIPS_CPU_SP;
547
548 return config3 & MIPS_CONF_M;
549 }
550
551 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
552 {
553 unsigned int config4;
554 unsigned int newcf4;
555 unsigned int mmuextdef;
556 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
557
558 config4 = read_c0_config4();
559
560 if (cpu_has_tlb) {
561 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
562 c->options |= MIPS_CPU_TLBINV;
563
564 /*
565 * R6 has dropped the MMUExtDef field from config4.
566 * On R6 the fields always describe the FTLB, and only if it is
567 * present according to Config.MT.
568 */
569 if (!cpu_has_mips_r6)
570 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
571 else if (cpu_has_ftlb)
572 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
573 else
574 mmuextdef = 0;
575
576 switch (mmuextdef) {
577 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
578 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
579 c->tlbsizevtlb = c->tlbsize;
580 break;
581 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
582 c->tlbsizevtlb +=
583 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
584 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
585 c->tlbsize = c->tlbsizevtlb;
586 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
587 /* fall through */
588 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
589 if (mips_ftlb_disabled)
590 break;
591 newcf4 = (config4 & ~ftlb_page) |
592 (page_size_ftlb(mmuextdef) <<
593 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
594 write_c0_config4(newcf4);
595 back_to_back_c0_hazard();
596 config4 = read_c0_config4();
597 if (config4 != newcf4) {
598 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
599 PAGE_SIZE, config4);
600 /* Switch FTLB off */
601 set_ftlb_enable(c, 0);
602 break;
603 }
604 c->tlbsizeftlbsets = 1 <<
605 ((config4 & MIPS_CONF4_FTLBSETS) >>
606 MIPS_CONF4_FTLBSETS_SHIFT);
607 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
608 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
609 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
610 mips_has_ftlb_configured = 1;
611 break;
612 }
613 }
614
615 c->kscratch_mask = (config4 >> 16) & 0xff;
616
617 return config4 & MIPS_CONF_M;
618 }
619
620 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
621 {
622 unsigned int config5;
623
624 config5 = read_c0_config5();
625 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
626 write_c0_config5(config5);
627
628 if (config5 & MIPS_CONF5_EVA)
629 c->options |= MIPS_CPU_EVA;
630 if (config5 & MIPS_CONF5_MRP)
631 c->options |= MIPS_CPU_MAAR;
632 if (config5 & MIPS_CONF5_LLB)
633 c->options |= MIPS_CPU_RW_LLB;
634 #ifdef CONFIG_XPA
635 if (config5 & MIPS_CONF5_MVH)
636 c->options |= MIPS_CPU_XPA;
637 #endif
638
639 return config5 & MIPS_CONF_M;
640 }
641
642 static void decode_configs(struct cpuinfo_mips *c)
643 {
644 int ok;
645
646 /* MIPS32 or MIPS64 compliant CPU. */
647 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
648 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
649
650 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
651
652 /* Enable FTLB if present and not disabled */
653 set_ftlb_enable(c, !mips_ftlb_disabled);
654
655 ok = decode_config0(c); /* Read Config registers. */
656 BUG_ON(!ok); /* Arch spec violation! */
657 if (ok)
658 ok = decode_config1(c);
659 if (ok)
660 ok = decode_config2(c);
661 if (ok)
662 ok = decode_config3(c);
663 if (ok)
664 ok = decode_config4(c);
665 if (ok)
666 ok = decode_config5(c);
667
668 mips_probe_watch_registers(c);
669
670 if (cpu_has_rixi) {
671 /* Enable the RIXI exceptions */
672 set_c0_pagegrain(PG_IEC);
673 back_to_back_c0_hazard();
674 /* Verify the IEC bit is set */
675 if (read_c0_pagegrain() & PG_IEC)
676 c->options |= MIPS_CPU_RIXIEX;
677 }
678
679 #ifndef CONFIG_MIPS_CPS
680 if (cpu_has_mips_r2_r6) {
681 c->core = get_ebase_cpunum();
682 if (cpu_has_mipsmt)
683 c->core >>= fls(core_nvpes()) - 1;
684 }
685 #endif
686 }
687
688 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
689 | MIPS_CPU_COUNTER)
690
691 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
692 {
693 switch (c->processor_id & PRID_IMP_MASK) {
694 case PRID_IMP_R2000:
695 c->cputype = CPU_R2000;
696 __cpu_name[cpu] = "R2000";
697 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
698 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
699 MIPS_CPU_NOFPUEX;
700 if (__cpu_has_fpu())
701 c->options |= MIPS_CPU_FPU;
702 c->tlbsize = 64;
703 break;
704 case PRID_IMP_R3000:
705 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
706 if (cpu_has_confreg()) {
707 c->cputype = CPU_R3081E;
708 __cpu_name[cpu] = "R3081";
709 } else {
710 c->cputype = CPU_R3000A;
711 __cpu_name[cpu] = "R3000A";
712 }
713 } else {
714 c->cputype = CPU_R3000;
715 __cpu_name[cpu] = "R3000";
716 }
717 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
718 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
719 MIPS_CPU_NOFPUEX;
720 if (__cpu_has_fpu())
721 c->options |= MIPS_CPU_FPU;
722 c->tlbsize = 64;
723 break;
724 case PRID_IMP_R4000:
725 if (read_c0_config() & CONF_SC) {
726 if ((c->processor_id & PRID_REV_MASK) >=
727 PRID_REV_R4400) {
728 c->cputype = CPU_R4400PC;
729 __cpu_name[cpu] = "R4400PC";
730 } else {
731 c->cputype = CPU_R4000PC;
732 __cpu_name[cpu] = "R4000PC";
733 }
734 } else {
735 int cca = read_c0_config() & CONF_CM_CMASK;
736 int mc;
737
738 /*
739 * SC and MC versions can't be reliably told apart,
740 * but only the latter support coherent caching
741 * modes so assume the firmware has set the KSEG0
742 * coherency attribute reasonably (if uncached, we
743 * assume SC).
744 */
745 switch (cca) {
746 case CONF_CM_CACHABLE_CE:
747 case CONF_CM_CACHABLE_COW:
748 case CONF_CM_CACHABLE_CUW:
749 mc = 1;
750 break;
751 default:
752 mc = 0;
753 break;
754 }
755 if ((c->processor_id & PRID_REV_MASK) >=
756 PRID_REV_R4400) {
757 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
758 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
759 } else {
760 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
761 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
762 }
763 }
764
765 set_isa(c, MIPS_CPU_ISA_III);
766 c->fpu_msk31 |= FPU_CSR_CONDX;
767 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
768 MIPS_CPU_WATCH | MIPS_CPU_VCE |
769 MIPS_CPU_LLSC;
770 c->tlbsize = 48;
771 break;
772 case PRID_IMP_VR41XX:
773 set_isa(c, MIPS_CPU_ISA_III);
774 c->fpu_msk31 |= FPU_CSR_CONDX;
775 c->options = R4K_OPTS;
776 c->tlbsize = 32;
777 switch (c->processor_id & 0xf0) {
778 case PRID_REV_VR4111:
779 c->cputype = CPU_VR4111;
780 __cpu_name[cpu] = "NEC VR4111";
781 break;
782 case PRID_REV_VR4121:
783 c->cputype = CPU_VR4121;
784 __cpu_name[cpu] = "NEC VR4121";
785 break;
786 case PRID_REV_VR4122:
787 if ((c->processor_id & 0xf) < 0x3) {
788 c->cputype = CPU_VR4122;
789 __cpu_name[cpu] = "NEC VR4122";
790 } else {
791 c->cputype = CPU_VR4181A;
792 __cpu_name[cpu] = "NEC VR4181A";
793 }
794 break;
795 case PRID_REV_VR4130:
796 if ((c->processor_id & 0xf) < 0x4) {
797 c->cputype = CPU_VR4131;
798 __cpu_name[cpu] = "NEC VR4131";
799 } else {
800 c->cputype = CPU_VR4133;
801 c->options |= MIPS_CPU_LLSC;
802 __cpu_name[cpu] = "NEC VR4133";
803 }
804 break;
805 default:
806 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
807 c->cputype = CPU_VR41XX;
808 __cpu_name[cpu] = "NEC Vr41xx";
809 break;
810 }
811 break;
812 case PRID_IMP_R4300:
813 c->cputype = CPU_R4300;
814 __cpu_name[cpu] = "R4300";
815 set_isa(c, MIPS_CPU_ISA_III);
816 c->fpu_msk31 |= FPU_CSR_CONDX;
817 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
818 MIPS_CPU_LLSC;
819 c->tlbsize = 32;
820 break;
821 case PRID_IMP_R4600:
822 c->cputype = CPU_R4600;
823 __cpu_name[cpu] = "R4600";
824 set_isa(c, MIPS_CPU_ISA_III);
825 c->fpu_msk31 |= FPU_CSR_CONDX;
826 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
827 MIPS_CPU_LLSC;
828 c->tlbsize = 48;
829 break;
830 #if 0
831 case PRID_IMP_R4650:
832 /*
833 * This processor doesn't have an MMU, so it's not
834 * "real easy" to run Linux on it. It is left purely
835 * for documentation. Commented out because it shares
836 * it's c0_prid id number with the TX3900.
837 */
838 c->cputype = CPU_R4650;
839 __cpu_name[cpu] = "R4650";
840 set_isa(c, MIPS_CPU_ISA_III);
841 c->fpu_msk31 |= FPU_CSR_CONDX;
842 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
843 c->tlbsize = 48;
844 break;
845 #endif
846 case PRID_IMP_TX39:
847 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
848 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
849
850 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
851 c->cputype = CPU_TX3927;
852 __cpu_name[cpu] = "TX3927";
853 c->tlbsize = 64;
854 } else {
855 switch (c->processor_id & PRID_REV_MASK) {
856 case PRID_REV_TX3912:
857 c->cputype = CPU_TX3912;
858 __cpu_name[cpu] = "TX3912";
859 c->tlbsize = 32;
860 break;
861 case PRID_REV_TX3922:
862 c->cputype = CPU_TX3922;
863 __cpu_name[cpu] = "TX3922";
864 c->tlbsize = 64;
865 break;
866 }
867 }
868 break;
869 case PRID_IMP_R4700:
870 c->cputype = CPU_R4700;
871 __cpu_name[cpu] = "R4700";
872 set_isa(c, MIPS_CPU_ISA_III);
873 c->fpu_msk31 |= FPU_CSR_CONDX;
874 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
875 MIPS_CPU_LLSC;
876 c->tlbsize = 48;
877 break;
878 case PRID_IMP_TX49:
879 c->cputype = CPU_TX49XX;
880 __cpu_name[cpu] = "R49XX";
881 set_isa(c, MIPS_CPU_ISA_III);
882 c->fpu_msk31 |= FPU_CSR_CONDX;
883 c->options = R4K_OPTS | MIPS_CPU_LLSC;
884 if (!(c->processor_id & 0x08))
885 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
886 c->tlbsize = 48;
887 break;
888 case PRID_IMP_R5000:
889 c->cputype = CPU_R5000;
890 __cpu_name[cpu] = "R5000";
891 set_isa(c, MIPS_CPU_ISA_IV);
892 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
893 MIPS_CPU_LLSC;
894 c->tlbsize = 48;
895 break;
896 case PRID_IMP_R5432:
897 c->cputype = CPU_R5432;
898 __cpu_name[cpu] = "R5432";
899 set_isa(c, MIPS_CPU_ISA_IV);
900 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
901 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
902 c->tlbsize = 48;
903 break;
904 case PRID_IMP_R5500:
905 c->cputype = CPU_R5500;
906 __cpu_name[cpu] = "R5500";
907 set_isa(c, MIPS_CPU_ISA_IV);
908 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
909 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
910 c->tlbsize = 48;
911 break;
912 case PRID_IMP_NEVADA:
913 c->cputype = CPU_NEVADA;
914 __cpu_name[cpu] = "Nevada";
915 set_isa(c, MIPS_CPU_ISA_IV);
916 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
917 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
918 c->tlbsize = 48;
919 break;
920 case PRID_IMP_R6000:
921 c->cputype = CPU_R6000;
922 __cpu_name[cpu] = "R6000";
923 set_isa(c, MIPS_CPU_ISA_II);
924 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
925 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
926 MIPS_CPU_LLSC;
927 c->tlbsize = 32;
928 break;
929 case PRID_IMP_R6000A:
930 c->cputype = CPU_R6000A;
931 __cpu_name[cpu] = "R6000A";
932 set_isa(c, MIPS_CPU_ISA_II);
933 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
934 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
935 MIPS_CPU_LLSC;
936 c->tlbsize = 32;
937 break;
938 case PRID_IMP_RM7000:
939 c->cputype = CPU_RM7000;
940 __cpu_name[cpu] = "RM7000";
941 set_isa(c, MIPS_CPU_ISA_IV);
942 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
943 MIPS_CPU_LLSC;
944 /*
945 * Undocumented RM7000: Bit 29 in the info register of
946 * the RM7000 v2.0 indicates if the TLB has 48 or 64
947 * entries.
948 *
949 * 29 1 => 64 entry JTLB
950 * 0 => 48 entry JTLB
951 */
952 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
953 break;
954 case PRID_IMP_R8000:
955 c->cputype = CPU_R8000;
956 __cpu_name[cpu] = "RM8000";
957 set_isa(c, MIPS_CPU_ISA_IV);
958 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
959 MIPS_CPU_FPU | MIPS_CPU_32FPR |
960 MIPS_CPU_LLSC;
961 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
962 break;
963 case PRID_IMP_R10000:
964 c->cputype = CPU_R10000;
965 __cpu_name[cpu] = "R10000";
966 set_isa(c, MIPS_CPU_ISA_IV);
967 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
968 MIPS_CPU_FPU | MIPS_CPU_32FPR |
969 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
970 MIPS_CPU_LLSC;
971 c->tlbsize = 64;
972 break;
973 case PRID_IMP_R12000:
974 c->cputype = CPU_R12000;
975 __cpu_name[cpu] = "R12000";
976 set_isa(c, MIPS_CPU_ISA_IV);
977 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
978 MIPS_CPU_FPU | MIPS_CPU_32FPR |
979 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
980 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
981 c->tlbsize = 64;
982 break;
983 case PRID_IMP_R14000:
984 if (((c->processor_id >> 4) & 0x0f) > 2) {
985 c->cputype = CPU_R16000;
986 __cpu_name[cpu] = "R16000";
987 } else {
988 c->cputype = CPU_R14000;
989 __cpu_name[cpu] = "R14000";
990 }
991 set_isa(c, MIPS_CPU_ISA_IV);
992 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
993 MIPS_CPU_FPU | MIPS_CPU_32FPR |
994 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
995 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
996 c->tlbsize = 64;
997 break;
998 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
999 switch (c->processor_id & PRID_REV_MASK) {
1000 case PRID_REV_LOONGSON2E:
1001 c->cputype = CPU_LOONGSON2;
1002 __cpu_name[cpu] = "ICT Loongson-2";
1003 set_elf_platform(cpu, "loongson2e");
1004 set_isa(c, MIPS_CPU_ISA_III);
1005 c->fpu_msk31 |= FPU_CSR_CONDX;
1006 break;
1007 case PRID_REV_LOONGSON2F:
1008 c->cputype = CPU_LOONGSON2;
1009 __cpu_name[cpu] = "ICT Loongson-2";
1010 set_elf_platform(cpu, "loongson2f");
1011 set_isa(c, MIPS_CPU_ISA_III);
1012 c->fpu_msk31 |= FPU_CSR_CONDX;
1013 break;
1014 case PRID_REV_LOONGSON3A:
1015 c->cputype = CPU_LOONGSON3;
1016 __cpu_name[cpu] = "ICT Loongson-3";
1017 set_elf_platform(cpu, "loongson3a");
1018 set_isa(c, MIPS_CPU_ISA_M64R1);
1019 break;
1020 case PRID_REV_LOONGSON3B_R1:
1021 case PRID_REV_LOONGSON3B_R2:
1022 c->cputype = CPU_LOONGSON3;
1023 __cpu_name[cpu] = "ICT Loongson-3";
1024 set_elf_platform(cpu, "loongson3b");
1025 set_isa(c, MIPS_CPU_ISA_M64R1);
1026 break;
1027 }
1028
1029 c->options = R4K_OPTS |
1030 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1031 MIPS_CPU_32FPR;
1032 c->tlbsize = 64;
1033 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1034 break;
1035 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1036 decode_configs(c);
1037
1038 c->cputype = CPU_LOONGSON1;
1039
1040 switch (c->processor_id & PRID_REV_MASK) {
1041 case PRID_REV_LOONGSON1B:
1042 __cpu_name[cpu] = "Loongson 1B";
1043 break;
1044 }
1045
1046 break;
1047 }
1048 }
1049
1050 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1051 {
1052 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1053 switch (c->processor_id & PRID_IMP_MASK) {
1054 case PRID_IMP_QEMU_GENERIC:
1055 c->writecombine = _CACHE_UNCACHED;
1056 c->cputype = CPU_QEMU_GENERIC;
1057 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1058 break;
1059 case PRID_IMP_4KC:
1060 c->cputype = CPU_4KC;
1061 c->writecombine = _CACHE_UNCACHED;
1062 __cpu_name[cpu] = "MIPS 4Kc";
1063 break;
1064 case PRID_IMP_4KEC:
1065 case PRID_IMP_4KECR2:
1066 c->cputype = CPU_4KEC;
1067 c->writecombine = _CACHE_UNCACHED;
1068 __cpu_name[cpu] = "MIPS 4KEc";
1069 break;
1070 case PRID_IMP_4KSC:
1071 case PRID_IMP_4KSD:
1072 c->cputype = CPU_4KSC;
1073 c->writecombine = _CACHE_UNCACHED;
1074 __cpu_name[cpu] = "MIPS 4KSc";
1075 break;
1076 case PRID_IMP_5KC:
1077 c->cputype = CPU_5KC;
1078 c->writecombine = _CACHE_UNCACHED;
1079 __cpu_name[cpu] = "MIPS 5Kc";
1080 break;
1081 case PRID_IMP_5KE:
1082 c->cputype = CPU_5KE;
1083 c->writecombine = _CACHE_UNCACHED;
1084 __cpu_name[cpu] = "MIPS 5KE";
1085 break;
1086 case PRID_IMP_20KC:
1087 c->cputype = CPU_20KC;
1088 c->writecombine = _CACHE_UNCACHED;
1089 __cpu_name[cpu] = "MIPS 20Kc";
1090 break;
1091 case PRID_IMP_24K:
1092 c->cputype = CPU_24K;
1093 c->writecombine = _CACHE_UNCACHED;
1094 __cpu_name[cpu] = "MIPS 24Kc";
1095 break;
1096 case PRID_IMP_24KE:
1097 c->cputype = CPU_24K;
1098 c->writecombine = _CACHE_UNCACHED;
1099 __cpu_name[cpu] = "MIPS 24KEc";
1100 break;
1101 case PRID_IMP_25KF:
1102 c->cputype = CPU_25KF;
1103 c->writecombine = _CACHE_UNCACHED;
1104 __cpu_name[cpu] = "MIPS 25Kc";
1105 break;
1106 case PRID_IMP_34K:
1107 c->cputype = CPU_34K;
1108 c->writecombine = _CACHE_UNCACHED;
1109 __cpu_name[cpu] = "MIPS 34Kc";
1110 break;
1111 case PRID_IMP_74K:
1112 c->cputype = CPU_74K;
1113 c->writecombine = _CACHE_UNCACHED;
1114 __cpu_name[cpu] = "MIPS 74Kc";
1115 break;
1116 case PRID_IMP_M14KC:
1117 c->cputype = CPU_M14KC;
1118 c->writecombine = _CACHE_UNCACHED;
1119 __cpu_name[cpu] = "MIPS M14Kc";
1120 break;
1121 case PRID_IMP_M14KEC:
1122 c->cputype = CPU_M14KEC;
1123 c->writecombine = _CACHE_UNCACHED;
1124 __cpu_name[cpu] = "MIPS M14KEc";
1125 break;
1126 case PRID_IMP_1004K:
1127 c->cputype = CPU_1004K;
1128 c->writecombine = _CACHE_UNCACHED;
1129 __cpu_name[cpu] = "MIPS 1004Kc";
1130 break;
1131 case PRID_IMP_1074K:
1132 c->cputype = CPU_1074K;
1133 c->writecombine = _CACHE_UNCACHED;
1134 __cpu_name[cpu] = "MIPS 1074Kc";
1135 break;
1136 case PRID_IMP_INTERAPTIV_UP:
1137 c->cputype = CPU_INTERAPTIV;
1138 __cpu_name[cpu] = "MIPS interAptiv";
1139 break;
1140 case PRID_IMP_INTERAPTIV_MP:
1141 c->cputype = CPU_INTERAPTIV;
1142 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1143 break;
1144 case PRID_IMP_PROAPTIV_UP:
1145 c->cputype = CPU_PROAPTIV;
1146 __cpu_name[cpu] = "MIPS proAptiv";
1147 break;
1148 case PRID_IMP_PROAPTIV_MP:
1149 c->cputype = CPU_PROAPTIV;
1150 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1151 break;
1152 case PRID_IMP_P5600:
1153 c->cputype = CPU_P5600;
1154 __cpu_name[cpu] = "MIPS P5600";
1155 break;
1156 case PRID_IMP_I6400:
1157 c->cputype = CPU_I6400;
1158 __cpu_name[cpu] = "MIPS I6400";
1159 break;
1160 case PRID_IMP_M5150:
1161 c->cputype = CPU_M5150;
1162 __cpu_name[cpu] = "MIPS M5150";
1163 break;
1164 }
1165
1166 decode_configs(c);
1167
1168 spram_config();
1169 }
1170
1171 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1172 {
1173 decode_configs(c);
1174 switch (c->processor_id & PRID_IMP_MASK) {
1175 case PRID_IMP_AU1_REV1:
1176 case PRID_IMP_AU1_REV2:
1177 c->cputype = CPU_ALCHEMY;
1178 switch ((c->processor_id >> 24) & 0xff) {
1179 case 0:
1180 __cpu_name[cpu] = "Au1000";
1181 break;
1182 case 1:
1183 __cpu_name[cpu] = "Au1500";
1184 break;
1185 case 2:
1186 __cpu_name[cpu] = "Au1100";
1187 break;
1188 case 3:
1189 __cpu_name[cpu] = "Au1550";
1190 break;
1191 case 4:
1192 __cpu_name[cpu] = "Au1200";
1193 if ((c->processor_id & PRID_REV_MASK) == 2)
1194 __cpu_name[cpu] = "Au1250";
1195 break;
1196 case 5:
1197 __cpu_name[cpu] = "Au1210";
1198 break;
1199 default:
1200 __cpu_name[cpu] = "Au1xxx";
1201 break;
1202 }
1203 break;
1204 }
1205 }
1206
1207 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1208 {
1209 decode_configs(c);
1210
1211 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1212 switch (c->processor_id & PRID_IMP_MASK) {
1213 case PRID_IMP_SB1:
1214 c->cputype = CPU_SB1;
1215 __cpu_name[cpu] = "SiByte SB1";
1216 /* FPU in pass1 is known to have issues. */
1217 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1218 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1219 break;
1220 case PRID_IMP_SB1A:
1221 c->cputype = CPU_SB1A;
1222 __cpu_name[cpu] = "SiByte SB1A";
1223 break;
1224 }
1225 }
1226
1227 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1228 {
1229 decode_configs(c);
1230 switch (c->processor_id & PRID_IMP_MASK) {
1231 case PRID_IMP_SR71000:
1232 c->cputype = CPU_SR71000;
1233 __cpu_name[cpu] = "Sandcraft SR71000";
1234 c->scache.ways = 8;
1235 c->tlbsize = 64;
1236 break;
1237 }
1238 }
1239
1240 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1241 {
1242 decode_configs(c);
1243 switch (c->processor_id & PRID_IMP_MASK) {
1244 case PRID_IMP_PR4450:
1245 c->cputype = CPU_PR4450;
1246 __cpu_name[cpu] = "Philips PR4450";
1247 set_isa(c, MIPS_CPU_ISA_M32R1);
1248 break;
1249 }
1250 }
1251
1252 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1253 {
1254 decode_configs(c);
1255 switch (c->processor_id & PRID_IMP_MASK) {
1256 case PRID_IMP_BMIPS32_REV4:
1257 case PRID_IMP_BMIPS32_REV8:
1258 c->cputype = CPU_BMIPS32;
1259 __cpu_name[cpu] = "Broadcom BMIPS32";
1260 set_elf_platform(cpu, "bmips32");
1261 break;
1262 case PRID_IMP_BMIPS3300:
1263 case PRID_IMP_BMIPS3300_ALT:
1264 case PRID_IMP_BMIPS3300_BUG:
1265 c->cputype = CPU_BMIPS3300;
1266 __cpu_name[cpu] = "Broadcom BMIPS3300";
1267 set_elf_platform(cpu, "bmips3300");
1268 break;
1269 case PRID_IMP_BMIPS43XX: {
1270 int rev = c->processor_id & PRID_REV_MASK;
1271
1272 if (rev >= PRID_REV_BMIPS4380_LO &&
1273 rev <= PRID_REV_BMIPS4380_HI) {
1274 c->cputype = CPU_BMIPS4380;
1275 __cpu_name[cpu] = "Broadcom BMIPS4380";
1276 set_elf_platform(cpu, "bmips4380");
1277 } else {
1278 c->cputype = CPU_BMIPS4350;
1279 __cpu_name[cpu] = "Broadcom BMIPS4350";
1280 set_elf_platform(cpu, "bmips4350");
1281 }
1282 break;
1283 }
1284 case PRID_IMP_BMIPS5000:
1285 case PRID_IMP_BMIPS5200:
1286 c->cputype = CPU_BMIPS5000;
1287 __cpu_name[cpu] = "Broadcom BMIPS5000";
1288 set_elf_platform(cpu, "bmips5000");
1289 c->options |= MIPS_CPU_ULRI;
1290 break;
1291 }
1292 }
1293
1294 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1295 {
1296 decode_configs(c);
1297 switch (c->processor_id & PRID_IMP_MASK) {
1298 case PRID_IMP_CAVIUM_CN38XX:
1299 case PRID_IMP_CAVIUM_CN31XX:
1300 case PRID_IMP_CAVIUM_CN30XX:
1301 c->cputype = CPU_CAVIUM_OCTEON;
1302 __cpu_name[cpu] = "Cavium Octeon";
1303 goto platform;
1304 case PRID_IMP_CAVIUM_CN58XX:
1305 case PRID_IMP_CAVIUM_CN56XX:
1306 case PRID_IMP_CAVIUM_CN50XX:
1307 case PRID_IMP_CAVIUM_CN52XX:
1308 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1309 __cpu_name[cpu] = "Cavium Octeon+";
1310 platform:
1311 set_elf_platform(cpu, "octeon");
1312 break;
1313 case PRID_IMP_CAVIUM_CN61XX:
1314 case PRID_IMP_CAVIUM_CN63XX:
1315 case PRID_IMP_CAVIUM_CN66XX:
1316 case PRID_IMP_CAVIUM_CN68XX:
1317 case PRID_IMP_CAVIUM_CNF71XX:
1318 c->cputype = CPU_CAVIUM_OCTEON2;
1319 __cpu_name[cpu] = "Cavium Octeon II";
1320 set_elf_platform(cpu, "octeon2");
1321 break;
1322 case PRID_IMP_CAVIUM_CN70XX:
1323 case PRID_IMP_CAVIUM_CN78XX:
1324 c->cputype = CPU_CAVIUM_OCTEON3;
1325 __cpu_name[cpu] = "Cavium Octeon III";
1326 set_elf_platform(cpu, "octeon3");
1327 break;
1328 default:
1329 printk(KERN_INFO "Unknown Octeon chip!\n");
1330 c->cputype = CPU_UNKNOWN;
1331 break;
1332 }
1333 }
1334
1335 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1336 {
1337 decode_configs(c);
1338 /* JZRISC does not implement the CP0 counter. */
1339 c->options &= ~MIPS_CPU_COUNTER;
1340 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1341 switch (c->processor_id & PRID_IMP_MASK) {
1342 case PRID_IMP_JZRISC:
1343 c->cputype = CPU_JZRISC;
1344 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1345 __cpu_name[cpu] = "Ingenic JZRISC";
1346 break;
1347 default:
1348 panic("Unknown Ingenic Processor ID!");
1349 break;
1350 }
1351 }
1352
1353 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1354 {
1355 decode_configs(c);
1356
1357 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1358 c->cputype = CPU_ALCHEMY;
1359 __cpu_name[cpu] = "Au1300";
1360 /* following stuff is not for Alchemy */
1361 return;
1362 }
1363
1364 c->options = (MIPS_CPU_TLB |
1365 MIPS_CPU_4KEX |
1366 MIPS_CPU_COUNTER |
1367 MIPS_CPU_DIVEC |
1368 MIPS_CPU_WATCH |
1369 MIPS_CPU_EJTAG |
1370 MIPS_CPU_LLSC);
1371
1372 switch (c->processor_id & PRID_IMP_MASK) {
1373 case PRID_IMP_NETLOGIC_XLP2XX:
1374 case PRID_IMP_NETLOGIC_XLP9XX:
1375 case PRID_IMP_NETLOGIC_XLP5XX:
1376 c->cputype = CPU_XLP;
1377 __cpu_name[cpu] = "Broadcom XLPII";
1378 break;
1379
1380 case PRID_IMP_NETLOGIC_XLP8XX:
1381 case PRID_IMP_NETLOGIC_XLP3XX:
1382 c->cputype = CPU_XLP;
1383 __cpu_name[cpu] = "Netlogic XLP";
1384 break;
1385
1386 case PRID_IMP_NETLOGIC_XLR732:
1387 case PRID_IMP_NETLOGIC_XLR716:
1388 case PRID_IMP_NETLOGIC_XLR532:
1389 case PRID_IMP_NETLOGIC_XLR308:
1390 case PRID_IMP_NETLOGIC_XLR532C:
1391 case PRID_IMP_NETLOGIC_XLR516C:
1392 case PRID_IMP_NETLOGIC_XLR508C:
1393 case PRID_IMP_NETLOGIC_XLR308C:
1394 c->cputype = CPU_XLR;
1395 __cpu_name[cpu] = "Netlogic XLR";
1396 break;
1397
1398 case PRID_IMP_NETLOGIC_XLS608:
1399 case PRID_IMP_NETLOGIC_XLS408:
1400 case PRID_IMP_NETLOGIC_XLS404:
1401 case PRID_IMP_NETLOGIC_XLS208:
1402 case PRID_IMP_NETLOGIC_XLS204:
1403 case PRID_IMP_NETLOGIC_XLS108:
1404 case PRID_IMP_NETLOGIC_XLS104:
1405 case PRID_IMP_NETLOGIC_XLS616B:
1406 case PRID_IMP_NETLOGIC_XLS608B:
1407 case PRID_IMP_NETLOGIC_XLS416B:
1408 case PRID_IMP_NETLOGIC_XLS412B:
1409 case PRID_IMP_NETLOGIC_XLS408B:
1410 case PRID_IMP_NETLOGIC_XLS404B:
1411 c->cputype = CPU_XLR;
1412 __cpu_name[cpu] = "Netlogic XLS";
1413 break;
1414
1415 default:
1416 pr_info("Unknown Netlogic chip id [%02x]!\n",
1417 c->processor_id);
1418 c->cputype = CPU_XLR;
1419 break;
1420 }
1421
1422 if (c->cputype == CPU_XLP) {
1423 set_isa(c, MIPS_CPU_ISA_M64R2);
1424 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1425 /* This will be updated again after all threads are woken up */
1426 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1427 } else {
1428 set_isa(c, MIPS_CPU_ISA_M64R1);
1429 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1430 }
1431 c->kscratch_mask = 0xf;
1432 }
1433
1434 #ifdef CONFIG_64BIT
1435 /* For use by uaccess.h */
1436 u64 __ua_limit;
1437 EXPORT_SYMBOL(__ua_limit);
1438 #endif
1439
1440 const char *__cpu_name[NR_CPUS];
1441 const char *__elf_platform;
1442
1443 void cpu_probe(void)
1444 {
1445 struct cpuinfo_mips *c = &current_cpu_data;
1446 unsigned int cpu = smp_processor_id();
1447
1448 c->processor_id = PRID_IMP_UNKNOWN;
1449 c->fpu_id = FPIR_IMP_NONE;
1450 c->cputype = CPU_UNKNOWN;
1451 c->writecombine = _CACHE_UNCACHED;
1452
1453 c->fpu_csr31 = FPU_CSR_RN;
1454 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1455
1456 c->processor_id = read_c0_prid();
1457 switch (c->processor_id & PRID_COMP_MASK) {
1458 case PRID_COMP_LEGACY:
1459 cpu_probe_legacy(c, cpu);
1460 break;
1461 case PRID_COMP_MIPS:
1462 cpu_probe_mips(c, cpu);
1463 break;
1464 case PRID_COMP_ALCHEMY:
1465 cpu_probe_alchemy(c, cpu);
1466 break;
1467 case PRID_COMP_SIBYTE:
1468 cpu_probe_sibyte(c, cpu);
1469 break;
1470 case PRID_COMP_BROADCOM:
1471 cpu_probe_broadcom(c, cpu);
1472 break;
1473 case PRID_COMP_SANDCRAFT:
1474 cpu_probe_sandcraft(c, cpu);
1475 break;
1476 case PRID_COMP_NXP:
1477 cpu_probe_nxp(c, cpu);
1478 break;
1479 case PRID_COMP_CAVIUM:
1480 cpu_probe_cavium(c, cpu);
1481 break;
1482 case PRID_COMP_INGENIC_D0:
1483 case PRID_COMP_INGENIC_D1:
1484 case PRID_COMP_INGENIC_E1:
1485 cpu_probe_ingenic(c, cpu);
1486 break;
1487 case PRID_COMP_NETLOGIC:
1488 cpu_probe_netlogic(c, cpu);
1489 break;
1490 }
1491
1492 BUG_ON(!__cpu_name[cpu]);
1493 BUG_ON(c->cputype == CPU_UNKNOWN);
1494
1495 /*
1496 * Platform code can force the cpu type to optimize code
1497 * generation. In that case be sure the cpu type is correctly
1498 * manually setup otherwise it could trigger some nasty bugs.
1499 */
1500 BUG_ON(current_cpu_type() != c->cputype);
1501
1502 if (mips_fpu_disabled)
1503 c->options &= ~MIPS_CPU_FPU;
1504
1505 if (mips_dsp_disabled)
1506 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1507
1508 if (mips_htw_disabled) {
1509 c->options &= ~MIPS_CPU_HTW;
1510 write_c0_pwctl(read_c0_pwctl() &
1511 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1512 }
1513
1514 if (c->options & MIPS_CPU_FPU)
1515 cpu_set_fpu_opts(c);
1516 else
1517 cpu_set_nofpu_opts(c);
1518
1519 if (cpu_has_bp_ghist)
1520 write_c0_r10k_diag(read_c0_r10k_diag() |
1521 R10K_DIAG_E_GHIST);
1522
1523 if (cpu_has_mips_r2_r6) {
1524 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1525 /* R2 has Performance Counter Interrupt indicator */
1526 c->options |= MIPS_CPU_PCI;
1527 }
1528 else
1529 c->srsets = 1;
1530
1531 if (cpu_has_mips_r6)
1532 elf_hwcap |= HWCAP_MIPS_R6;
1533
1534 if (cpu_has_msa) {
1535 c->msa_id = cpu_get_msa_id();
1536 WARN(c->msa_id & MSA_IR_WRPF,
1537 "Vector register partitioning unimplemented!");
1538 elf_hwcap |= HWCAP_MIPS_MSA;
1539 }
1540
1541 cpu_probe_vmbits(c);
1542
1543 #ifdef CONFIG_64BIT
1544 if (cpu == 0)
1545 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1546 #endif
1547 }
1548
1549 void cpu_report(void)
1550 {
1551 struct cpuinfo_mips *c = &current_cpu_data;
1552
1553 pr_info("CPU%d revision is: %08x (%s)\n",
1554 smp_processor_id(), c->processor_id, cpu_name_string());
1555 if (c->options & MIPS_CPU_FPU)
1556 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1557 if (cpu_has_msa)
1558 pr_info("MSA revision is: %08x\n", c->msa_id);
1559 }
Linux with added FPC-III support