arch/mips/lantiq/xway/reset.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
   7  *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/io.h>
  12 #include <linux/ioport.h>
  13 #include <linux/pm.h>
  14 #include <linux/export.h>
  15 #include <linux/delay.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/reset-controller.h>
  19
  20 #include <asm/reboot.h>
  21
  22 #include <lantiq_soc.h>
  23
  24 #include "../prom.h"
  25
  26 /* reset request register */
  27 #define RCU_RST_REQ             0x0010
  28 /* reset status register */
  29 #define RCU_RST_STAT            0x0014
  30 /* vr9 gphy registers */
  31 #define RCU_GFS_ADD0_XRX200     0x0020
  32 #define RCU_GFS_ADD1_XRX200     0x0068
  33 /* xRX300 gphy registers */
  34 #define RCU_GFS_ADD0_XRX300     0x0020
  35 #define RCU_GFS_ADD1_XRX300     0x0058
  36 #define RCU_GFS_ADD2_XRX300     0x00AC
  37 /* xRX330 gphy registers */
  38 #define RCU_GFS_ADD0_XRX330     0x0020
  39 #define RCU_GFS_ADD1_XRX330     0x0058
  40 #define RCU_GFS_ADD2_XRX330     0x00AC
  41 #define RCU_GFS_ADD3_XRX330     0x0264
  42
  43 /* xbar BE flag */
  44 #define RCU_AHB_ENDIAN          0x004C
  45 #define RCU_VR9_BE_AHB1S        0x00000008
  46
  47 /* reboot bit */
  48 #define RCU_RD_GPHY0_XRX200     BIT(31)
  49 #define RCU_RD_SRST             BIT(30)
  50 #define RCU_RD_GPHY1_XRX200     BIT(29)
  51 /* xRX300 bits */
  52 #define RCU_RD_GPHY0_XRX300     BIT(31)
  53 #define RCU_RD_GPHY1_XRX300     BIT(29)
  54 #define RCU_RD_GPHY2_XRX300     BIT(28)
  55 /* xRX330 bits */
  56 #define RCU_RD_GPHY0_XRX330     BIT(31)
  57 #define RCU_RD_GPHY1_XRX330     BIT(29)
  58 #define RCU_RD_GPHY2_XRX330     BIT(28)
  59 #define RCU_RD_GPHY3_XRX330     BIT(10)
  60
  61 /* reset cause */
  62 #define RCU_STAT_SHIFT          26
  63 /* boot selection */
  64 #define RCU_BOOT_SEL(x)         ((x >> 18) & 0x7)
  65 #define RCU_BOOT_SEL_XRX200(x)  (((x >> 17) & 0xf) | ((x >> 8) & 0x10))
  66
  67 /* dwc2 USB configuration registers */
  68 #define RCU_USB1CFG             0x0018
  69 #define RCU_USB2CFG             0x0034
  70
  71 /* USB DMA endianness bits */
  72 #define RCU_USBCFG_HDSEL_BIT    BIT(11)
  73 #define RCU_USBCFG_HOST_END_BIT BIT(10)
  74 #define RCU_USBCFG_SLV_END_BIT  BIT(9)
  75
  76 /* USB reset bits */
  77 #define RCU_USBRESET            0x0010
  78
  79 #define USBRESET_BIT            BIT(4)
  80
  81 #define RCU_USBRESET2           0x0048
  82
  83 #define USB1RESET_BIT           BIT(4)
  84 #define USB2RESET_BIT           BIT(5)
  85
  86 #define RCU_CFG1A               0x0038
  87 #define RCU_CFG1B               0x003C
  88
  89 /* USB PMU devices */
  90 #define PMU_AHBM                BIT(15)
  91 #define PMU_USB0                BIT(6)
  92 #define PMU_USB1                BIT(27)
  93
  94 /* USB PHY PMU devices */
  95 #define PMU_USB0_P              BIT(0)
  96 #define PMU_USB1_P              BIT(26)
  97
  98 /* remapped base addr of the reset control unit */
  99 static void __iomem *ltq_rcu_membase;
 100 static struct device_node *ltq_rcu_np;
 101 static DEFINE_SPINLOCK(ltq_rcu_lock);
 102
 103 static void ltq_rcu_w32(uint32_t val, uint32_t reg_off)
 104 {
 105         ltq_w32(val, ltq_rcu_membase + reg_off);
 106 }
 107
 108 static uint32_t ltq_rcu_r32(uint32_t reg_off)
 109 {
 110         return ltq_r32(ltq_rcu_membase + reg_off);
 111 }
 112
 113 static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
 114 {
 115         unsigned long flags;
 116
 117         spin_lock_irqsave(&ltq_rcu_lock, flags);
 118         ltq_rcu_w32((ltq_rcu_r32(reg_off) & ~(clr)) | (set), reg_off);
 119         spin_unlock_irqrestore(&ltq_rcu_lock, flags);
 120 }
 121
 122 /* This function is used by the watchdog driver */
 123 int ltq_reset_cause(void)
 124 {
 125         u32 val = ltq_rcu_r32(RCU_RST_STAT);
 126         return val >> RCU_STAT_SHIFT;
 127 }
 128 EXPORT_SYMBOL_GPL(ltq_reset_cause);
 129
 130 /* allow platform code to find out what source we booted from */
 131 unsigned char ltq_boot_select(void)
 132 {
 133         u32 val = ltq_rcu_r32(RCU_RST_STAT);
 134
 135         if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
 136                 return RCU_BOOT_SEL_XRX200(val);
 137
 138         return RCU_BOOT_SEL(val);
 139 }
 140
 141 struct ltq_gphy_reset {
 142         u32 rd;
 143         u32 addr;
 144 };
 145
 146 /* reset / boot a gphy */
 147 static struct ltq_gphy_reset xrx200_gphy[] = {
 148         {RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200},
 149         {RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200},
 150 };
 151
 152 /* reset / boot a gphy */
 153 static struct ltq_gphy_reset xrx300_gphy[] = {
 154         {RCU_RD_GPHY0_XRX300, RCU_GFS_ADD0_XRX300},
 155         {RCU_RD_GPHY1_XRX300, RCU_GFS_ADD1_XRX300},
 156         {RCU_RD_GPHY2_XRX300, RCU_GFS_ADD2_XRX300},
 157 };
 158
 159 /* reset / boot a gphy */
 160 static struct ltq_gphy_reset xrx330_gphy[] = {
 161         {RCU_RD_GPHY0_XRX330, RCU_GFS_ADD0_XRX330},
 162         {RCU_RD_GPHY1_XRX330, RCU_GFS_ADD1_XRX330},
 163         {RCU_RD_GPHY2_XRX330, RCU_GFS_ADD2_XRX330},
 164         {RCU_RD_GPHY3_XRX330, RCU_GFS_ADD3_XRX330},
 165 };
 166
 167 static void xrx200_gphy_boot_addr(struct ltq_gphy_reset *phy_regs,
 168                                   dma_addr_t dev_addr)
 169 {
 170         ltq_rcu_w32_mask(0, phy_regs->rd, RCU_RST_REQ);
 171         ltq_rcu_w32(dev_addr, phy_regs->addr);
 172         ltq_rcu_w32_mask(phy_regs->rd, 0,  RCU_RST_REQ);
 173 }
 174
 175 /* reset and boot a gphy. these phys only exist on xrx200 SoC */
 176 int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
 177 {
 178         struct clk *clk;
 179
 180         if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
 181                 dev_err(dev, "this SoC has no GPHY\n");
 182                 return -EINVAL;
 183         }
 184
 185         if (of_machine_is_compatible("lantiq,vr9")) {
 186                 clk = clk_get_sys("1f203000.rcu", "gphy");
 187                 if (IS_ERR(clk))
 188                         return PTR_ERR(clk);
 189                 clk_enable(clk);
 190         }
 191
 192         dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr);
 193
 194         if (of_machine_is_compatible("lantiq,vr9")) {
 195                 if (id >= ARRAY_SIZE(xrx200_gphy)) {
 196                         dev_err(dev, "%u is an invalid gphy id\n", id);
 197                         return -EINVAL;
 198                 }
 199                 xrx200_gphy_boot_addr(&xrx200_gphy[id], dev_addr);
 200         } else if (of_machine_is_compatible("lantiq,ar10")) {
 201                 if (id >= ARRAY_SIZE(xrx300_gphy)) {
 202                         dev_err(dev, "%u is an invalid gphy id\n", id);
 203                         return -EINVAL;
 204                 }
 205                 xrx200_gphy_boot_addr(&xrx300_gphy[id], dev_addr);
 206         } else if (of_machine_is_compatible("lantiq,grx390")) {
 207                 if (id >= ARRAY_SIZE(xrx330_gphy)) {
 208                         dev_err(dev, "%u is an invalid gphy id\n", id);
 209                         return -EINVAL;
 210                 }
 211                 xrx200_gphy_boot_addr(&xrx330_gphy[id], dev_addr);
 212         }
 213         return 0;
 214 }
 215
 216 /* reset a io domain for u micro seconds */
 217 void ltq_reset_once(unsigned int module, ulong u)
 218 {
 219         ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
 220         udelay(u);
 221         ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
 222 }
 223
 224 static int ltq_assert_device(struct reset_controller_dev *rcdev,
 225                                 unsigned long id)
 226 {
 227         u32 val;
 228
 229         if (id < 8)
 230                 return -1;
 231
 232         val = ltq_rcu_r32(RCU_RST_REQ);
 233         val |= BIT(id);
 234         ltq_rcu_w32(val, RCU_RST_REQ);
 235
 236         return 0;
 237 }
 238
 239 static int ltq_deassert_device(struct reset_controller_dev *rcdev,
 240                                   unsigned long id)
 241 {
 242         u32 val;
 243
 244         if (id < 8)
 245                 return -1;
 246
 247         val = ltq_rcu_r32(RCU_RST_REQ);
 248         val &= ~BIT(id);
 249         ltq_rcu_w32(val, RCU_RST_REQ);
 250
 251         return 0;
 252 }
 253
 254 static int ltq_reset_device(struct reset_controller_dev *rcdev,
 255                                unsigned long id)
 256 {
 257         ltq_assert_device(rcdev, id);
 258         return ltq_deassert_device(rcdev, id);
 259 }
 260
 261 static struct reset_control_ops reset_ops = {
 262         .reset = ltq_reset_device,
 263         .assert = ltq_assert_device,
 264         .deassert = ltq_deassert_device,
 265 };
 266
 267 static struct reset_controller_dev reset_dev = {
 268         .ops                    = &reset_ops,
 269         .owner                  = THIS_MODULE,
 270         .nr_resets              = 32,
 271         .of_reset_n_cells       = 1,
 272 };
 273
 274 void ltq_rst_init(void)
 275 {
 276         reset_dev.of_node = of_find_compatible_node(NULL, NULL,
 277                                                 "lantiq,xway-reset");
 278         if (!reset_dev.of_node)
 279                 pr_err("Failed to find reset controller node");
 280         else
 281                 reset_controller_register(&reset_dev);
 282 }
 283
 284 static void ltq_machine_restart(char *command)
 285 {
 286         u32 val = ltq_rcu_r32(RCU_RST_REQ);
 287
 288         if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
 289                 val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200;
 290
 291         val |= RCU_RD_SRST;
 292
 293         local_irq_disable();
 294         ltq_rcu_w32(val, RCU_RST_REQ);
 295         unreachable();
 296 }
 297
 298 static void ltq_machine_halt(void)
 299 {
 300         local_irq_disable();
 301         unreachable();
 302 }
 303
 304 static void ltq_machine_power_off(void)
 305 {
 306         local_irq_disable();
 307         unreachable();
 308 }
 309
 310 static void ltq_usb_init(void)
 311 {
 312         /* Power for USB cores 1 & 2 */
 313         ltq_pmu_enable(PMU_AHBM);
 314         ltq_pmu_enable(PMU_USB0);
 315         ltq_pmu_enable(PMU_USB1);
 316
 317         ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
 318         ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
 319
 320         /* Enable USB PHY power for cores 1 & 2 */
 321         ltq_pmu_enable(PMU_USB0_P);
 322         ltq_pmu_enable(PMU_USB1_P);
 323
 324         /* Configure cores to host mode */
 325         ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
 326                 RCU_USB1CFG);
 327         ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
 328                 RCU_USB2CFG);
 329
 330         /* Select DMA endianness (Host-endian: big-endian) */
 331         ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
 332                 | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
 333         ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
 334                 | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
 335
 336         /* Hard reset USB state machines */
 337         ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
 338         udelay(50 * 1000);
 339         ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
 340
 341         /* Soft reset USB state machines */
 342         ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
 343                 | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
 344         udelay(50 * 1000);
 345         ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
 346                 & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
 347 }
 348
 349 static int __init mips_reboot_setup(void)
 350 {
 351         struct resource res;
 352
 353         ltq_rcu_np = of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway");
 354         if (!ltq_rcu_np)
 355                 ltq_rcu_np = of_find_compatible_node(NULL, NULL,
 356                                                         "lantiq,rcu-xrx200");
 357
 358         /* check if all the reset register range is available */
 359         if (!ltq_rcu_np)
 360                 panic("Failed to load reset resources from devicetree");
 361
 362         if (of_address_to_resource(ltq_rcu_np, 0, &res))
 363                 panic("Failed to get rcu memory range");
 364
 365         if (!request_mem_region(res.start, resource_size(&res), res.name))
 366                 pr_err("Failed to request rcu memory");
 367
 368         ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res));
 369         if (!ltq_rcu_membase)
 370                 panic("Failed to remap core memory");
 371
 372         if (of_machine_is_compatible("lantiq,ar9") ||
 373             of_machine_is_compatible("lantiq,vr9"))
 374                 ltq_usb_init();
 375
 376         if (of_machine_is_compatible("lantiq,vr9"))
 377                 ltq_rcu_w32(ltq_rcu_r32(RCU_AHB_ENDIAN) | RCU_VR9_BE_AHB1S,
 378                             RCU_AHB_ENDIAN);
 379
 380         _machine_restart = ltq_machine_restart;
 381         _machine_halt = ltq_machine_halt;
 382         pm_power_off = ltq_machine_power_off;
 383
 384         return 0;
 385 }
 386
 387 arch_initcall(mips_reboot_setup);