2 * Copyright (C) 2010, 2011, 2012, Lemote, Inc.
3 * Author: Chen Huacai, chenhc@lemote.com
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/init.h>
18 #include <linux/cpu.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/cpufreq.h>
22 #include <asm/processor.h>
24 #include <asm/clock.h>
25 #include <asm/tlbflush.h>
26 #include <asm/cacheflush.h>
28 #include <workarounds.h>
32 DEFINE_PER_CPU(int, cpu_state
);
33 DEFINE_PER_CPU(uint32_t, core0_c0count
);
35 static void *ipi_set0_regs
[16];
36 static void *ipi_clear0_regs
[16];
37 static void *ipi_status0_regs
[16];
38 static void *ipi_en0_regs
[16];
39 static void *ipi_mailbox_buf
[16];
41 /* read a 32bit value from ipi register */
42 #define loongson3_ipi_read32(addr) readl(addr)
43 /* read a 64bit value from ipi register */
44 #define loongson3_ipi_read64(addr) readq(addr)
45 /* write a 32bit value to ipi register */
46 #define loongson3_ipi_write32(action, addr) \
48 writel(action, addr); \
51 /* write a 64bit value to ipi register */
52 #define loongson3_ipi_write64(action, addr) \
54 writeq(action, addr); \
58 static void ipi_set0_regs_init(void)
60 ipi_set0_regs
[0] = (void *)
61 (SMP_CORE_GROUP0_BASE
+ SMP_CORE0_OFFSET
+ SET0
);
62 ipi_set0_regs
[1] = (void *)
63 (SMP_CORE_GROUP0_BASE
+ SMP_CORE1_OFFSET
+ SET0
);
64 ipi_set0_regs
[2] = (void *)
65 (SMP_CORE_GROUP0_BASE
+ SMP_CORE2_OFFSET
+ SET0
);
66 ipi_set0_regs
[3] = (void *)
67 (SMP_CORE_GROUP0_BASE
+ SMP_CORE3_OFFSET
+ SET0
);
68 ipi_set0_regs
[4] = (void *)
69 (SMP_CORE_GROUP1_BASE
+ SMP_CORE0_OFFSET
+ SET0
);
70 ipi_set0_regs
[5] = (void *)
71 (SMP_CORE_GROUP1_BASE
+ SMP_CORE1_OFFSET
+ SET0
);
72 ipi_set0_regs
[6] = (void *)
73 (SMP_CORE_GROUP1_BASE
+ SMP_CORE2_OFFSET
+ SET0
);
74 ipi_set0_regs
[7] = (void *)
75 (SMP_CORE_GROUP1_BASE
+ SMP_CORE3_OFFSET
+ SET0
);
76 ipi_set0_regs
[8] = (void *)
77 (SMP_CORE_GROUP2_BASE
+ SMP_CORE0_OFFSET
+ SET0
);
78 ipi_set0_regs
[9] = (void *)
79 (SMP_CORE_GROUP2_BASE
+ SMP_CORE1_OFFSET
+ SET0
);
80 ipi_set0_regs
[10] = (void *)
81 (SMP_CORE_GROUP2_BASE
+ SMP_CORE2_OFFSET
+ SET0
);
82 ipi_set0_regs
[11] = (void *)
83 (SMP_CORE_GROUP2_BASE
+ SMP_CORE3_OFFSET
+ SET0
);
84 ipi_set0_regs
[12] = (void *)
85 (SMP_CORE_GROUP3_BASE
+ SMP_CORE0_OFFSET
+ SET0
);
86 ipi_set0_regs
[13] = (void *)
87 (SMP_CORE_GROUP3_BASE
+ SMP_CORE1_OFFSET
+ SET0
);
88 ipi_set0_regs
[14] = (void *)
89 (SMP_CORE_GROUP3_BASE
+ SMP_CORE2_OFFSET
+ SET0
);
90 ipi_set0_regs
[15] = (void *)
91 (SMP_CORE_GROUP3_BASE
+ SMP_CORE3_OFFSET
+ SET0
);
94 static void ipi_clear0_regs_init(void)
96 ipi_clear0_regs
[0] = (void *)
97 (SMP_CORE_GROUP0_BASE
+ SMP_CORE0_OFFSET
+ CLEAR0
);
98 ipi_clear0_regs
[1] = (void *)
99 (SMP_CORE_GROUP0_BASE
+ SMP_CORE1_OFFSET
+ CLEAR0
);
100 ipi_clear0_regs
[2] = (void *)
101 (SMP_CORE_GROUP0_BASE
+ SMP_CORE2_OFFSET
+ CLEAR0
);
102 ipi_clear0_regs
[3] = (void *)
103 (SMP_CORE_GROUP0_BASE
+ SMP_CORE3_OFFSET
+ CLEAR0
);
104 ipi_clear0_regs
[4] = (void *)
105 (SMP_CORE_GROUP1_BASE
+ SMP_CORE0_OFFSET
+ CLEAR0
);
106 ipi_clear0_regs
[5] = (void *)
107 (SMP_CORE_GROUP1_BASE
+ SMP_CORE1_OFFSET
+ CLEAR0
);
108 ipi_clear0_regs
[6] = (void *)
109 (SMP_CORE_GROUP1_BASE
+ SMP_CORE2_OFFSET
+ CLEAR0
);
110 ipi_clear0_regs
[7] = (void *)
111 (SMP_CORE_GROUP1_BASE
+ SMP_CORE3_OFFSET
+ CLEAR0
);
112 ipi_clear0_regs
[8] = (void *)
113 (SMP_CORE_GROUP2_BASE
+ SMP_CORE0_OFFSET
+ CLEAR0
);
114 ipi_clear0_regs
[9] = (void *)
115 (SMP_CORE_GROUP2_BASE
+ SMP_CORE1_OFFSET
+ CLEAR0
);
116 ipi_clear0_regs
[10] = (void *)
117 (SMP_CORE_GROUP2_BASE
+ SMP_CORE2_OFFSET
+ CLEAR0
);
118 ipi_clear0_regs
[11] = (void *)
119 (SMP_CORE_GROUP2_BASE
+ SMP_CORE3_OFFSET
+ CLEAR0
);
120 ipi_clear0_regs
[12] = (void *)
121 (SMP_CORE_GROUP3_BASE
+ SMP_CORE0_OFFSET
+ CLEAR0
);
122 ipi_clear0_regs
[13] = (void *)
123 (SMP_CORE_GROUP3_BASE
+ SMP_CORE1_OFFSET
+ CLEAR0
);
124 ipi_clear0_regs
[14] = (void *)
125 (SMP_CORE_GROUP3_BASE
+ SMP_CORE2_OFFSET
+ CLEAR0
);
126 ipi_clear0_regs
[15] = (void *)
127 (SMP_CORE_GROUP3_BASE
+ SMP_CORE3_OFFSET
+ CLEAR0
);
130 static void ipi_status0_regs_init(void)
132 ipi_status0_regs
[0] = (void *)
133 (SMP_CORE_GROUP0_BASE
+ SMP_CORE0_OFFSET
+ STATUS0
);
134 ipi_status0_regs
[1] = (void *)
135 (SMP_CORE_GROUP0_BASE
+ SMP_CORE1_OFFSET
+ STATUS0
);
136 ipi_status0_regs
[2] = (void *)
137 (SMP_CORE_GROUP0_BASE
+ SMP_CORE2_OFFSET
+ STATUS0
);
138 ipi_status0_regs
[3] = (void *)
139 (SMP_CORE_GROUP0_BASE
+ SMP_CORE3_OFFSET
+ STATUS0
);
140 ipi_status0_regs
[4] = (void *)
141 (SMP_CORE_GROUP1_BASE
+ SMP_CORE0_OFFSET
+ STATUS0
);
142 ipi_status0_regs
[5] = (void *)
143 (SMP_CORE_GROUP1_BASE
+ SMP_CORE1_OFFSET
+ STATUS0
);
144 ipi_status0_regs
[6] = (void *)
145 (SMP_CORE_GROUP1_BASE
+ SMP_CORE2_OFFSET
+ STATUS0
);
146 ipi_status0_regs
[7] = (void *)
147 (SMP_CORE_GROUP1_BASE
+ SMP_CORE3_OFFSET
+ STATUS0
);
148 ipi_status0_regs
[8] = (void *)
149 (SMP_CORE_GROUP2_BASE
+ SMP_CORE0_OFFSET
+ STATUS0
);
150 ipi_status0_regs
[9] = (void *)
151 (SMP_CORE_GROUP2_BASE
+ SMP_CORE1_OFFSET
+ STATUS0
);
152 ipi_status0_regs
[10] = (void *)
153 (SMP_CORE_GROUP2_BASE
+ SMP_CORE2_OFFSET
+ STATUS0
);
154 ipi_status0_regs
[11] = (void *)
155 (SMP_CORE_GROUP2_BASE
+ SMP_CORE3_OFFSET
+ STATUS0
);
156 ipi_status0_regs
[12] = (void *)
157 (SMP_CORE_GROUP3_BASE
+ SMP_CORE0_OFFSET
+ STATUS0
);
158 ipi_status0_regs
[13] = (void *)
159 (SMP_CORE_GROUP3_BASE
+ SMP_CORE1_OFFSET
+ STATUS0
);
160 ipi_status0_regs
[14] = (void *)
161 (SMP_CORE_GROUP3_BASE
+ SMP_CORE2_OFFSET
+ STATUS0
);
162 ipi_status0_regs
[15] = (void *)
163 (SMP_CORE_GROUP3_BASE
+ SMP_CORE3_OFFSET
+ STATUS0
);
166 static void ipi_en0_regs_init(void)
168 ipi_en0_regs
[0] = (void *)
169 (SMP_CORE_GROUP0_BASE
+ SMP_CORE0_OFFSET
+ EN0
);
170 ipi_en0_regs
[1] = (void *)
171 (SMP_CORE_GROUP0_BASE
+ SMP_CORE1_OFFSET
+ EN0
);
172 ipi_en0_regs
[2] = (void *)
173 (SMP_CORE_GROUP0_BASE
+ SMP_CORE2_OFFSET
+ EN0
);
174 ipi_en0_regs
[3] = (void *)
175 (SMP_CORE_GROUP0_BASE
+ SMP_CORE3_OFFSET
+ EN0
);
176 ipi_en0_regs
[4] = (void *)
177 (SMP_CORE_GROUP1_BASE
+ SMP_CORE0_OFFSET
+ EN0
);
178 ipi_en0_regs
[5] = (void *)
179 (SMP_CORE_GROUP1_BASE
+ SMP_CORE1_OFFSET
+ EN0
);
180 ipi_en0_regs
[6] = (void *)
181 (SMP_CORE_GROUP1_BASE
+ SMP_CORE2_OFFSET
+ EN0
);
182 ipi_en0_regs
[7] = (void *)
183 (SMP_CORE_GROUP1_BASE
+ SMP_CORE3_OFFSET
+ EN0
);
184 ipi_en0_regs
[8] = (void *)
185 (SMP_CORE_GROUP2_BASE
+ SMP_CORE0_OFFSET
+ EN0
);
186 ipi_en0_regs
[9] = (void *)
187 (SMP_CORE_GROUP2_BASE
+ SMP_CORE1_OFFSET
+ EN0
);
188 ipi_en0_regs
[10] = (void *)
189 (SMP_CORE_GROUP2_BASE
+ SMP_CORE2_OFFSET
+ EN0
);
190 ipi_en0_regs
[11] = (void *)
191 (SMP_CORE_GROUP2_BASE
+ SMP_CORE3_OFFSET
+ EN0
);
192 ipi_en0_regs
[12] = (void *)
193 (SMP_CORE_GROUP3_BASE
+ SMP_CORE0_OFFSET
+ EN0
);
194 ipi_en0_regs
[13] = (void *)
195 (SMP_CORE_GROUP3_BASE
+ SMP_CORE1_OFFSET
+ EN0
);
196 ipi_en0_regs
[14] = (void *)
197 (SMP_CORE_GROUP3_BASE
+ SMP_CORE2_OFFSET
+ EN0
);
198 ipi_en0_regs
[15] = (void *)
199 (SMP_CORE_GROUP3_BASE
+ SMP_CORE3_OFFSET
+ EN0
);
202 static void ipi_mailbox_buf_init(void)
204 ipi_mailbox_buf
[0] = (void *)
205 (SMP_CORE_GROUP0_BASE
+ SMP_CORE0_OFFSET
+ BUF
);
206 ipi_mailbox_buf
[1] = (void *)
207 (SMP_CORE_GROUP0_BASE
+ SMP_CORE1_OFFSET
+ BUF
);
208 ipi_mailbox_buf
[2] = (void *)
209 (SMP_CORE_GROUP0_BASE
+ SMP_CORE2_OFFSET
+ BUF
);
210 ipi_mailbox_buf
[3] = (void *)
211 (SMP_CORE_GROUP0_BASE
+ SMP_CORE3_OFFSET
+ BUF
);
212 ipi_mailbox_buf
[4] = (void *)
213 (SMP_CORE_GROUP1_BASE
+ SMP_CORE0_OFFSET
+ BUF
);
214 ipi_mailbox_buf
[5] = (void *)
215 (SMP_CORE_GROUP1_BASE
+ SMP_CORE1_OFFSET
+ BUF
);
216 ipi_mailbox_buf
[6] = (void *)
217 (SMP_CORE_GROUP1_BASE
+ SMP_CORE2_OFFSET
+ BUF
);
218 ipi_mailbox_buf
[7] = (void *)
219 (SMP_CORE_GROUP1_BASE
+ SMP_CORE3_OFFSET
+ BUF
);
220 ipi_mailbox_buf
[8] = (void *)
221 (SMP_CORE_GROUP2_BASE
+ SMP_CORE0_OFFSET
+ BUF
);
222 ipi_mailbox_buf
[9] = (void *)
223 (SMP_CORE_GROUP2_BASE
+ SMP_CORE1_OFFSET
+ BUF
);
224 ipi_mailbox_buf
[10] = (void *)
225 (SMP_CORE_GROUP2_BASE
+ SMP_CORE2_OFFSET
+ BUF
);
226 ipi_mailbox_buf
[11] = (void *)
227 (SMP_CORE_GROUP2_BASE
+ SMP_CORE3_OFFSET
+ BUF
);
228 ipi_mailbox_buf
[12] = (void *)
229 (SMP_CORE_GROUP3_BASE
+ SMP_CORE0_OFFSET
+ BUF
);
230 ipi_mailbox_buf
[13] = (void *)
231 (SMP_CORE_GROUP3_BASE
+ SMP_CORE1_OFFSET
+ BUF
);
232 ipi_mailbox_buf
[14] = (void *)
233 (SMP_CORE_GROUP3_BASE
+ SMP_CORE2_OFFSET
+ BUF
);
234 ipi_mailbox_buf
[15] = (void *)
235 (SMP_CORE_GROUP3_BASE
+ SMP_CORE3_OFFSET
+ BUF
);
239 * Simple enough, just poke the appropriate ipi register
241 static void loongson3_send_ipi_single(int cpu
, unsigned int action
)
243 loongson3_ipi_write32((u32
)action
, ipi_set0_regs
[cpu_logical_map(cpu
)]);
247 loongson3_send_ipi_mask(const struct cpumask
*mask
, unsigned int action
)
251 for_each_cpu(i
, mask
)
252 loongson3_ipi_write32((u32
)action
, ipi_set0_regs
[cpu_logical_map(i
)]);
255 void loongson3_ipi_interrupt(struct pt_regs
*regs
)
257 int i
, cpu
= smp_processor_id();
258 unsigned int action
, c0count
;
260 /* Load the ipi register to figure out what we're supposed to do */
261 action
= loongson3_ipi_read32(ipi_status0_regs
[cpu_logical_map(cpu
)]);
263 /* Clear the ipi register to clear the interrupt */
264 loongson3_ipi_write32((u32
)action
, ipi_clear0_regs
[cpu_logical_map(cpu
)]);
266 if (action
& SMP_RESCHEDULE_YOURSELF
)
269 if (action
& SMP_CALL_FUNCTION
) {
271 generic_smp_call_function_interrupt();
275 if (action
& SMP_ASK_C0COUNT
) {
277 c0count
= read_c0_count();
278 for (i
= 1; i
< num_possible_cpus(); i
++)
279 per_cpu(core0_c0count
, i
) = c0count
;
283 #define MAX_LOOPS 1111
285 * SMP init and finish on secondary CPUs
287 static void loongson3_init_secondary(void)
291 unsigned int cpu
= smp_processor_id();
292 unsigned int imask
= STATUSF_IP7
| STATUSF_IP6
|
293 STATUSF_IP3
| STATUSF_IP2
;
295 /* Set interrupt mask, but don't enable */
296 change_c0_status(ST0_IM
, imask
);
298 for (i
= 0; i
< num_possible_cpus(); i
++)
299 loongson3_ipi_write32(0xffffffff, ipi_en0_regs
[cpu_logical_map(i
)]);
301 per_cpu(cpu_state
, cpu
) = CPU_ONLINE
;
303 cpu_logical_map(cpu
) % loongson_sysconf
.cores_per_package
;
304 cpu_data
[cpu
].package
=
305 cpu_logical_map(cpu
) / loongson_sysconf
.cores_per_package
;
308 __this_cpu_write(core0_c0count
, 0);
309 loongson3_send_ipi_single(0, SMP_ASK_C0COUNT
);
310 while (!__this_cpu_read(core0_c0count
)) {
317 initcount
= __this_cpu_read(core0_c0count
) + i
;
318 write_c0_count(initcount
);
321 static void loongson3_smp_finish(void)
323 int cpu
= smp_processor_id();
325 write_c0_compare(read_c0_count() + mips_hpt_frequency
/HZ
);
327 loongson3_ipi_write64(0,
328 (void *)(ipi_mailbox_buf
[cpu_logical_map(cpu
)]+0x0));
329 pr_info("CPU#%d finished, CP0_ST=%x\n",
330 smp_processor_id(), read_c0_status());
333 static void __init
loongson3_smp_setup(void)
335 int i
= 0, num
= 0; /* i: physical id, num: logical id */
337 init_cpu_possible(cpu_none_mask
);
339 /* For unified kernel, NR_CPUS is the maximum possible value,
340 * loongson_sysconf.nr_cpus is the really present value */
341 while (i
< loongson_sysconf
.nr_cpus
) {
342 if (loongson_sysconf
.reserved_cpus_mask
& (1<<i
)) {
343 /* Reserved physical CPU cores */
344 __cpu_number_map
[i
] = -1;
346 __cpu_number_map
[i
] = num
;
347 __cpu_logical_map
[num
] = i
;
348 set_cpu_possible(num
, true);
353 pr_info("Detected %i available CPU(s)\n", num
);
355 while (num
< loongson_sysconf
.nr_cpus
) {
356 __cpu_logical_map
[num
] = -1;
360 ipi_set0_regs_init();
361 ipi_clear0_regs_init();
362 ipi_status0_regs_init();
364 ipi_mailbox_buf_init();
365 cpu_data
[0].core
= cpu_logical_map(0) % loongson_sysconf
.cores_per_package
;
366 cpu_data
[0].package
= cpu_logical_map(0) / loongson_sysconf
.cores_per_package
;
369 static void __init
loongson3_prepare_cpus(unsigned int max_cpus
)
371 init_cpu_present(cpu_possible_mask
);
372 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
376 * Setup the PC, SP, and GP of a secondary processor and start it runing!
378 static void loongson3_boot_secondary(int cpu
, struct task_struct
*idle
)
380 unsigned long startargs
[4];
382 pr_info("Booting CPU#%d...\n", cpu
);
384 /* startargs[] are initial PC, SP and GP for secondary CPU */
385 startargs
[0] = (unsigned long)&smp_bootstrap
;
386 startargs
[1] = (unsigned long)__KSTK_TOS(idle
);
387 startargs
[2] = (unsigned long)task_thread_info(idle
);
390 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
391 cpu
, startargs
[0], startargs
[1], startargs
[2]);
393 loongson3_ipi_write64(startargs
[3],
394 (void *)(ipi_mailbox_buf
[cpu_logical_map(cpu
)]+0x18));
395 loongson3_ipi_write64(startargs
[2],
396 (void *)(ipi_mailbox_buf
[cpu_logical_map(cpu
)]+0x10));
397 loongson3_ipi_write64(startargs
[1],
398 (void *)(ipi_mailbox_buf
[cpu_logical_map(cpu
)]+0x8));
399 loongson3_ipi_write64(startargs
[0],
400 (void *)(ipi_mailbox_buf
[cpu_logical_map(cpu
)]+0x0));
403 #ifdef CONFIG_HOTPLUG_CPU
405 static int loongson3_cpu_disable(void)
408 unsigned int cpu
= smp_processor_id();
413 set_cpu_online(cpu
, false);
414 cpumask_clear_cpu(cpu
, &cpu_callin_map
);
415 local_irq_save(flags
);
417 local_irq_restore(flags
);
419 local_flush_tlb_all();
425 static void loongson3_cpu_die(unsigned int cpu
)
427 while (per_cpu(cpu_state
, cpu
) != CPU_DEAD
)
433 /* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and
434 * flush all L1 entries at first. Then, another core (usually Core 0) can
435 * safely disable the clock of the target core. loongson3_play_dead() is
436 * called via CKSEG1 (uncached and unmmaped) */
437 static void loongson3a_play_dead(int *state_addr
)
440 register long cpuid
, core
, node
, count
;
441 register void *addr
, *base
, *initfunc
;
443 __asm__
__volatile__(
446 " li %[addr], 0x80000000 \n" /* KSEG0 */
447 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
448 " cache 0, 1(%[addr]) \n"
449 " cache 0, 2(%[addr]) \n"
450 " cache 0, 3(%[addr]) \n"
451 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
452 " cache 1, 1(%[addr]) \n"
453 " cache 1, 2(%[addr]) \n"
454 " cache 1, 3(%[addr]) \n"
455 " addiu %[sets], %[sets], -1 \n"
456 " bnez %[sets], 1b \n"
457 " addiu %[addr], %[addr], 0x20 \n"
458 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
459 " sw %[val], (%[state_addr]) \n"
461 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
463 : [addr
] "=&r" (addr
), [val
] "=&r" (val
)
464 : [state_addr
] "r" (state_addr
),
465 [sets
] "r" (cpu_data
[smp_processor_id()].dcache
.sets
));
467 __asm__
__volatile__(
471 " mfc0 %[cpuid], $15, 1 \n"
472 " andi %[cpuid], 0x3ff \n"
473 " dli %[base], 0x900000003ff01000 \n"
474 " andi %[core], %[cpuid], 0x3 \n"
475 " sll %[core], 8 \n" /* get core id */
476 " or %[base], %[base], %[core] \n"
477 " andi %[node], %[cpuid], 0xc \n"
478 " dsll %[node], 42 \n" /* get node id */
479 " or %[base], %[base], %[node] \n"
480 "1: li %[count], 0x100 \n" /* wait for init loop */
481 "2: bnez %[count], 2b \n" /* limit mailbox access */
482 " addiu %[count], -1 \n"
483 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
484 " beqz %[initfunc], 1b \n"
486 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
487 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
488 " ld $a1, 0x38(%[base]) \n"
489 " jr %[initfunc] \n" /* jump to initial PC */
492 : [core
] "=&r" (core
), [node
] "=&r" (node
),
493 [base
] "=&r" (base
), [cpuid
] "=&r" (cpuid
),
494 [count
] "=&r" (count
), [initfunc
] "=&r" (initfunc
)
499 static void loongson3b_play_dead(int *state_addr
)
502 register long cpuid
, core
, node
, count
;
503 register void *addr
, *base
, *initfunc
;
505 __asm__
__volatile__(
508 " li %[addr], 0x80000000 \n" /* KSEG0 */
509 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
510 " cache 0, 1(%[addr]) \n"
511 " cache 0, 2(%[addr]) \n"
512 " cache 0, 3(%[addr]) \n"
513 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
514 " cache 1, 1(%[addr]) \n"
515 " cache 1, 2(%[addr]) \n"
516 " cache 1, 3(%[addr]) \n"
517 " addiu %[sets], %[sets], -1 \n"
518 " bnez %[sets], 1b \n"
519 " addiu %[addr], %[addr], 0x20 \n"
520 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
521 " sw %[val], (%[state_addr]) \n"
523 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
525 : [addr
] "=&r" (addr
), [val
] "=&r" (val
)
526 : [state_addr
] "r" (state_addr
),
527 [sets
] "r" (cpu_data
[smp_processor_id()].dcache
.sets
));
529 __asm__
__volatile__(
533 " mfc0 %[cpuid], $15, 1 \n"
534 " andi %[cpuid], 0x3ff \n"
535 " dli %[base], 0x900000003ff01000 \n"
536 " andi %[core], %[cpuid], 0x3 \n"
537 " sll %[core], 8 \n" /* get core id */
538 " or %[base], %[base], %[core] \n"
539 " andi %[node], %[cpuid], 0xc \n"
540 " dsll %[node], 42 \n" /* get node id */
541 " or %[base], %[base], %[node] \n"
542 " dsrl %[node], 30 \n" /* 15:14 */
543 " or %[base], %[base], %[node] \n"
544 "1: li %[count], 0x100 \n" /* wait for init loop */
545 "2: bnez %[count], 2b \n" /* limit mailbox access */
546 " addiu %[count], -1 \n"
547 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
548 " beqz %[initfunc], 1b \n"
550 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
551 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
552 " ld $a1, 0x38(%[base]) \n"
553 " jr %[initfunc] \n" /* jump to initial PC */
556 : [core
] "=&r" (core
), [node
] "=&r" (node
),
557 [base
] "=&r" (base
), [cpuid
] "=&r" (cpuid
),
558 [count
] "=&r" (count
), [initfunc
] "=&r" (initfunc
)
566 unsigned int cpu
= smp_processor_id();
567 void (*play_dead_at_ckseg1
)(int *);
570 switch (loongson_sysconf
.cputype
) {
573 play_dead_at_ckseg1
=
574 (void *)CKSEG1ADDR((unsigned long)loongson3a_play_dead
);
577 play_dead_at_ckseg1
=
578 (void *)CKSEG1ADDR((unsigned long)loongson3b_play_dead
);
581 state_addr
= &per_cpu(cpu_state
, cpu
);
583 play_dead_at_ckseg1(state_addr
);
586 void loongson3_disable_clock(int cpu
)
588 uint64_t core_id
= cpu_data
[cpu
].core
;
589 uint64_t package_id
= cpu_data
[cpu
].package
;
591 if (loongson_sysconf
.cputype
== Loongson_3A
) {
592 LOONGSON_CHIPCFG(package_id
) &= ~(1 << (12 + core_id
));
593 } else if (loongson_sysconf
.cputype
== Loongson_3B
) {
594 if (!(loongson_sysconf
.workarounds
& WORKAROUND_CPUHOTPLUG
))
595 LOONGSON_FREQCTRL(package_id
) &= ~(1 << (core_id
* 4 + 3));
599 void loongson3_enable_clock(int cpu
)
601 uint64_t core_id
= cpu_data
[cpu
].core
;
602 uint64_t package_id
= cpu_data
[cpu
].package
;
604 if (loongson_sysconf
.cputype
== Loongson_3A
) {
605 LOONGSON_CHIPCFG(package_id
) |= 1 << (12 + core_id
);
606 } else if (loongson_sysconf
.cputype
== Loongson_3B
) {
607 if (!(loongson_sysconf
.workarounds
& WORKAROUND_CPUHOTPLUG
))
608 LOONGSON_FREQCTRL(package_id
) |= 1 << (core_id
* 4 + 3);
612 #define CPU_POST_DEAD_FROZEN (CPU_POST_DEAD | CPU_TASKS_FROZEN)
613 static int loongson3_cpu_callback(struct notifier_block
*nfb
,
614 unsigned long action
, void *hcpu
)
616 unsigned int cpu
= (unsigned long)hcpu
;
620 case CPU_POST_DEAD_FROZEN
:
621 pr_info("Disable clock for CPU#%d\n", cpu
);
622 loongson3_disable_clock(cpu
);
625 case CPU_UP_PREPARE_FROZEN
:
626 pr_info("Enable clock for CPU#%d\n", cpu
);
627 loongson3_enable_clock(cpu
);
634 static int register_loongson3_notifier(void)
636 hotcpu_notifier(loongson3_cpu_callback
, 0);
639 early_initcall(register_loongson3_notifier
);
643 struct plat_smp_ops loongson3_smp_ops
= {
644 .send_ipi_single
= loongson3_send_ipi_single
,
645 .send_ipi_mask
= loongson3_send_ipi_mask
,
646 .init_secondary
= loongson3_init_secondary
,
647 .smp_finish
= loongson3_smp_finish
,
648 .boot_secondary
= loongson3_boot_secondary
,
649 .smp_setup
= loongson3_smp_setup
,
650 .prepare_cpus
= loongson3_prepare_cpus
,
651 #ifdef CONFIG_HOTPLUG_CPU
652 .cpu_disable
= loongson3_cpu_disable
,
653 .cpu_die
= loongson3_cpu_die
,