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of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / arch / powerpc / include / asm / opal-api.h
blob8374afed9d0a95cb373e94af41d2e2ceeaae9d90
1 /*
2 * OPAL API definitions.
3 *
4 * Copyright 2011-2015 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #ifndef __OPAL_API_H
13 #define __OPAL_API_H
14
15 /****** OPAL APIs ******/
16
17 /* Return codes */
18 #define OPAL_SUCCESS 0
19 #define OPAL_PARAMETER -1
20 #define OPAL_BUSY -2
21 #define OPAL_PARTIAL -3
22 #define OPAL_CONSTRAINED -4
23 #define OPAL_CLOSED -5
24 #define OPAL_HARDWARE -6
25 #define OPAL_UNSUPPORTED -7
26 #define OPAL_PERMISSION -8
27 #define OPAL_NO_MEM -9
28 #define OPAL_RESOURCE -10
29 #define OPAL_INTERNAL_ERROR -11
30 #define OPAL_BUSY_EVENT -12
31 #define OPAL_HARDWARE_FROZEN -13
32 #define OPAL_WRONG_STATE -14
33 #define OPAL_ASYNC_COMPLETION -15
34 #define OPAL_EMPTY -16
35 #define OPAL_I2C_TIMEOUT -17
36 #define OPAL_I2C_INVALID_CMD -18
37 #define OPAL_I2C_LBUS_PARITY -19
38 #define OPAL_I2C_BKEND_OVERRUN -20
39 #define OPAL_I2C_BKEND_ACCESS -21
40 #define OPAL_I2C_ARBT_LOST -22
41 #define OPAL_I2C_NACK_RCVD -23
42 #define OPAL_I2C_STOP_ERR -24
43
44 /* API Tokens (in r0) */
45 #define OPAL_INVALID_CALL -1
46 #define OPAL_TEST 0
47 #define OPAL_CONSOLE_WRITE 1
48 #define OPAL_CONSOLE_READ 2
49 #define OPAL_RTC_READ 3
50 #define OPAL_RTC_WRITE 4
51 #define OPAL_CEC_POWER_DOWN 5
52 #define OPAL_CEC_REBOOT 6
53 #define OPAL_READ_NVRAM 7
54 #define OPAL_WRITE_NVRAM 8
55 #define OPAL_HANDLE_INTERRUPT 9
56 #define OPAL_POLL_EVENTS 10
57 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
58 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
59 #define OPAL_PCI_CONFIG_READ_BYTE 13
60 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
61 #define OPAL_PCI_CONFIG_READ_WORD 15
62 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
63 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
64 #define OPAL_PCI_CONFIG_WRITE_WORD 18
65 #define OPAL_SET_XIVE 19
66 #define OPAL_GET_XIVE 20
67 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
68 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
69 #define OPAL_PCI_EEH_FREEZE_STATUS 23
70 #define OPAL_PCI_SHPC 24
71 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
72 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
73 #define OPAL_PCI_PHB_MMIO_ENABLE 27
74 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
75 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
76 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
77 #define OPAL_PCI_SET_PE 31
78 #define OPAL_PCI_SET_PELTV 32
79 #define OPAL_PCI_SET_MVE 33
80 #define OPAL_PCI_SET_MVE_ENABLE 34
81 #define OPAL_PCI_GET_XIVE_REISSUE 35
82 #define OPAL_PCI_SET_XIVE_REISSUE 36
83 #define OPAL_PCI_SET_XIVE_PE 37
84 #define OPAL_GET_XIVE_SOURCE 38
85 #define OPAL_GET_MSI_32 39
86 #define OPAL_GET_MSI_64 40
87 #define OPAL_START_CPU 41
88 #define OPAL_QUERY_CPU_STATUS 42
89 #define OPAL_WRITE_OPPANEL 43 /* unimplemented */
90 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
91 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
92 #define OPAL_PCI_RESET 49
93 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
94 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
95 #define OPAL_PCI_FENCE_PHB 52
96 #define OPAL_PCI_REINIT 53
97 #define OPAL_PCI_MASK_PE_ERROR 54
98 #define OPAL_SET_SLOT_LED_STATUS 55
99 #define OPAL_GET_EPOW_STATUS 56
100 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
101 #define OPAL_RESERVED1 58
102 #define OPAL_RESERVED2 59
103 #define OPAL_PCI_NEXT_ERROR 60
104 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
105 #define OPAL_PCI_POLL 62
106 #define OPAL_PCI_MSI_EOI 63
107 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
108 #define OPAL_XSCOM_READ 65
109 #define OPAL_XSCOM_WRITE 66
110 #define OPAL_LPC_READ 67
111 #define OPAL_LPC_WRITE 68
112 #define OPAL_RETURN_CPU 69
113 #define OPAL_REINIT_CPUS 70
114 #define OPAL_ELOG_READ 71
115 #define OPAL_ELOG_WRITE 72
116 #define OPAL_ELOG_ACK 73
117 #define OPAL_ELOG_RESEND 74
118 #define OPAL_ELOG_SIZE 75
119 #define OPAL_FLASH_VALIDATE 76
120 #define OPAL_FLASH_MANAGE 77
121 #define OPAL_FLASH_UPDATE 78
122 #define OPAL_RESYNC_TIMEBASE 79
123 #define OPAL_CHECK_TOKEN 80
124 #define OPAL_DUMP_INIT 81
125 #define OPAL_DUMP_INFO 82
126 #define OPAL_DUMP_READ 83
127 #define OPAL_DUMP_ACK 84
128 #define OPAL_GET_MSG 85
129 #define OPAL_CHECK_ASYNC_COMPLETION 86
130 #define OPAL_SYNC_HOST_REBOOT 87
131 #define OPAL_SENSOR_READ 88
132 #define OPAL_GET_PARAM 89
133 #define OPAL_SET_PARAM 90
134 #define OPAL_DUMP_RESEND 91
135 #define OPAL_ELOG_SEND 92 /* Deprecated */
136 #define OPAL_PCI_SET_PHB_CAPI_MODE 93
137 #define OPAL_DUMP_INFO2 94
138 #define OPAL_WRITE_OPPANEL_ASYNC 95
139 #define OPAL_PCI_ERR_INJECT 96
140 #define OPAL_PCI_EEH_FREEZE_SET 97
141 #define OPAL_HANDLE_HMI 98
142 #define OPAL_CONFIG_CPU_IDLE_STATE 99
143 #define OPAL_SLW_SET_REG 100
144 #define OPAL_REGISTER_DUMP_REGION 101
145 #define OPAL_UNREGISTER_DUMP_REGION 102
146 #define OPAL_WRITE_TPO 103
147 #define OPAL_READ_TPO 104
148 #define OPAL_GET_DPO_STATUS 105
149 #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */
150 #define OPAL_IPMI_SEND 107
151 #define OPAL_IPMI_RECV 108
152 #define OPAL_I2C_REQUEST 109
153 #define OPAL_FLASH_READ 110
154 #define OPAL_FLASH_WRITE 111
155 #define OPAL_FLASH_ERASE 112
156 #define OPAL_PRD_MSG 113
157 #define OPAL_LEDS_GET_INDICATOR 114
158 #define OPAL_LEDS_SET_INDICATOR 115
159 #define OPAL_CEC_REBOOT2 116
160 #define OPAL_LAST 116
161
162 /* Device tree flags */
163
164 /* Flags set in power-mgmt nodes in device tree if
165 * respective idle states are supported in the platform.
166 */
167 #define OPAL_PM_NAP_ENABLED 0x00010000
168 #define OPAL_PM_SLEEP_ENABLED 0x00020000
169 #define OPAL_PM_WINKLE_ENABLED 0x00040000
170 #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */
171
172 /*
173 * OPAL_CONFIG_CPU_IDLE_STATE parameters
174 */
175 #define OPAL_CONFIG_IDLE_FASTSLEEP 1
176 #define OPAL_CONFIG_IDLE_UNDO 0
177 #define OPAL_CONFIG_IDLE_APPLY 1
178
179 #ifndef __ASSEMBLY__
180
181 /* Other enums */
182 enum OpalFreezeState {
183 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
184 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
185 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
186 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
187 OPAL_EEH_STOPPED_RESET = 4,
188 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
189 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
190 };
191
192 enum OpalEehFreezeActionToken {
193 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
194 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
195 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
196
197 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
198 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
199 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
200 };
201
202 enum OpalPciStatusToken {
203 OPAL_EEH_NO_ERROR = 0,
204 OPAL_EEH_IOC_ERROR = 1,
205 OPAL_EEH_PHB_ERROR = 2,
206 OPAL_EEH_PE_ERROR = 3,
207 OPAL_EEH_PE_MMIO_ERROR = 4,
208 OPAL_EEH_PE_DMA_ERROR = 5
209 };
210
211 enum OpalPciErrorSeverity {
212 OPAL_EEH_SEV_NO_ERROR = 0,
213 OPAL_EEH_SEV_IOC_DEAD = 1,
214 OPAL_EEH_SEV_PHB_DEAD = 2,
215 OPAL_EEH_SEV_PHB_FENCED = 3,
216 OPAL_EEH_SEV_PE_ER = 4,
217 OPAL_EEH_SEV_INF = 5
218 };
219
220 enum OpalErrinjectType {
221 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
222 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
223 };
224
225 enum OpalErrinjectFunc {
226 /* IOA bus specific errors */
227 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
228 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
229 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
230 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
231 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
232 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
233 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
234 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
235 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
236 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
237 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
238 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
239 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
240 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
241 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
242 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
243 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
244 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
245 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
246 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
247 };
248
249 enum OpalMmioWindowType {
250 OPAL_M32_WINDOW_TYPE = 1,
251 OPAL_M64_WINDOW_TYPE = 2,
252 OPAL_IO_WINDOW_TYPE = 3
253 };
254
255 enum OpalExceptionHandler {
256 OPAL_MACHINE_CHECK_HANDLER = 1,
257 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
258 OPAL_SOFTPATCH_HANDLER = 3
259 };
260
261 enum OpalPendingState {
262 OPAL_EVENT_OPAL_INTERNAL = 0x1,
263 OPAL_EVENT_NVRAM = 0x2,
264 OPAL_EVENT_RTC = 0x4,
265 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
266 OPAL_EVENT_CONSOLE_INPUT = 0x10,
267 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
268 OPAL_EVENT_ERROR_LOG = 0x40,
269 OPAL_EVENT_EPOW = 0x80,
270 OPAL_EVENT_LED_STATUS = 0x100,
271 OPAL_EVENT_PCI_ERROR = 0x200,
272 OPAL_EVENT_DUMP_AVAIL = 0x400,
273 OPAL_EVENT_MSG_PENDING = 0x800,
274 };
275
276 enum OpalThreadStatus {
277 OPAL_THREAD_INACTIVE = 0x0,
278 OPAL_THREAD_STARTED = 0x1,
279 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
280 };
281
282 enum OpalPciBusCompare {
283 OpalPciBusAny = 0, /* Any bus number match */
284 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
285 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
286 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
287 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
288 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
289 OpalPciBusAll = 7, /* Match bus number exactly */
290 };
291
292 enum OpalDeviceCompare {
293 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
294 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
295 };
296
297 enum OpalFuncCompare {
298 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
299 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
300 };
301
302 enum OpalPeAction {
303 OPAL_UNMAP_PE = 0,
304 OPAL_MAP_PE = 1
305 };
306
307 enum OpalPeltvAction {
308 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
309 OPAL_ADD_PE_TO_DOMAIN = 1
310 };
311
312 enum OpalMveEnableAction {
313 OPAL_DISABLE_MVE = 0,
314 OPAL_ENABLE_MVE = 1
315 };
316
317 enum OpalM64Action {
318 OPAL_DISABLE_M64 = 0,
319 OPAL_ENABLE_M64_SPLIT = 1,
320 OPAL_ENABLE_M64_NON_SPLIT = 2
321 };
322
323 enum OpalPciResetScope {
324 OPAL_RESET_PHB_COMPLETE = 1,
325 OPAL_RESET_PCI_LINK = 2,
326 OPAL_RESET_PHB_ERROR = 3,
327 OPAL_RESET_PCI_HOT = 4,
328 OPAL_RESET_PCI_FUNDAMENTAL = 5,
329 OPAL_RESET_PCI_IODA_TABLE = 6
330 };
331
332 enum OpalPciReinitScope {
333 /*
334 * Note: we chose values that do not overlap
335 * OpalPciResetScope as OPAL v2 used the same
336 * enum for both
337 */
338 OPAL_REINIT_PCI_DEV = 1000
339 };
340
341 enum OpalPciResetState {
342 OPAL_DEASSERT_RESET = 0,
343 OPAL_ASSERT_RESET = 1
344 };
345
346 enum OpalSlotLedType {
347 OPAL_SLOT_LED_TYPE_ID = 0, /* IDENTIFY LED */
348 OPAL_SLOT_LED_TYPE_FAULT = 1, /* FAULT LED */
349 OPAL_SLOT_LED_TYPE_ATTN = 2, /* System Attention LED */
350 OPAL_SLOT_LED_TYPE_MAX = 3
351 };
352
353 enum OpalSlotLedState {
354 OPAL_SLOT_LED_STATE_OFF = 0, /* LED is OFF */
355 OPAL_SLOT_LED_STATE_ON = 1 /* LED is ON */
356 };
357
358 /*
359 * Address cycle types for LPC accesses. These also correspond
360 * to the content of the first cell of the "reg" property for
361 * device nodes on the LPC bus
362 */
363 enum OpalLPCAddressType {
364 OPAL_LPC_MEM = 0,
365 OPAL_LPC_IO = 1,
366 OPAL_LPC_FW = 2,
367 };
368
369 enum opal_msg_type {
370 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
371 * additional params function-specific
372 */
373 OPAL_MSG_MEM_ERR,
374 OPAL_MSG_EPOW,
375 OPAL_MSG_SHUTDOWN, /* params[0] = 1 reboot, 0 shutdown */
376 OPAL_MSG_HMI_EVT,
377 OPAL_MSG_DPO,
378 OPAL_MSG_PRD,
379 OPAL_MSG_OCC,
380 OPAL_MSG_TYPE_MAX,
381 };
382
383 struct opal_msg {
384 __be32 msg_type;
385 __be32 reserved;
386 __be64 params[8];
387 };
388
389 /* System parameter permission */
390 enum OpalSysparamPerm {
391 OPAL_SYSPARAM_READ = 0x1,
392 OPAL_SYSPARAM_WRITE = 0x2,
393 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
394 };
395
396 enum {
397 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
398 };
399
400 struct opal_ipmi_msg {
401 uint8_t version;
402 uint8_t netfn;
403 uint8_t cmd;
404 uint8_t data[];
405 };
406
407 /* FSP memory errors handling */
408 enum OpalMemErr_Version {
409 OpalMemErr_V1 = 1,
410 };
411
412 enum OpalMemErrType {
413 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
414 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
415 };
416
417 /* Memory Reilience error type */
418 enum OpalMemErr_ResilErrType {
419 OPAL_MEM_RESILIENCE_CE = 0,
420 OPAL_MEM_RESILIENCE_UE,
421 OPAL_MEM_RESILIENCE_UE_SCRUB,
422 };
423
424 /* Dynamic Memory Deallocation type */
425 enum OpalMemErr_DynErrType {
426 OPAL_MEM_DYNAMIC_DEALLOC = 0,
427 };
428
429 struct OpalMemoryErrorData {
430 enum OpalMemErr_Version version:8; /* 0x00 */
431 enum OpalMemErrType type:8; /* 0x01 */
432 __be16 flags; /* 0x02 */
433 uint8_t reserved_1[4]; /* 0x04 */
434
435 union {
436 /* Memory Resilience corrected/uncorrected error info */
437 struct {
438 enum OpalMemErr_ResilErrType resil_err_type:8;
439 uint8_t reserved_1[7];
440 __be64 physical_address_start;
441 __be64 physical_address_end;
442 } resilience;
443 /* Dynamic memory deallocation error info */
444 struct {
445 enum OpalMemErr_DynErrType dyn_err_type:8;
446 uint8_t reserved_1[7];
447 __be64 physical_address_start;
448 __be64 physical_address_end;
449 } dyn_dealloc;
450 } u;
451 };
452
453 /* HMI interrupt event */
454 enum OpalHMI_Version {
455 OpalHMIEvt_V1 = 1,
456 OpalHMIEvt_V2 = 2,
457 };
458
459 enum OpalHMI_Severity {
460 OpalHMI_SEV_NO_ERROR = 0,
461 OpalHMI_SEV_WARNING = 1,
462 OpalHMI_SEV_ERROR_SYNC = 2,
463 OpalHMI_SEV_FATAL = 3,
464 };
465
466 enum OpalHMI_Disposition {
467 OpalHMI_DISPOSITION_RECOVERED = 0,
468 OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
469 };
470
471 enum OpalHMI_ErrType {
472 OpalHMI_ERROR_MALFUNC_ALERT = 0,
473 OpalHMI_ERROR_PROC_RECOV_DONE,
474 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
475 OpalHMI_ERROR_PROC_RECOV_MASKED,
476 OpalHMI_ERROR_TFAC,
477 OpalHMI_ERROR_TFMR_PARITY,
478 OpalHMI_ERROR_HA_OVERFLOW_WARN,
479 OpalHMI_ERROR_XSCOM_FAIL,
480 OpalHMI_ERROR_XSCOM_DONE,
481 OpalHMI_ERROR_SCOM_FIR,
482 OpalHMI_ERROR_DEBUG_TRIG_FIR,
483 OpalHMI_ERROR_HYP_RESOURCE,
484 OpalHMI_ERROR_CAPP_RECOVERY,
485 };
486
487 enum OpalHMI_XstopType {
488 CHECKSTOP_TYPE_UNKNOWN = 0,
489 CHECKSTOP_TYPE_CORE = 1,
490 CHECKSTOP_TYPE_NX = 2,
491 };
492
493 enum OpalHMI_CoreXstopReason {
494 CORE_CHECKSTOP_IFU_REGFILE = 0x00000001,
495 CORE_CHECKSTOP_IFU_LOGIC = 0x00000002,
496 CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004,
497 CORE_CHECKSTOP_ISU_REGFILE = 0x00000008,
498 CORE_CHECKSTOP_ISU_LOGIC = 0x00000010,
499 CORE_CHECKSTOP_FXU_LOGIC = 0x00000020,
500 CORE_CHECKSTOP_VSU_LOGIC = 0x00000040,
501 CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080,
502 CORE_CHECKSTOP_LSU_REGFILE = 0x00000100,
503 CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200,
504 CORE_CHECKSTOP_LSU_LOGIC = 0x00000400,
505 CORE_CHECKSTOP_PC_LOGIC = 0x00000800,
506 CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000,
507 CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000,
508 CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000,
509 CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000,
510 CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000,
511 };
512
513 enum OpalHMI_NestAccelXstopReason {
514 NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001,
515 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002,
516 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004,
517 NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008,
518 NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010,
519 NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020,
520 NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040,
521 NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080,
522 NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100,
523 NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200,
524 NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400,
525 NX_CHECKSTOP_DMA_CRB_UE = 0x00000800,
526 NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000,
527 NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
528 };
529
530 struct OpalHMIEvent {
531 uint8_t version; /* 0x00 */
532 uint8_t severity; /* 0x01 */
533 uint8_t type; /* 0x02 */
534 uint8_t disposition; /* 0x03 */
535 uint8_t reserved_1[4]; /* 0x04 */
536
537 __be64 hmer;
538 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
539 __be64 tfmr;
540
541 /* version 2 and later */
542 union {
543 /*
544 * checkstop info (Core/NX).
545 * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
546 */
547 struct {
548 uint8_t xstop_type; /* enum OpalHMI_XstopType */
549 uint8_t reserved_1[3];
550 __be32 xstop_reason;
551 union {
552 __be32 pir; /* for CHECKSTOP_TYPE_CORE */
553 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
554 } u;
555 } xstop_error;
556 } u;
557 };
558
559 enum {
560 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
561 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
562 OPAL_P7IOC_DIAG_TYPE_BI = 2,
563 OPAL_P7IOC_DIAG_TYPE_CI = 3,
564 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
565 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
566 OPAL_P7IOC_DIAG_TYPE_LAST = 6
567 };
568
569 struct OpalIoP7IOCErrorData {
570 __be16 type;
571
572 /* GEM */
573 __be64 gemXfir;
574 __be64 gemRfir;
575 __be64 gemRirqfir;
576 __be64 gemMask;
577 __be64 gemRwof;
578
579 /* LEM */
580 __be64 lemFir;
581 __be64 lemErrMask;
582 __be64 lemAction0;
583 __be64 lemAction1;
584 __be64 lemWof;
585
586 union {
587 struct OpalIoP7IOCRgcErrorData {
588 __be64 rgcStatus; /* 3E1C10 */
589 __be64 rgcLdcp; /* 3E1C18 */
590 }rgc;
591 struct OpalIoP7IOCBiErrorData {
592 __be64 biLdcp0; /* 3C0100, 3C0118 */
593 __be64 biLdcp1; /* 3C0108, 3C0120 */
594 __be64 biLdcp2; /* 3C0110, 3C0128 */
595 __be64 biFenceStatus; /* 3C0130, 3C0130 */
596
597 uint8_t biDownbound; /* BI Downbound or Upbound */
598 }bi;
599 struct OpalIoP7IOCCiErrorData {
600 __be64 ciPortStatus; /* 3Dn008 */
601 __be64 ciPortLdcp; /* 3Dn010 */
602
603 uint8_t ciPort; /* Index of CI port: 0/1 */
604 }ci;
605 };
606 };
607
608 /**
609 * This structure defines the overlay which will be used to store PHB error
610 * data upon request.
611 */
612 enum {
613 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
614 };
615
616 enum {
617 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
618 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
619 };
620
621 enum {
622 OPAL_P7IOC_NUM_PEST_REGS = 128,
623 OPAL_PHB3_NUM_PEST_REGS = 256
624 };
625
626 struct OpalIoPhbErrorCommon {
627 __be32 version;
628 __be32 ioType;
629 __be32 len;
630 };
631
632 struct OpalIoP7IOCPhbErrorData {
633 struct OpalIoPhbErrorCommon common;
634
635 __be32 brdgCtl;
636
637 // P7IOC utl regs
638 __be32 portStatusReg;
639 __be32 rootCmplxStatus;
640 __be32 busAgentStatus;
641
642 // P7IOC cfg regs
643 __be32 deviceStatus;
644 __be32 slotStatus;
645 __be32 linkStatus;
646 __be32 devCmdStatus;
647 __be32 devSecStatus;
648
649 // cfg AER regs
650 __be32 rootErrorStatus;
651 __be32 uncorrErrorStatus;
652 __be32 corrErrorStatus;
653 __be32 tlpHdr1;
654 __be32 tlpHdr2;
655 __be32 tlpHdr3;
656 __be32 tlpHdr4;
657 __be32 sourceId;
658
659 __be32 rsv3;
660
661 // Record data about the call to allocate a buffer.
662 __be64 errorClass;
663 __be64 correlator;
664
665 //P7IOC MMIO Error Regs
666 __be64 p7iocPlssr; // n120
667 __be64 p7iocCsr; // n110
668 __be64 lemFir; // nC00
669 __be64 lemErrorMask; // nC18
670 __be64 lemWOF; // nC40
671 __be64 phbErrorStatus; // nC80
672 __be64 phbFirstErrorStatus; // nC88
673 __be64 phbErrorLog0; // nCC0
674 __be64 phbErrorLog1; // nCC8
675 __be64 mmioErrorStatus; // nD00
676 __be64 mmioFirstErrorStatus; // nD08
677 __be64 mmioErrorLog0; // nD40
678 __be64 mmioErrorLog1; // nD48
679 __be64 dma0ErrorStatus; // nD80
680 __be64 dma0FirstErrorStatus; // nD88
681 __be64 dma0ErrorLog0; // nDC0
682 __be64 dma0ErrorLog1; // nDC8
683 __be64 dma1ErrorStatus; // nE00
684 __be64 dma1FirstErrorStatus; // nE08
685 __be64 dma1ErrorLog0; // nE40
686 __be64 dma1ErrorLog1; // nE48
687 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
688 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
689 };
690
691 struct OpalIoPhb3ErrorData {
692 struct OpalIoPhbErrorCommon common;
693
694 __be32 brdgCtl;
695
696 /* PHB3 UTL regs */
697 __be32 portStatusReg;
698 __be32 rootCmplxStatus;
699 __be32 busAgentStatus;
700
701 /* PHB3 cfg regs */
702 __be32 deviceStatus;
703 __be32 slotStatus;
704 __be32 linkStatus;
705 __be32 devCmdStatus;
706 __be32 devSecStatus;
707
708 /* cfg AER regs */
709 __be32 rootErrorStatus;
710 __be32 uncorrErrorStatus;
711 __be32 corrErrorStatus;
712 __be32 tlpHdr1;
713 __be32 tlpHdr2;
714 __be32 tlpHdr3;
715 __be32 tlpHdr4;
716 __be32 sourceId;
717
718 __be32 rsv3;
719
720 /* Record data about the call to allocate a buffer */
721 __be64 errorClass;
722 __be64 correlator;
723
724 /* PHB3 MMIO Error Regs */
725 __be64 nFir; /* 000 */
726 __be64 nFirMask; /* 003 */
727 __be64 nFirWOF; /* 008 */
728 __be64 phbPlssr; /* 120 */
729 __be64 phbCsr; /* 110 */
730 __be64 lemFir; /* C00 */
731 __be64 lemErrorMask; /* C18 */
732 __be64 lemWOF; /* C40 */
733 __be64 phbErrorStatus; /* C80 */
734 __be64 phbFirstErrorStatus; /* C88 */
735 __be64 phbErrorLog0; /* CC0 */
736 __be64 phbErrorLog1; /* CC8 */
737 __be64 mmioErrorStatus; /* D00 */
738 __be64 mmioFirstErrorStatus; /* D08 */
739 __be64 mmioErrorLog0; /* D40 */
740 __be64 mmioErrorLog1; /* D48 */
741 __be64 dma0ErrorStatus; /* D80 */
742 __be64 dma0FirstErrorStatus; /* D88 */
743 __be64 dma0ErrorLog0; /* DC0 */
744 __be64 dma0ErrorLog1; /* DC8 */
745 __be64 dma1ErrorStatus; /* E00 */
746 __be64 dma1FirstErrorStatus; /* E08 */
747 __be64 dma1ErrorLog0; /* E40 */
748 __be64 dma1ErrorLog1; /* E48 */
749 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
750 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
751 };
752
753 enum {
754 OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
755 OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
756 };
757
758 typedef struct oppanel_line {
759 __be64 line;
760 __be64 line_len;
761 } oppanel_line_t;
762
763 enum opal_prd_msg_type {
764 OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */
765 OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */
766 OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */
767 OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */
768 OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */
769 OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */
770 };
771
772 struct opal_prd_msg_header {
773 uint8_t type;
774 uint8_t pad[1];
775 __be16 size;
776 };
777
778 struct opal_prd_msg;
779
780 #define OCC_RESET 0
781 #define OCC_LOAD 1
782 #define OCC_THROTTLE 2
783 #define OCC_MAX_THROTTLE_STATUS 5
784
785 struct opal_occ_msg {
786 __be64 type;
787 __be64 chip;
788 __be64 throttle_status;
789 };
790
791 /*
792 * SG entries
793 *
794 * WARNING: The current implementation requires each entry
795 * to represent a block that is 4k aligned *and* each block
796 * size except the last one in the list to be as well.
797 */
798 struct opal_sg_entry {
799 __be64 data;
800 __be64 length;
801 };
802
803 /*
804 * Candiate image SG list.
805 *
806 * length = VER | length
807 */
808 struct opal_sg_list {
809 __be64 length;
810 __be64 next;
811 struct opal_sg_entry entry[];
812 };
813
814 /*
815 * Dump region ID range usable by the OS
816 */
817 #define OPAL_DUMP_REGION_HOST_START 0x80
818 #define OPAL_DUMP_REGION_LOG_BUF 0x80
819 #define OPAL_DUMP_REGION_HOST_END 0xFF
820
821 /* CAPI modes for PHB */
822 enum {
823 OPAL_PHB_CAPI_MODE_PCIE = 0,
824 OPAL_PHB_CAPI_MODE_CAPI = 1,
825 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
826 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
827 };
828
829 /* OPAL I2C request */
830 struct opal_i2c_request {
831 uint8_t type;
832 #define OPAL_I2C_RAW_READ 0
833 #define OPAL_I2C_RAW_WRITE 1
834 #define OPAL_I2C_SM_READ 2
835 #define OPAL_I2C_SM_WRITE 3
836 uint8_t flags;
837 #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
838 uint8_t subaddr_sz; /* Max 4 */
839 uint8_t reserved;
840 __be16 addr; /* 7 or 10 bit address */
841 __be16 reserved2;
842 __be32 subaddr; /* Sub-address if any */
843 __be32 size; /* Data size */
844 __be64 buffer_ra; /* Buffer real address */
845 };
846
847 /*
848 * EPOW status sharing (OPAL and the host)
849 *
850 * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
851 * with individual elements being 16 bits wide to fetch the system
852 * wide EPOW status. Each element in the buffer will contain the
853 * EPOW status in it's bit representation for a particular EPOW sub
854 * class as defiend here. So multiple detailed EPOW status bits
855 * specific for any sub class can be represented in a single buffer
856 * element as it's bit representation.
857 */
858
859 /* System EPOW type */
860 enum OpalSysEpow {
861 OPAL_SYSEPOW_POWER = 0, /* Power EPOW */
862 OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */
863 OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */
864 OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */
865 };
866
867 /* Power EPOW */
868 enum OpalSysPower {
869 OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */
870 OPAL_SYSPOWER_CHNG = 0x0002, /* System power config change */
871 OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */
872 OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */
873 };
874
875 /* Temperature EPOW */
876 enum OpalSysTemp {
877 OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */
878 OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */
879 OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */
880 };
881
882 /* Cooling EPOW */
883 enum OpalSysCooling {
884 OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */
885 };
886
887 /* Argument to OPAL_CEC_REBOOT2() */
888 enum {
889 OPAL_REBOOT_NORMAL = 0,
890 OPAL_REBOOT_PLATFORM_ERROR = 1,
891 };
892
893 #endif /* __ASSEMBLY__ */
894
895 #endif /* __OPAL_API_H */
Linux with added FPC-III support