arch/powerpc/include/asm/pte-hash64-64k.h

   1 /* To be include by pgtable-hash64.h only */
   2
   3 /* Additional PTE bits (don't change without checking asm in hash_low.S) */
   4 #define _PAGE_SPECIAL   0x00000400 /* software: special page */
   5 #define _PAGE_HPTE_SUB  0x0ffff000 /* combo only: sub pages HPTE bits */
   6 #define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
   7 #define _PAGE_COMBO     0x10000000 /* this is a combo 4k page */
   8 #define _PAGE_4K_PFN    0x20000000 /* PFN is for a single 4k page */
   9
  10 /* For 64K page, we don't have a separate _PAGE_HASHPTE bit. Instead,
  11  * we set that to be the whole sub-bits mask. The C code will only
  12  * test this, so a multi-bit mask will work. For combo pages, this
  13  * is equivalent as effectively, the old _PAGE_HASHPTE was an OR of
  14  * all the sub bits. For real 64k pages, we now have the assembly set
  15  * _PAGE_HPTE_SUB0 in addition to setting the HIDX bits which overlap
  16  * that mask. This is fine as long as the HIDX bits are never set on
  17  * a PTE that isn't hashed, which is the case today.
  18  *
  19  * A little nit is for the huge page C code, which does the hashing
  20  * in C, we need to provide which bit to use.
  21  */
  22 #define _PAGE_HASHPTE   _PAGE_HPTE_SUB
  23
  24 /* Note the full page bits must be in the same location as for normal
  25  * 4k pages as the same assembly will be used to insert 64K pages
  26  * whether the kernel has CONFIG_PPC_64K_PAGES or not
  27  */
  28 #define _PAGE_F_SECOND  0x00008000 /* full page: hidx bits */
  29 #define _PAGE_F_GIX     0x00007000 /* full page: hidx bits */
  30
  31 /* PTE flags to conserve for HPTE identification */
  32 #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO)
  33
  34 /* Shift to put page number into pte.
  35  *
  36  * That gives us a max RPN of 34 bits, which means a max of 50 bits
  37  * of addressable physical space, or 46 bits for the special 4k PFNs.
  38  */
  39 #define PTE_RPN_SHIFT   (30)
  40
  41 #ifndef __ASSEMBLY__
  42
  43 /*
  44  * With 64K pages on hash table, we have a special PTE format that
  45  * uses a second "half" of the page table to encode sub-page information
  46  * in order to deal with 64K made of 4K HW pages. Thus we override the
  47  * generic accessors and iterators here
  48  */
  49 #define __real_pte __real_pte
  50 static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep)
  51 {
  52         real_pte_t rpte;
  53
  54         rpte.pte = pte;
  55         rpte.hidx = 0;
  56         if (pte_val(pte) & _PAGE_COMBO) {
  57                 /*
  58                  * Make sure we order the hidx load against the _PAGE_COMBO
  59                  * check. The store side ordering is done in __hash_page_4K
  60                  */
  61                 smp_rmb();
  62                 rpte.hidx = pte_val(*((ptep) + PTRS_PER_PTE));
  63         }
  64         return rpte;
  65 }
  66
  67 static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
  68 {
  69         if ((pte_val(rpte.pte) & _PAGE_COMBO))
  70                 return (rpte.hidx >> (index<<2)) & 0xf;
  71         return (pte_val(rpte.pte) >> 12) & 0xf;
  72 }
  73
  74 #define __rpte_to_pte(r)        ((r).pte)
  75 #define __rpte_sub_valid(rpte, index) \
  76         (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
  77
  78 /* Trick: we set __end to va + 64k, which happens works for
  79  * a 16M page as well as we want only one iteration
  80  */
  81 #define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift)     \
  82         do {                                                            \
  83                 unsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT));  \
  84                 unsigned __split = (psize == MMU_PAGE_4K ||             \
  85                                     psize == MMU_PAGE_64K_AP);          \
  86                 shift = mmu_psize_defs[psize].shift;                    \
  87                 for (index = 0; vpn < __end; index++,                   \
  88                              vpn += (1L << (shift - VPN_SHIFT))) {      \
  89                         if (!__split || __rpte_sub_valid(rpte, index))  \
  90                                 do {
  91
  92 #define pte_iterate_hashed_end() } while(0); } } while(0)
  93
  94 #define pte_pagesize_index(mm, addr, pte)       \
  95         (((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
  96
  97 #define remap_4k_pfn(vma, addr, pfn, prot)                              \
  98         (WARN_ON(((pfn) >= (1UL << (64 - PTE_RPN_SHIFT)))) ? -EINVAL :  \
  99                 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,        \
 100                         __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN)))
 101
 102 #endif  /* __ASSEMBLY__ */