?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / arch / powerpc / kvm / booke.c
blobfd5875179e5c0e6738a1e7867a75f05cbe1fa0c8
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
16 * Copyright 2010-2011 Freescale Semiconductor, Inc.
17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
20 * Scott Wood <scottwood@freescale.com>
21 * Varun Sethi <varun.sethi@freescale.com>
22 */
23
24 #include <linux/errno.h>
25 #include <linux/err.h>
26 #include <linux/kvm_host.h>
27 #include <linux/gfp.h>
28 #include <linux/module.h>
29 #include <linux/vmalloc.h>
30 #include <linux/fs.h>
31
32 #include <asm/cputable.h>
33 #include <asm/uaccess.h>
34 #include <asm/kvm_ppc.h>
35 #include <asm/cacheflush.h>
36 #include <asm/dbell.h>
37 #include <asm/hw_irq.h>
38 #include <asm/irq.h>
39 #include <asm/time.h>
40
41 #include "timing.h"
42 #include "booke.h"
43
44 #define CREATE_TRACE_POINTS
45 #include "trace_booke.h"
46
47 unsigned long kvmppc_booke_handlers;
48
49 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
50 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
51
52 struct kvm_stats_debugfs_item debugfs_entries[] = {
53 { "mmio", VCPU_STAT(mmio_exits) },
54 { "sig", VCPU_STAT(signal_exits) },
55 { "itlb_r", VCPU_STAT(itlb_real_miss_exits) },
56 { "itlb_v", VCPU_STAT(itlb_virt_miss_exits) },
57 { "dtlb_r", VCPU_STAT(dtlb_real_miss_exits) },
58 { "dtlb_v", VCPU_STAT(dtlb_virt_miss_exits) },
59 { "sysc", VCPU_STAT(syscall_exits) },
60 { "isi", VCPU_STAT(isi_exits) },
61 { "dsi", VCPU_STAT(dsi_exits) },
62 { "inst_emu", VCPU_STAT(emulated_inst_exits) },
63 { "dec", VCPU_STAT(dec_exits) },
64 { "ext_intr", VCPU_STAT(ext_intr_exits) },
65 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
66 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
67 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
68 { "doorbell", VCPU_STAT(dbell_exits) },
69 { "guest doorbell", VCPU_STAT(gdbell_exits) },
70 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
71 { NULL }
72 };
73
74 /* TODO: use vcpu_printf() */
75 void kvmppc_dump_vcpu(struct kvm_vcpu *vcpu)
76 {
77 int i;
78
79 printk("pc: %08lx msr: %08llx\n", vcpu->arch.pc, vcpu->arch.shared->msr);
80 printk("lr: %08lx ctr: %08lx\n", vcpu->arch.lr, vcpu->arch.ctr);
81 printk("srr0: %08llx srr1: %08llx\n", vcpu->arch.shared->srr0,
82 vcpu->arch.shared->srr1);
83
84 printk("exceptions: %08lx\n", vcpu->arch.pending_exceptions);
85
86 for (i = 0; i < 32; i += 4) {
87 printk("gpr%02d: %08lx %08lx %08lx %08lx\n", i,
88 kvmppc_get_gpr(vcpu, i),
89 kvmppc_get_gpr(vcpu, i+1),
90 kvmppc_get_gpr(vcpu, i+2),
91 kvmppc_get_gpr(vcpu, i+3));
92 }
93 }
94
95 #ifdef CONFIG_SPE
96 void kvmppc_vcpu_disable_spe(struct kvm_vcpu *vcpu)
97 {
98 preempt_disable();
99 enable_kernel_spe();
100 kvmppc_save_guest_spe(vcpu);
101 vcpu->arch.shadow_msr &= ~MSR_SPE;
102 preempt_enable();
103 }
104
105 static void kvmppc_vcpu_enable_spe(struct kvm_vcpu *vcpu)
106 {
107 preempt_disable();
108 enable_kernel_spe();
109 kvmppc_load_guest_spe(vcpu);
110 vcpu->arch.shadow_msr |= MSR_SPE;
111 preempt_enable();
112 }
113
114 static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
115 {
116 if (vcpu->arch.shared->msr & MSR_SPE) {
117 if (!(vcpu->arch.shadow_msr & MSR_SPE))
118 kvmppc_vcpu_enable_spe(vcpu);
119 } else if (vcpu->arch.shadow_msr & MSR_SPE) {
120 kvmppc_vcpu_disable_spe(vcpu);
121 }
122 }
123 #else
124 static void kvmppc_vcpu_sync_spe(struct kvm_vcpu *vcpu)
125 {
126 }
127 #endif
128
129 /*
130 * Load up guest vcpu FP state if it's needed.
131 * It also set the MSR_FP in thread so that host know
132 * we're holding FPU, and then host can help to save
133 * guest vcpu FP state if other threads require to use FPU.
134 * This simulates an FP unavailable fault.
135 *
136 * It requires to be called with preemption disabled.
137 */
138 static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu)
139 {
140 #ifdef CONFIG_PPC_FPU
141 if (!(current->thread.regs->msr & MSR_FP)) {
142 enable_kernel_fp();
143 load_fp_state(&vcpu->arch.fp);
144 current->thread.fp_save_area = &vcpu->arch.fp;
145 current->thread.regs->msr |= MSR_FP;
146 }
147 #endif
148 }
149
150 /*
151 * Save guest vcpu FP state into thread.
152 * It requires to be called with preemption disabled.
153 */
154 static inline void kvmppc_save_guest_fp(struct kvm_vcpu *vcpu)
155 {
156 #ifdef CONFIG_PPC_FPU
157 if (current->thread.regs->msr & MSR_FP)
158 giveup_fpu(current);
159 current->thread.fp_save_area = NULL;
160 #endif
161 }
162
163 static void kvmppc_vcpu_sync_fpu(struct kvm_vcpu *vcpu)
164 {
165 #if defined(CONFIG_PPC_FPU) && !defined(CONFIG_KVM_BOOKE_HV)
166 /* We always treat the FP bit as enabled from the host
167 perspective, so only need to adjust the shadow MSR */
168 vcpu->arch.shadow_msr &= ~MSR_FP;
169 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_FP;
170 #endif
171 }
172
173 /*
174 * Simulate AltiVec unavailable fault to load guest state
175 * from thread to AltiVec unit.
176 * It requires to be called with preemption disabled.
177 */
178 static inline void kvmppc_load_guest_altivec(struct kvm_vcpu *vcpu)
179 {
180 #ifdef CONFIG_ALTIVEC
181 if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
182 if (!(current->thread.regs->msr & MSR_VEC)) {
183 enable_kernel_altivec();
184 load_vr_state(&vcpu->arch.vr);
185 current->thread.vr_save_area = &vcpu->arch.vr;
186 current->thread.regs->msr |= MSR_VEC;
187 }
188 }
189 #endif
190 }
191
192 /*
193 * Save guest vcpu AltiVec state into thread.
194 * It requires to be called with preemption disabled.
195 */
196 static inline void kvmppc_save_guest_altivec(struct kvm_vcpu *vcpu)
197 {
198 #ifdef CONFIG_ALTIVEC
199 if (cpu_has_feature(CPU_FTR_ALTIVEC)) {
200 if (current->thread.regs->msr & MSR_VEC)
201 giveup_altivec(current);
202 current->thread.vr_save_area = NULL;
203 }
204 #endif
205 }
206
207 static void kvmppc_vcpu_sync_debug(struct kvm_vcpu *vcpu)
208 {
209 /* Synchronize guest's desire to get debug interrupts into shadow MSR */
210 #ifndef CONFIG_KVM_BOOKE_HV
211 vcpu->arch.shadow_msr &= ~MSR_DE;
212 vcpu->arch.shadow_msr |= vcpu->arch.shared->msr & MSR_DE;
213 #endif
214
215 /* Force enable debug interrupts when user space wants to debug */
216 if (vcpu->guest_debug) {
217 #ifdef CONFIG_KVM_BOOKE_HV
218 /*
219 * Since there is no shadow MSR, sync MSR_DE into the guest
220 * visible MSR.
221 */
222 vcpu->arch.shared->msr |= MSR_DE;
223 #else
224 vcpu->arch.shadow_msr |= MSR_DE;
225 vcpu->arch.shared->msr &= ~MSR_DE;
226 #endif
227 }
228 }
229
230 /*
231 * Helper function for "full" MSR writes. No need to call this if only
232 * EE/CE/ME/DE/RI are changing.
233 */
234 void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 new_msr)
235 {
236 u32 old_msr = vcpu->arch.shared->msr;
237
238 #ifdef CONFIG_KVM_BOOKE_HV
239 new_msr |= MSR_GS;
240 #endif
241
242 vcpu->arch.shared->msr = new_msr;
243
244 kvmppc_mmu_msr_notify(vcpu, old_msr);
245 kvmppc_vcpu_sync_spe(vcpu);
246 kvmppc_vcpu_sync_fpu(vcpu);
247 kvmppc_vcpu_sync_debug(vcpu);
248 }
249
250 static void kvmppc_booke_queue_irqprio(struct kvm_vcpu *vcpu,
251 unsigned int priority)
252 {
253 trace_kvm_booke_queue_irqprio(vcpu, priority);
254 set_bit(priority, &vcpu->arch.pending_exceptions);
255 }
256
257 void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu,
258 ulong dear_flags, ulong esr_flags)
259 {
260 vcpu->arch.queued_dear = dear_flags;
261 vcpu->arch.queued_esr = esr_flags;
262 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS);
263 }
264
265 void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu,
266 ulong dear_flags, ulong esr_flags)
267 {
268 vcpu->arch.queued_dear = dear_flags;
269 vcpu->arch.queued_esr = esr_flags;
270 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE);
271 }
272
273 void kvmppc_core_queue_itlb_miss(struct kvm_vcpu *vcpu)
274 {
275 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS);
276 }
277
278 void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, ulong esr_flags)
279 {
280 vcpu->arch.queued_esr = esr_flags;
281 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_INST_STORAGE);
282 }
283
284 static void kvmppc_core_queue_alignment(struct kvm_vcpu *vcpu, ulong dear_flags,
285 ulong esr_flags)
286 {
287 vcpu->arch.queued_dear = dear_flags;
288 vcpu->arch.queued_esr = esr_flags;
289 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALIGNMENT);
290 }
291
292 void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags)
293 {
294 vcpu->arch.queued_esr = esr_flags;
295 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM);
296 }
297
298 void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
299 {
300 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER);
301 }
302
303 int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu)
304 {
305 return test_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
306 }
307
308 void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu)
309 {
310 clear_bit(BOOKE_IRQPRIO_DECREMENTER, &vcpu->arch.pending_exceptions);
311 }
312
313 void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
314 struct kvm_interrupt *irq)
315 {
316 unsigned int prio = BOOKE_IRQPRIO_EXTERNAL;
317
318 if (irq->irq == KVM_INTERRUPT_SET_LEVEL)
319 prio = BOOKE_IRQPRIO_EXTERNAL_LEVEL;
320
321 kvmppc_booke_queue_irqprio(vcpu, prio);
322 }
323
324 void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu)
325 {
326 clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions);
327 clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
328 }
329
330 static void kvmppc_core_queue_watchdog(struct kvm_vcpu *vcpu)
331 {
332 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_WATCHDOG);
333 }
334
335 static void kvmppc_core_dequeue_watchdog(struct kvm_vcpu *vcpu)
336 {
337 clear_bit(BOOKE_IRQPRIO_WATCHDOG, &vcpu->arch.pending_exceptions);
338 }
339
340 void kvmppc_core_queue_debug(struct kvm_vcpu *vcpu)
341 {
342 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DEBUG);
343 }
344
345 void kvmppc_core_dequeue_debug(struct kvm_vcpu *vcpu)
346 {
347 clear_bit(BOOKE_IRQPRIO_DEBUG, &vcpu->arch.pending_exceptions);
348 }
349
350 static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
351 {
352 kvmppc_set_srr0(vcpu, srr0);
353 kvmppc_set_srr1(vcpu, srr1);
354 }
355
356 static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
357 {
358 vcpu->arch.csrr0 = srr0;
359 vcpu->arch.csrr1 = srr1;
360 }
361
362 static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
363 {
364 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) {
365 vcpu->arch.dsrr0 = srr0;
366 vcpu->arch.dsrr1 = srr1;
367 } else {
368 set_guest_csrr(vcpu, srr0, srr1);
369 }
370 }
371
372 static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long srr0, u32 srr1)
373 {
374 vcpu->arch.mcsrr0 = srr0;
375 vcpu->arch.mcsrr1 = srr1;
376 }
377
378 /* Deliver the interrupt of the corresponding priority, if possible. */
379 static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
380 unsigned int priority)
381 {
382 int allowed = 0;
383 ulong msr_mask = 0;
384 bool update_esr = false, update_dear = false, update_epr = false;
385 ulong crit_raw = vcpu->arch.shared->critical;
386 ulong crit_r1 = kvmppc_get_gpr(vcpu, 1);
387 bool crit;
388 bool keep_irq = false;
389 enum int_class int_class;
390 ulong new_msr = vcpu->arch.shared->msr;
391
392 /* Truncate crit indicators in 32 bit mode */
393 if (!(vcpu->arch.shared->msr & MSR_SF)) {
394 crit_raw &= 0xffffffff;
395 crit_r1 &= 0xffffffff;
396 }
397
398 /* Critical section when crit == r1 */
399 crit = (crit_raw == crit_r1);
400 /* ... and we're in supervisor mode */
401 crit = crit && !(vcpu->arch.shared->msr & MSR_PR);
402
403 if (priority == BOOKE_IRQPRIO_EXTERNAL_LEVEL) {
404 priority = BOOKE_IRQPRIO_EXTERNAL;
405 keep_irq = true;
406 }
407
408 if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags)
409 update_epr = true;
410
411 switch (priority) {
412 case BOOKE_IRQPRIO_DTLB_MISS:
413 case BOOKE_IRQPRIO_DATA_STORAGE:
414 case BOOKE_IRQPRIO_ALIGNMENT:
415 update_dear = true;
416 /* fall through */
417 case BOOKE_IRQPRIO_INST_STORAGE:
418 case BOOKE_IRQPRIO_PROGRAM:
419 update_esr = true;
420 /* fall through */
421 case BOOKE_IRQPRIO_ITLB_MISS:
422 case BOOKE_IRQPRIO_SYSCALL:
423 case BOOKE_IRQPRIO_FP_UNAVAIL:
424 #ifdef CONFIG_SPE_POSSIBLE
425 case BOOKE_IRQPRIO_SPE_UNAVAIL:
426 case BOOKE_IRQPRIO_SPE_FP_DATA:
427 case BOOKE_IRQPRIO_SPE_FP_ROUND:
428 #endif
429 #ifdef CONFIG_ALTIVEC
430 case BOOKE_IRQPRIO_ALTIVEC_UNAVAIL:
431 case BOOKE_IRQPRIO_ALTIVEC_ASSIST:
432 #endif
433 case BOOKE_IRQPRIO_AP_UNAVAIL:
434 allowed = 1;
435 msr_mask = MSR_CE | MSR_ME | MSR_DE;
436 int_class = INT_CLASS_NONCRIT;
437 break;
438 case BOOKE_IRQPRIO_WATCHDOG:
439 case BOOKE_IRQPRIO_CRITICAL:
440 case BOOKE_IRQPRIO_DBELL_CRIT:
441 allowed = vcpu->arch.shared->msr & MSR_CE;
442 allowed = allowed && !crit;
443 msr_mask = MSR_ME;
444 int_class = INT_CLASS_CRIT;
445 break;
446 case BOOKE_IRQPRIO_MACHINE_CHECK:
447 allowed = vcpu->arch.shared->msr & MSR_ME;
448 allowed = allowed && !crit;
449 int_class = INT_CLASS_MC;
450 break;
451 case BOOKE_IRQPRIO_DECREMENTER:
452 case BOOKE_IRQPRIO_FIT:
453 keep_irq = true;
454 /* fall through */
455 case BOOKE_IRQPRIO_EXTERNAL:
456 case BOOKE_IRQPRIO_DBELL:
457 allowed = vcpu->arch.shared->msr & MSR_EE;
458 allowed = allowed && !crit;
459 msr_mask = MSR_CE | MSR_ME | MSR_DE;
460 int_class = INT_CLASS_NONCRIT;
461 break;
462 case BOOKE_IRQPRIO_DEBUG:
463 allowed = vcpu->arch.shared->msr & MSR_DE;
464 allowed = allowed && !crit;
465 msr_mask = MSR_ME;
466 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
467 int_class = INT_CLASS_DBG;
468 else
469 int_class = INT_CLASS_CRIT;
470
471 break;
472 }
473
474 if (allowed) {
475 switch (int_class) {
476 case INT_CLASS_NONCRIT:
477 set_guest_srr(vcpu, vcpu->arch.pc,
478 vcpu->arch.shared->msr);
479 break;
480 case INT_CLASS_CRIT:
481 set_guest_csrr(vcpu, vcpu->arch.pc,
482 vcpu->arch.shared->msr);
483 break;
484 case INT_CLASS_DBG:
485 set_guest_dsrr(vcpu, vcpu->arch.pc,
486 vcpu->arch.shared->msr);
487 break;
488 case INT_CLASS_MC:
489 set_guest_mcsrr(vcpu, vcpu->arch.pc,
490 vcpu->arch.shared->msr);
491 break;
492 }
493
494 vcpu->arch.pc = vcpu->arch.ivpr | vcpu->arch.ivor[priority];
495 if (update_esr == true)
496 kvmppc_set_esr(vcpu, vcpu->arch.queued_esr);
497 if (update_dear == true)
498 kvmppc_set_dar(vcpu, vcpu->arch.queued_dear);
499 if (update_epr == true) {
500 if (vcpu->arch.epr_flags & KVMPPC_EPR_USER)
501 kvm_make_request(KVM_REQ_EPR_EXIT, vcpu);
502 else if (vcpu->arch.epr_flags & KVMPPC_EPR_KERNEL) {
503 BUG_ON(vcpu->arch.irq_type != KVMPPC_IRQ_MPIC);
504 kvmppc_mpic_set_epr(vcpu);
505 }
506 }
507
508 new_msr &= msr_mask;
509 #if defined(CONFIG_64BIT)
510 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
511 new_msr |= MSR_CM;
512 #endif
513 kvmppc_set_msr(vcpu, new_msr);
514
515 if (!keep_irq)
516 clear_bit(priority, &vcpu->arch.pending_exceptions);
517 }
518
519 #ifdef CONFIG_KVM_BOOKE_HV
520 /*
521 * If an interrupt is pending but masked, raise a guest doorbell
522 * so that we are notified when the guest enables the relevant
523 * MSR bit.
524 */
525 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE)
526 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT);
527 if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE)
528 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT);
529 if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK)
530 kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC);
531 #endif
532
533 return allowed;
534 }
535
536 /*
537 * Return the number of jiffies until the next timeout. If the timeout is
538 * longer than the NEXT_TIMER_MAX_DELTA, then return NEXT_TIMER_MAX_DELTA
539 * because the larger value can break the timer APIs.
540 */
541 static unsigned long watchdog_next_timeout(struct kvm_vcpu *vcpu)
542 {
543 u64 tb, wdt_tb, wdt_ticks = 0;
544 u64 nr_jiffies = 0;
545 u32 period = TCR_GET_WP(vcpu->arch.tcr);
546
547 wdt_tb = 1ULL << (63 - period);
548 tb = get_tb();
549 /*
550 * The watchdog timeout will hapeen when TB bit corresponding
551 * to watchdog will toggle from 0 to 1.
552 */
553 if (tb & wdt_tb)
554 wdt_ticks = wdt_tb;
555
556 wdt_ticks += wdt_tb - (tb & (wdt_tb - 1));
557
558 /* Convert timebase ticks to jiffies */
559 nr_jiffies = wdt_ticks;
560
561 if (do_div(nr_jiffies, tb_ticks_per_jiffy))
562 nr_jiffies++;
563
564 return min_t(unsigned long long, nr_jiffies, NEXT_TIMER_MAX_DELTA);
565 }
566
567 static void arm_next_watchdog(struct kvm_vcpu *vcpu)
568 {
569 unsigned long nr_jiffies;
570 unsigned long flags;
571
572 /*
573 * If TSR_ENW and TSR_WIS are not set then no need to exit to
574 * userspace, so clear the KVM_REQ_WATCHDOG request.
575 */
576 if ((vcpu->arch.tsr & (TSR_ENW | TSR_WIS)) != (TSR_ENW | TSR_WIS))
577 clear_bit(KVM_REQ_WATCHDOG, &vcpu->requests);
578
579 spin_lock_irqsave(&vcpu->arch.wdt_lock, flags);
580 nr_jiffies = watchdog_next_timeout(vcpu);
581 /*
582 * If the number of jiffies of watchdog timer >= NEXT_TIMER_MAX_DELTA
583 * then do not run the watchdog timer as this can break timer APIs.
584 */
585 if (nr_jiffies < NEXT_TIMER_MAX_DELTA)
586 mod_timer(&vcpu->arch.wdt_timer, jiffies + nr_jiffies);
587 else
588 del_timer(&vcpu->arch.wdt_timer);
589 spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags);
590 }
591
592 void kvmppc_watchdog_func(unsigned long data)
593 {
594 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
595 u32 tsr, new_tsr;
596 int final;
597
598 do {
599 new_tsr = tsr = vcpu->arch.tsr;
600 final = 0;
601
602 /* Time out event */
603 if (tsr & TSR_ENW) {
604 if (tsr & TSR_WIS)
605 final = 1;
606 else
607 new_tsr = tsr | TSR_WIS;
608 } else {
609 new_tsr = tsr | TSR_ENW;
610 }
611 } while (cmpxchg(&vcpu->arch.tsr, tsr, new_tsr) != tsr);
612
613 if (new_tsr & TSR_WIS) {
614 smp_wmb();
615 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
616 kvm_vcpu_kick(vcpu);
617 }
618
619 /*
620 * If this is final watchdog expiry and some action is required
621 * then exit to userspace.
622 */
623 if (final && (vcpu->arch.tcr & TCR_WRC_MASK) &&
624 vcpu->arch.watchdog_enabled) {
625 smp_wmb();
626 kvm_make_request(KVM_REQ_WATCHDOG, vcpu);
627 kvm_vcpu_kick(vcpu);
628 }
629
630 /*
631 * Stop running the watchdog timer after final expiration to
632 * prevent the host from being flooded with timers if the
633 * guest sets a short period.
634 * Timers will resume when TSR/TCR is updated next time.
635 */
636 if (!final)
637 arm_next_watchdog(vcpu);
638 }
639
640 static void update_timer_ints(struct kvm_vcpu *vcpu)
641 {
642 if ((vcpu->arch.tcr & TCR_DIE) && (vcpu->arch.tsr & TSR_DIS))
643 kvmppc_core_queue_dec(vcpu);
644 else
645 kvmppc_core_dequeue_dec(vcpu);
646
647 if ((vcpu->arch.tcr & TCR_WIE) && (vcpu->arch.tsr & TSR_WIS))
648 kvmppc_core_queue_watchdog(vcpu);
649 else
650 kvmppc_core_dequeue_watchdog(vcpu);
651 }
652
653 static void kvmppc_core_check_exceptions(struct kvm_vcpu *vcpu)
654 {
655 unsigned long *pending = &vcpu->arch.pending_exceptions;
656 unsigned int priority;
657
658 priority = __ffs(*pending);
659 while (priority < BOOKE_IRQPRIO_MAX) {
660 if (kvmppc_booke_irqprio_deliver(vcpu, priority))
661 break;
662
663 priority = find_next_bit(pending,
664 BITS_PER_BYTE * sizeof(*pending),
665 priority + 1);
666 }
667
668 /* Tell the guest about our interrupt status */
669 vcpu->arch.shared->int_pending = !!*pending;
670 }
671
672 /* Check pending exceptions and deliver one, if possible. */
673 int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu)
674 {
675 int r = 0;
676 WARN_ON_ONCE(!irqs_disabled());
677
678 kvmppc_core_check_exceptions(vcpu);
679
680 if (vcpu->requests) {
681 /* Exception delivery raised request; start over */
682 return 1;
683 }
684
685 if (vcpu->arch.shared->msr & MSR_WE) {
686 local_irq_enable();
687 kvm_vcpu_block(vcpu);
688 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
689 hard_irq_disable();
690
691 kvmppc_set_exit_type(vcpu, EMULATED_MTMSRWE_EXITS);
692 r = 1;
693 };
694
695 return r;
696 }
697
698 int kvmppc_core_check_requests(struct kvm_vcpu *vcpu)
699 {
700 int r = 1; /* Indicate we want to get back into the guest */
701
702 if (kvm_check_request(KVM_REQ_PENDING_TIMER, vcpu))
703 update_timer_ints(vcpu);
704 #if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC)
705 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
706 kvmppc_core_flush_tlb(vcpu);
707 #endif
708
709 if (kvm_check_request(KVM_REQ_WATCHDOG, vcpu)) {
710 vcpu->run->exit_reason = KVM_EXIT_WATCHDOG;
711 r = 0;
712 }
713
714 if (kvm_check_request(KVM_REQ_EPR_EXIT, vcpu)) {
715 vcpu->run->epr.epr = 0;
716 vcpu->arch.epr_needed = true;
717 vcpu->run->exit_reason = KVM_EXIT_EPR;
718 r = 0;
719 }
720
721 return r;
722 }
723
724 int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
725 {
726 int ret, s;
727 struct debug_reg debug;
728
729 if (!vcpu->arch.sane) {
730 kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
731 return -EINVAL;
732 }
733
734 s = kvmppc_prepare_to_enter(vcpu);
735 if (s <= 0) {
736 ret = s;
737 goto out;
738 }
739 /* interrupts now hard-disabled */
740
741 #ifdef CONFIG_PPC_FPU
742 /* Save userspace FPU state in stack */
743 enable_kernel_fp();
744
745 /*
746 * Since we can't trap on MSR_FP in GS-mode, we consider the guest
747 * as always using the FPU.
748 */
749 kvmppc_load_guest_fp(vcpu);
750 #endif
751
752 #ifdef CONFIG_ALTIVEC
753 /* Save userspace AltiVec state in stack */
754 if (cpu_has_feature(CPU_FTR_ALTIVEC))
755 enable_kernel_altivec();
756 /*
757 * Since we can't trap on MSR_VEC in GS-mode, we consider the guest
758 * as always using the AltiVec.
759 */
760 kvmppc_load_guest_altivec(vcpu);
761 #endif
762
763 /* Switch to guest debug context */
764 debug = vcpu->arch.dbg_reg;
765 switch_booke_debug_regs(&debug);
766 debug = current->thread.debug;
767 current->thread.debug = vcpu->arch.dbg_reg;
768
769 vcpu->arch.pgdir = current->mm->pgd;
770 kvmppc_fix_ee_before_entry();
771
772 ret = __kvmppc_vcpu_run(kvm_run, vcpu);
773
774 /* No need for kvm_guest_exit. It's done in handle_exit.
775 We also get here with interrupts enabled. */
776
777 /* Switch back to user space debug context */
778 switch_booke_debug_regs(&debug);
779 current->thread.debug = debug;
780
781 #ifdef CONFIG_PPC_FPU
782 kvmppc_save_guest_fp(vcpu);
783 #endif
784
785 #ifdef CONFIG_ALTIVEC
786 kvmppc_save_guest_altivec(vcpu);
787 #endif
788
789 out:
790 vcpu->mode = OUTSIDE_GUEST_MODE;
791 return ret;
792 }
793
794 static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
795 {
796 enum emulation_result er;
797
798 er = kvmppc_emulate_instruction(run, vcpu);
799 switch (er) {
800 case EMULATE_DONE:
801 /* don't overwrite subtypes, just account kvm_stats */
802 kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS);
803 /* Future optimization: only reload non-volatiles if
804 * they were actually modified by emulation. */
805 return RESUME_GUEST_NV;
806
807 case EMULATE_AGAIN:
808 return RESUME_GUEST;
809
810 case EMULATE_FAIL:
811 printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
812 __func__, vcpu->arch.pc, vcpu->arch.last_inst);
813 /* For debugging, encode the failing instruction and
814 * report it to userspace. */
815 run->hw.hardware_exit_reason = ~0ULL << 32;
816 run->hw.hardware_exit_reason |= vcpu->arch.last_inst;
817 kvmppc_core_queue_program(vcpu, ESR_PIL);
818 return RESUME_HOST;
819
820 case EMULATE_EXIT_USER:
821 return RESUME_HOST;
822
823 default:
824 BUG();
825 }
826 }
827
828 static int kvmppc_handle_debug(struct kvm_run *run, struct kvm_vcpu *vcpu)
829 {
830 struct debug_reg *dbg_reg = &(vcpu->arch.dbg_reg);
831 u32 dbsr = vcpu->arch.dbsr;
832
833 if (vcpu->guest_debug == 0) {
834 /*
835 * Debug resources belong to Guest.
836 * Imprecise debug event is not injected
837 */
838 if (dbsr & DBSR_IDE) {
839 dbsr &= ~DBSR_IDE;
840 if (!dbsr)
841 return RESUME_GUEST;
842 }
843
844 if (dbsr && (vcpu->arch.shared->msr & MSR_DE) &&
845 (vcpu->arch.dbg_reg.dbcr0 & DBCR0_IDM))
846 kvmppc_core_queue_debug(vcpu);
847
848 /* Inject a program interrupt if trap debug is not allowed */
849 if ((dbsr & DBSR_TIE) && !(vcpu->arch.shared->msr & MSR_DE))
850 kvmppc_core_queue_program(vcpu, ESR_PTR);
851
852 return RESUME_GUEST;
853 }
854
855 /*
856 * Debug resource owned by userspace.
857 * Clear guest dbsr (vcpu->arch.dbsr)
858 */
859 vcpu->arch.dbsr = 0;
860 run->debug.arch.status = 0;
861 run->debug.arch.address = vcpu->arch.pc;
862
863 if (dbsr & (DBSR_IAC1 | DBSR_IAC2 | DBSR_IAC3 | DBSR_IAC4)) {
864 run->debug.arch.status |= KVMPPC_DEBUG_BREAKPOINT;
865 } else {
866 if (dbsr & (DBSR_DAC1W | DBSR_DAC2W))
867 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_WRITE;
868 else if (dbsr & (DBSR_DAC1R | DBSR_DAC2R))
869 run->debug.arch.status |= KVMPPC_DEBUG_WATCH_READ;
870 if (dbsr & (DBSR_DAC1R | DBSR_DAC1W))
871 run->debug.arch.address = dbg_reg->dac1;
872 else if (dbsr & (DBSR_DAC2R | DBSR_DAC2W))
873 run->debug.arch.address = dbg_reg->dac2;
874 }
875
876 return RESUME_HOST;
877 }
878
879 static void kvmppc_fill_pt_regs(struct pt_regs *regs)
880 {
881 ulong r1, ip, msr, lr;
882
883 asm("mr %0, 1" : "=r"(r1));
884 asm("mflr %0" : "=r"(lr));
885 asm("mfmsr %0" : "=r"(msr));
886 asm("bl 1f; 1: mflr %0" : "=r"(ip));
887
888 memset(regs, 0, sizeof(*regs));
889 regs->gpr[1] = r1;
890 regs->nip = ip;
891 regs->msr = msr;
892 regs->link = lr;
893 }
894
895 /*
896 * For interrupts needed to be handled by host interrupt handlers,
897 * corresponding host handler are called from here in similar way
898 * (but not exact) as they are called from low level handler
899 * (such as from arch/powerpc/kernel/head_fsl_booke.S).
900 */
901 static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu,
902 unsigned int exit_nr)
903 {
904 struct pt_regs regs;
905
906 switch (exit_nr) {
907 case BOOKE_INTERRUPT_EXTERNAL:
908 kvmppc_fill_pt_regs(&regs);
909 do_IRQ(&regs);
910 break;
911 case BOOKE_INTERRUPT_DECREMENTER:
912 kvmppc_fill_pt_regs(&regs);
913 timer_interrupt(&regs);
914 break;
915 #if defined(CONFIG_PPC_DOORBELL)
916 case BOOKE_INTERRUPT_DOORBELL:
917 kvmppc_fill_pt_regs(&regs);
918 doorbell_exception(&regs);
919 break;
920 #endif
921 case BOOKE_INTERRUPT_MACHINE_CHECK:
922 /* FIXME */
923 break;
924 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
925 kvmppc_fill_pt_regs(&regs);
926 performance_monitor_exception(&regs);
927 break;
928 case BOOKE_INTERRUPT_WATCHDOG:
929 kvmppc_fill_pt_regs(&regs);
930 #ifdef CONFIG_BOOKE_WDT
931 WatchdogException(&regs);
932 #else
933 unknown_exception(&regs);
934 #endif
935 break;
936 case BOOKE_INTERRUPT_CRITICAL:
937 kvmppc_fill_pt_regs(&regs);
938 unknown_exception(&regs);
939 break;
940 case BOOKE_INTERRUPT_DEBUG:
941 /* Save DBSR before preemption is enabled */
942 vcpu->arch.dbsr = mfspr(SPRN_DBSR);
943 kvmppc_clear_dbsr();
944 break;
945 }
946 }
947
948 static int kvmppc_resume_inst_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
949 enum emulation_result emulated, u32 last_inst)
950 {
951 switch (emulated) {
952 case EMULATE_AGAIN:
953 return RESUME_GUEST;
954
955 case EMULATE_FAIL:
956 pr_debug("%s: load instruction from guest address %lx failed\n",
957 __func__, vcpu->arch.pc);
958 /* For debugging, encode the failing instruction and
959 * report it to userspace. */
960 run->hw.hardware_exit_reason = ~0ULL << 32;
961 run->hw.hardware_exit_reason |= last_inst;
962 kvmppc_core_queue_program(vcpu, ESR_PIL);
963 return RESUME_HOST;
964
965 default:
966 BUG();
967 }
968 }
969
970 /**
971 * kvmppc_handle_exit
972 *
973 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
974 */
975 int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
976 unsigned int exit_nr)
977 {
978 int r = RESUME_HOST;
979 int s;
980 int idx;
981 u32 last_inst = KVM_INST_FETCH_FAILED;
982 enum emulation_result emulated = EMULATE_DONE;
983
984 /* update before a new last_exit_type is rewritten */
985 kvmppc_update_timing_stats(vcpu);
986
987 /* restart interrupts if they were meant for the host */
988 kvmppc_restart_interrupt(vcpu, exit_nr);
989
990 /*
991 * get last instruction before beeing preempted
992 * TODO: for e6500 check also BOOKE_INTERRUPT_LRAT_ERROR & ESR_DATA
993 */
994 switch (exit_nr) {
995 case BOOKE_INTERRUPT_DATA_STORAGE:
996 case BOOKE_INTERRUPT_DTLB_MISS:
997 case BOOKE_INTERRUPT_HV_PRIV:
998 emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
999 break;
1000 case BOOKE_INTERRUPT_PROGRAM:
1001 /* SW breakpoints arrive as illegal instructions on HV */
1002 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1003 emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
1004 break;
1005 default:
1006 break;
1007 }
1008
1009 trace_kvm_exit(exit_nr, vcpu);
1010 __kvm_guest_exit();
1011
1012 local_irq_enable();
1013
1014 run->exit_reason = KVM_EXIT_UNKNOWN;
1015 run->ready_for_interrupt_injection = 1;
1016
1017 if (emulated != EMULATE_DONE) {
1018 r = kvmppc_resume_inst_load(run, vcpu, emulated, last_inst);
1019 goto out;
1020 }
1021
1022 switch (exit_nr) {
1023 case BOOKE_INTERRUPT_MACHINE_CHECK:
1024 printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR));
1025 kvmppc_dump_vcpu(vcpu);
1026 /* For debugging, send invalid exit reason to user space */
1027 run->hw.hardware_exit_reason = ~1ULL << 32;
1028 run->hw.hardware_exit_reason |= mfspr(SPRN_MCSR);
1029 r = RESUME_HOST;
1030 break;
1031
1032 case BOOKE_INTERRUPT_EXTERNAL:
1033 kvmppc_account_exit(vcpu, EXT_INTR_EXITS);
1034 r = RESUME_GUEST;
1035 break;
1036
1037 case BOOKE_INTERRUPT_DECREMENTER:
1038 kvmppc_account_exit(vcpu, DEC_EXITS);
1039 r = RESUME_GUEST;
1040 break;
1041
1042 case BOOKE_INTERRUPT_WATCHDOG:
1043 r = RESUME_GUEST;
1044 break;
1045
1046 case BOOKE_INTERRUPT_DOORBELL:
1047 kvmppc_account_exit(vcpu, DBELL_EXITS);
1048 r = RESUME_GUEST;
1049 break;
1050
1051 case BOOKE_INTERRUPT_GUEST_DBELL_CRIT:
1052 kvmppc_account_exit(vcpu, GDBELL_EXITS);
1053
1054 /*
1055 * We are here because there is a pending guest interrupt
1056 * which could not be delivered as MSR_CE or MSR_ME was not
1057 * set. Once we break from here we will retry delivery.
1058 */
1059 r = RESUME_GUEST;
1060 break;
1061
1062 case BOOKE_INTERRUPT_GUEST_DBELL:
1063 kvmppc_account_exit(vcpu, GDBELL_EXITS);
1064
1065 /*
1066 * We are here because there is a pending guest interrupt
1067 * which could not be delivered as MSR_EE was not set. Once
1068 * we break from here we will retry delivery.
1069 */
1070 r = RESUME_GUEST;
1071 break;
1072
1073 case BOOKE_INTERRUPT_PERFORMANCE_MONITOR:
1074 r = RESUME_GUEST;
1075 break;
1076
1077 case BOOKE_INTERRUPT_HV_PRIV:
1078 r = emulation_exit(run, vcpu);
1079 break;
1080
1081 case BOOKE_INTERRUPT_PROGRAM:
1082 if ((vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) &&
1083 (last_inst == KVMPPC_INST_SW_BREAKPOINT)) {
1084 /*
1085 * We are here because of an SW breakpoint instr,
1086 * so lets return to host to handle.
1087 */
1088 r = kvmppc_handle_debug(run, vcpu);
1089 run->exit_reason = KVM_EXIT_DEBUG;
1090 kvmppc_account_exit(vcpu, DEBUG_EXITS);
1091 break;
1092 }
1093
1094 if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) {
1095 /*
1096 * Program traps generated by user-level software must
1097 * be handled by the guest kernel.
1098 *
1099 * In GS mode, hypervisor privileged instructions trap
1100 * on BOOKE_INTERRUPT_HV_PRIV, not here, so these are
1101 * actual program interrupts, handled by the guest.
1102 */
1103 kvmppc_core_queue_program(vcpu, vcpu->arch.fault_esr);
1104 r = RESUME_GUEST;
1105 kvmppc_account_exit(vcpu, USR_PR_INST);
1106 break;
1107 }
1108
1109 r = emulation_exit(run, vcpu);
1110 break;
1111
1112 case BOOKE_INTERRUPT_FP_UNAVAIL:
1113 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL);
1114 kvmppc_account_exit(vcpu, FP_UNAVAIL);
1115 r = RESUME_GUEST;
1116 break;
1117
1118 #ifdef CONFIG_SPE
1119 case BOOKE_INTERRUPT_SPE_UNAVAIL: {
1120 if (vcpu->arch.shared->msr & MSR_SPE)
1121 kvmppc_vcpu_enable_spe(vcpu);
1122 else
1123 kvmppc_booke_queue_irqprio(vcpu,
1124 BOOKE_IRQPRIO_SPE_UNAVAIL);
1125 r = RESUME_GUEST;
1126 break;
1127 }
1128
1129 case BOOKE_INTERRUPT_SPE_FP_DATA:
1130 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_DATA);
1131 r = RESUME_GUEST;
1132 break;
1133
1134 case BOOKE_INTERRUPT_SPE_FP_ROUND:
1135 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SPE_FP_ROUND);
1136 r = RESUME_GUEST;
1137 break;
1138 #elif defined(CONFIG_SPE_POSSIBLE)
1139 case BOOKE_INTERRUPT_SPE_UNAVAIL:
1140 /*
1141 * Guest wants SPE, but host kernel doesn't support it. Send
1142 * an "unimplemented operation" program check to the guest.
1143 */
1144 kvmppc_core_queue_program(vcpu, ESR_PUO | ESR_SPV);
1145 r = RESUME_GUEST;
1146 break;
1147
1148 /*
1149 * These really should never happen without CONFIG_SPE,
1150 * as we should never enable the real MSR[SPE] in the guest.
1151 */
1152 case BOOKE_INTERRUPT_SPE_FP_DATA:
1153 case BOOKE_INTERRUPT_SPE_FP_ROUND:
1154 printk(KERN_CRIT "%s: unexpected SPE interrupt %u at %08lx\n",
1155 __func__, exit_nr, vcpu->arch.pc);
1156 run->hw.hardware_exit_reason = exit_nr;
1157 r = RESUME_HOST;
1158 break;
1159 #endif /* CONFIG_SPE_POSSIBLE */
1160
1161 /*
1162 * On cores with Vector category, KVM is loaded only if CONFIG_ALTIVEC,
1163 * see kvmppc_core_check_processor_compat().
1164 */
1165 #ifdef CONFIG_ALTIVEC
1166 case BOOKE_INTERRUPT_ALTIVEC_UNAVAIL:
1167 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_UNAVAIL);
1168 r = RESUME_GUEST;
1169 break;
1170
1171 case BOOKE_INTERRUPT_ALTIVEC_ASSIST:
1172 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_ASSIST);
1173 r = RESUME_GUEST;
1174 break;
1175 #endif
1176
1177 case BOOKE_INTERRUPT_DATA_STORAGE:
1178 kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear,
1179 vcpu->arch.fault_esr);
1180 kvmppc_account_exit(vcpu, DSI_EXITS);
1181 r = RESUME_GUEST;
1182 break;
1183
1184 case BOOKE_INTERRUPT_INST_STORAGE:
1185 kvmppc_core_queue_inst_storage(vcpu, vcpu->arch.fault_esr);
1186 kvmppc_account_exit(vcpu, ISI_EXITS);
1187 r = RESUME_GUEST;
1188 break;
1189
1190 case BOOKE_INTERRUPT_ALIGNMENT:
1191 kvmppc_core_queue_alignment(vcpu, vcpu->arch.fault_dear,
1192 vcpu->arch.fault_esr);
1193 r = RESUME_GUEST;
1194 break;
1195
1196 #ifdef CONFIG_KVM_BOOKE_HV
1197 case BOOKE_INTERRUPT_HV_SYSCALL:
1198 if (!(vcpu->arch.shared->msr & MSR_PR)) {
1199 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1200 } else {
1201 /*
1202 * hcall from guest userspace -- send privileged
1203 * instruction program check.
1204 */
1205 kvmppc_core_queue_program(vcpu, ESR_PPR);
1206 }
1207
1208 r = RESUME_GUEST;
1209 break;
1210 #else
1211 case BOOKE_INTERRUPT_SYSCALL:
1212 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1213 (((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) {
1214 /* KVM PV hypercalls */
1215 kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
1216 r = RESUME_GUEST;
1217 } else {
1218 /* Guest syscalls */
1219 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_SYSCALL);
1220 }
1221 kvmppc_account_exit(vcpu, SYSCALL_EXITS);
1222 r = RESUME_GUEST;
1223 break;
1224 #endif
1225
1226 case BOOKE_INTERRUPT_DTLB_MISS: {
1227 unsigned long eaddr = vcpu->arch.fault_dear;
1228 int gtlb_index;
1229 gpa_t gpaddr;
1230 gfn_t gfn;
1231
1232 #ifdef CONFIG_KVM_E500V2
1233 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1234 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) {
1235 kvmppc_map_magic(vcpu);
1236 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
1237 r = RESUME_GUEST;
1238
1239 break;
1240 }
1241 #endif
1242
1243 /* Check the guest TLB. */
1244 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr);
1245 if (gtlb_index < 0) {
1246 /* The guest didn't have a mapping for it. */
1247 kvmppc_core_queue_dtlb_miss(vcpu,
1248 vcpu->arch.fault_dear,
1249 vcpu->arch.fault_esr);
1250 kvmppc_mmu_dtlb_miss(vcpu);
1251 kvmppc_account_exit(vcpu, DTLB_REAL_MISS_EXITS);
1252 r = RESUME_GUEST;
1253 break;
1254 }
1255
1256 idx = srcu_read_lock(&vcpu->kvm->srcu);
1257
1258 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1259 gfn = gpaddr >> PAGE_SHIFT;
1260
1261 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1262 /* The guest TLB had a mapping, but the shadow TLB
1263 * didn't, and it is RAM. This could be because:
1264 * a) the entry is mapping the host kernel, or
1265 * b) the guest used a large mapping which we're faking
1266 * Either way, we need to satisfy the fault without
1267 * invoking the guest. */
1268 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
1269 kvmppc_account_exit(vcpu, DTLB_VIRT_MISS_EXITS);
1270 r = RESUME_GUEST;
1271 } else {
1272 /* Guest has mapped and accessed a page which is not
1273 * actually RAM. */
1274 vcpu->arch.paddr_accessed = gpaddr;
1275 vcpu->arch.vaddr_accessed = eaddr;
1276 r = kvmppc_emulate_mmio(run, vcpu);
1277 kvmppc_account_exit(vcpu, MMIO_EXITS);
1278 }
1279
1280 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1281 break;
1282 }
1283
1284 case BOOKE_INTERRUPT_ITLB_MISS: {
1285 unsigned long eaddr = vcpu->arch.pc;
1286 gpa_t gpaddr;
1287 gfn_t gfn;
1288 int gtlb_index;
1289
1290 r = RESUME_GUEST;
1291
1292 /* Check the guest TLB. */
1293 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr);
1294 if (gtlb_index < 0) {
1295 /* The guest didn't have a mapping for it. */
1296 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ITLB_MISS);
1297 kvmppc_mmu_itlb_miss(vcpu);
1298 kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS);
1299 break;
1300 }
1301
1302 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
1303
1304 idx = srcu_read_lock(&vcpu->kvm->srcu);
1305
1306 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1307 gfn = gpaddr >> PAGE_SHIFT;
1308
1309 if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
1310 /* The guest TLB had a mapping, but the shadow TLB
1311 * didn't. This could be because:
1312 * a) the entry is mapping the host kernel, or
1313 * b) the guest used a large mapping which we're faking
1314 * Either way, we need to satisfy the fault without
1315 * invoking the guest. */
1316 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
1317 } else {
1318 /* Guest mapped and leaped at non-RAM! */
1319 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
1320 }
1321
1322 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1323 break;
1324 }
1325
1326 case BOOKE_INTERRUPT_DEBUG: {
1327 r = kvmppc_handle_debug(run, vcpu);
1328 if (r == RESUME_HOST)
1329 run->exit_reason = KVM_EXIT_DEBUG;
1330 kvmppc_account_exit(vcpu, DEBUG_EXITS);
1331 break;
1332 }
1333
1334 default:
1335 printk(KERN_EMERG "exit_nr %d\n", exit_nr);
1336 BUG();
1337 }
1338
1339 out:
1340 /*
1341 * To avoid clobbering exit_reason, only check for signals if we
1342 * aren't already exiting to userspace for some other reason.
1343 */
1344 if (!(r & RESUME_HOST)) {
1345 s = kvmppc_prepare_to_enter(vcpu);
1346 if (s <= 0)
1347 r = (s << 2) | RESUME_HOST | (r & RESUME_FLAG_NV);
1348 else {
1349 /* interrupts now hard-disabled */
1350 kvmppc_fix_ee_before_entry();
1351 kvmppc_load_guest_fp(vcpu);
1352 kvmppc_load_guest_altivec(vcpu);
1353 }
1354 }
1355
1356 return r;
1357 }
1358
1359 static void kvmppc_set_tsr(struct kvm_vcpu *vcpu, u32 new_tsr)
1360 {
1361 u32 old_tsr = vcpu->arch.tsr;
1362
1363 vcpu->arch.tsr = new_tsr;
1364
1365 if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS))
1366 arm_next_watchdog(vcpu);
1367
1368 update_timer_ints(vcpu);
1369 }
1370
1371 /* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */
1372 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1373 {
1374 int i;
1375 int r;
1376
1377 vcpu->arch.pc = 0;
1378 vcpu->arch.shared->pir = vcpu->vcpu_id;
1379 kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save LR slot */
1380 kvmppc_set_msr(vcpu, 0);
1381
1382 #ifndef CONFIG_KVM_BOOKE_HV
1383 vcpu->arch.shadow_msr = MSR_USER | MSR_IS | MSR_DS;
1384 vcpu->arch.shadow_pid = 1;
1385 vcpu->arch.shared->msr = 0;
1386 #endif
1387
1388 /* Eye-catching numbers so we know if the guest takes an interrupt
1389 * before it's programmed its own IVPR/IVORs. */
1390 vcpu->arch.ivpr = 0x55550000;
1391 for (i = 0; i < BOOKE_IRQPRIO_MAX; i++)
1392 vcpu->arch.ivor[i] = 0x7700 | i * 4;
1393
1394 kvmppc_init_timing_stats(vcpu);
1395
1396 r = kvmppc_core_vcpu_setup(vcpu);
1397 kvmppc_sanity_check(vcpu);
1398 return r;
1399 }
1400
1401 int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu)
1402 {
1403 /* setup watchdog timer once */
1404 spin_lock_init(&vcpu->arch.wdt_lock);
1405 setup_timer(&vcpu->arch.wdt_timer, kvmppc_watchdog_func,
1406 (unsigned long)vcpu);
1407
1408 /*
1409 * Clear DBSR.MRR to avoid guest debug interrupt as
1410 * this is of host interest
1411 */
1412 mtspr(SPRN_DBSR, DBSR_MRR);
1413 return 0;
1414 }
1415
1416 void kvmppc_subarch_vcpu_uninit(struct kvm_vcpu *vcpu)
1417 {
1418 del_timer_sync(&vcpu->arch.wdt_timer);
1419 }
1420
1421 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1422 {
1423 int i;
1424
1425 regs->pc = vcpu->arch.pc;
1426 regs->cr = kvmppc_get_cr(vcpu);
1427 regs->ctr = vcpu->arch.ctr;
1428 regs->lr = vcpu->arch.lr;
1429 regs->xer = kvmppc_get_xer(vcpu);
1430 regs->msr = vcpu->arch.shared->msr;
1431 regs->srr0 = kvmppc_get_srr0(vcpu);
1432 regs->srr1 = kvmppc_get_srr1(vcpu);
1433 regs->pid = vcpu->arch.pid;
1434 regs->sprg0 = kvmppc_get_sprg0(vcpu);
1435 regs->sprg1 = kvmppc_get_sprg1(vcpu);
1436 regs->sprg2 = kvmppc_get_sprg2(vcpu);
1437 regs->sprg3 = kvmppc_get_sprg3(vcpu);
1438 regs->sprg4 = kvmppc_get_sprg4(vcpu);
1439 regs->sprg5 = kvmppc_get_sprg5(vcpu);
1440 regs->sprg6 = kvmppc_get_sprg6(vcpu);
1441 regs->sprg7 = kvmppc_get_sprg7(vcpu);
1442
1443 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
1444 regs->gpr[i] = kvmppc_get_gpr(vcpu, i);
1445
1446 return 0;
1447 }
1448
1449 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1450 {
1451 int i;
1452
1453 vcpu->arch.pc = regs->pc;
1454 kvmppc_set_cr(vcpu, regs->cr);
1455 vcpu->arch.ctr = regs->ctr;
1456 vcpu->arch.lr = regs->lr;
1457 kvmppc_set_xer(vcpu, regs->xer);
1458 kvmppc_set_msr(vcpu, regs->msr);
1459 kvmppc_set_srr0(vcpu, regs->srr0);
1460 kvmppc_set_srr1(vcpu, regs->srr1);
1461 kvmppc_set_pid(vcpu, regs->pid);
1462 kvmppc_set_sprg0(vcpu, regs->sprg0);
1463 kvmppc_set_sprg1(vcpu, regs->sprg1);
1464 kvmppc_set_sprg2(vcpu, regs->sprg2);
1465 kvmppc_set_sprg3(vcpu, regs->sprg3);
1466 kvmppc_set_sprg4(vcpu, regs->sprg4);
1467 kvmppc_set_sprg5(vcpu, regs->sprg5);
1468 kvmppc_set_sprg6(vcpu, regs->sprg6);
1469 kvmppc_set_sprg7(vcpu, regs->sprg7);
1470
1471 for (i = 0; i < ARRAY_SIZE(regs->gpr); i++)
1472 kvmppc_set_gpr(vcpu, i, regs->gpr[i]);
1473
1474 return 0;
1475 }
1476
1477 static void get_sregs_base(struct kvm_vcpu *vcpu,
1478 struct kvm_sregs *sregs)
1479 {
1480 u64 tb = get_tb();
1481
1482 sregs->u.e.features |= KVM_SREGS_E_BASE;
1483
1484 sregs->u.e.csrr0 = vcpu->arch.csrr0;
1485 sregs->u.e.csrr1 = vcpu->arch.csrr1;
1486 sregs->u.e.mcsr = vcpu->arch.mcsr;
1487 sregs->u.e.esr = kvmppc_get_esr(vcpu);
1488 sregs->u.e.dear = kvmppc_get_dar(vcpu);
1489 sregs->u.e.tsr = vcpu->arch.tsr;
1490 sregs->u.e.tcr = vcpu->arch.tcr;
1491 sregs->u.e.dec = kvmppc_get_dec(vcpu, tb);
1492 sregs->u.e.tb = tb;
1493 sregs->u.e.vrsave = vcpu->arch.vrsave;
1494 }
1495
1496 static int set_sregs_base(struct kvm_vcpu *vcpu,
1497 struct kvm_sregs *sregs)
1498 {
1499 if (!(sregs->u.e.features & KVM_SREGS_E_BASE))
1500 return 0;
1501
1502 vcpu->arch.csrr0 = sregs->u.e.csrr0;
1503 vcpu->arch.csrr1 = sregs->u.e.csrr1;
1504 vcpu->arch.mcsr = sregs->u.e.mcsr;
1505 kvmppc_set_esr(vcpu, sregs->u.e.esr);
1506 kvmppc_set_dar(vcpu, sregs->u.e.dear);
1507 vcpu->arch.vrsave = sregs->u.e.vrsave;
1508 kvmppc_set_tcr(vcpu, sregs->u.e.tcr);
1509
1510 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_DEC) {
1511 vcpu->arch.dec = sregs->u.e.dec;
1512 kvmppc_emulate_dec(vcpu);
1513 }
1514
1515 if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR)
1516 kvmppc_set_tsr(vcpu, sregs->u.e.tsr);
1517
1518 return 0;
1519 }
1520
1521 static void get_sregs_arch206(struct kvm_vcpu *vcpu,
1522 struct kvm_sregs *sregs)
1523 {
1524 sregs->u.e.features |= KVM_SREGS_E_ARCH206;
1525
1526 sregs->u.e.pir = vcpu->vcpu_id;
1527 sregs->u.e.mcsrr0 = vcpu->arch.mcsrr0;
1528 sregs->u.e.mcsrr1 = vcpu->arch.mcsrr1;
1529 sregs->u.e.decar = vcpu->arch.decar;
1530 sregs->u.e.ivpr = vcpu->arch.ivpr;
1531 }
1532
1533 static int set_sregs_arch206(struct kvm_vcpu *vcpu,
1534 struct kvm_sregs *sregs)
1535 {
1536 if (!(sregs->u.e.features & KVM_SREGS_E_ARCH206))
1537 return 0;
1538
1539 if (sregs->u.e.pir != vcpu->vcpu_id)
1540 return -EINVAL;
1541
1542 vcpu->arch.mcsrr0 = sregs->u.e.mcsrr0;
1543 vcpu->arch.mcsrr1 = sregs->u.e.mcsrr1;
1544 vcpu->arch.decar = sregs->u.e.decar;
1545 vcpu->arch.ivpr = sregs->u.e.ivpr;
1546
1547 return 0;
1548 }
1549
1550 int kvmppc_get_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
1551 {
1552 sregs->u.e.features |= KVM_SREGS_E_IVOR;
1553
1554 sregs->u.e.ivor_low[0] = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
1555 sregs->u.e.ivor_low[1] = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
1556 sregs->u.e.ivor_low[2] = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
1557 sregs->u.e.ivor_low[3] = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
1558 sregs->u.e.ivor_low[4] = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
1559 sregs->u.e.ivor_low[5] = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
1560 sregs->u.e.ivor_low[6] = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
1561 sregs->u.e.ivor_low[7] = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
1562 sregs->u.e.ivor_low[8] = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
1563 sregs->u.e.ivor_low[9] = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
1564 sregs->u.e.ivor_low[10] = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
1565 sregs->u.e.ivor_low[11] = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
1566 sregs->u.e.ivor_low[12] = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
1567 sregs->u.e.ivor_low[13] = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
1568 sregs->u.e.ivor_low[14] = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
1569 sregs->u.e.ivor_low[15] = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
1570 return 0;
1571 }
1572
1573 int kvmppc_set_sregs_ivor(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
1574 {
1575 if (!(sregs->u.e.features & KVM_SREGS_E_IVOR))
1576 return 0;
1577
1578 vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = sregs->u.e.ivor_low[0];
1579 vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = sregs->u.e.ivor_low[1];
1580 vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = sregs->u.e.ivor_low[2];
1581 vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = sregs->u.e.ivor_low[3];
1582 vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = sregs->u.e.ivor_low[4];
1583 vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = sregs->u.e.ivor_low[5];
1584 vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = sregs->u.e.ivor_low[6];
1585 vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = sregs->u.e.ivor_low[7];
1586 vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = sregs->u.e.ivor_low[8];
1587 vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = sregs->u.e.ivor_low[9];
1588 vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = sregs->u.e.ivor_low[10];
1589 vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = sregs->u.e.ivor_low[11];
1590 vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = sregs->u.e.ivor_low[12];
1591 vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = sregs->u.e.ivor_low[13];
1592 vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = sregs->u.e.ivor_low[14];
1593 vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = sregs->u.e.ivor_low[15];
1594
1595 return 0;
1596 }
1597
1598 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1599 struct kvm_sregs *sregs)
1600 {
1601 sregs->pvr = vcpu->arch.pvr;
1602
1603 get_sregs_base(vcpu, sregs);
1604 get_sregs_arch206(vcpu, sregs);
1605 return vcpu->kvm->arch.kvm_ops->get_sregs(vcpu, sregs);
1606 }
1607
1608 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1609 struct kvm_sregs *sregs)
1610 {
1611 int ret;
1612
1613 if (vcpu->arch.pvr != sregs->pvr)
1614 return -EINVAL;
1615
1616 ret = set_sregs_base(vcpu, sregs);
1617 if (ret < 0)
1618 return ret;
1619
1620 ret = set_sregs_arch206(vcpu, sregs);
1621 if (ret < 0)
1622 return ret;
1623
1624 return vcpu->kvm->arch.kvm_ops->set_sregs(vcpu, sregs);
1625 }
1626
1627 int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
1628 union kvmppc_one_reg *val)
1629 {
1630 int r = 0;
1631
1632 switch (id) {
1633 case KVM_REG_PPC_IAC1:
1634 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac1);
1635 break;
1636 case KVM_REG_PPC_IAC2:
1637 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac2);
1638 break;
1639 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1640 case KVM_REG_PPC_IAC3:
1641 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac3);
1642 break;
1643 case KVM_REG_PPC_IAC4:
1644 *val = get_reg_val(id, vcpu->arch.dbg_reg.iac4);
1645 break;
1646 #endif
1647 case KVM_REG_PPC_DAC1:
1648 *val = get_reg_val(id, vcpu->arch.dbg_reg.dac1);
1649 break;
1650 case KVM_REG_PPC_DAC2:
1651 *val = get_reg_val(id, vcpu->arch.dbg_reg.dac2);
1652 break;
1653 case KVM_REG_PPC_EPR: {
1654 u32 epr = kvmppc_get_epr(vcpu);
1655 *val = get_reg_val(id, epr);
1656 break;
1657 }
1658 #if defined(CONFIG_64BIT)
1659 case KVM_REG_PPC_EPCR:
1660 *val = get_reg_val(id, vcpu->arch.epcr);
1661 break;
1662 #endif
1663 case KVM_REG_PPC_TCR:
1664 *val = get_reg_val(id, vcpu->arch.tcr);
1665 break;
1666 case KVM_REG_PPC_TSR:
1667 *val = get_reg_val(id, vcpu->arch.tsr);
1668 break;
1669 case KVM_REG_PPC_DEBUG_INST:
1670 *val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT);
1671 break;
1672 case KVM_REG_PPC_VRSAVE:
1673 *val = get_reg_val(id, vcpu->arch.vrsave);
1674 break;
1675 default:
1676 r = vcpu->kvm->arch.kvm_ops->get_one_reg(vcpu, id, val);
1677 break;
1678 }
1679
1680 return r;
1681 }
1682
1683 int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id,
1684 union kvmppc_one_reg *val)
1685 {
1686 int r = 0;
1687
1688 switch (id) {
1689 case KVM_REG_PPC_IAC1:
1690 vcpu->arch.dbg_reg.iac1 = set_reg_val(id, *val);
1691 break;
1692 case KVM_REG_PPC_IAC2:
1693 vcpu->arch.dbg_reg.iac2 = set_reg_val(id, *val);
1694 break;
1695 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1696 case KVM_REG_PPC_IAC3:
1697 vcpu->arch.dbg_reg.iac3 = set_reg_val(id, *val);
1698 break;
1699 case KVM_REG_PPC_IAC4:
1700 vcpu->arch.dbg_reg.iac4 = set_reg_val(id, *val);
1701 break;
1702 #endif
1703 case KVM_REG_PPC_DAC1:
1704 vcpu->arch.dbg_reg.dac1 = set_reg_val(id, *val);
1705 break;
1706 case KVM_REG_PPC_DAC2:
1707 vcpu->arch.dbg_reg.dac2 = set_reg_val(id, *val);
1708 break;
1709 case KVM_REG_PPC_EPR: {
1710 u32 new_epr = set_reg_val(id, *val);
1711 kvmppc_set_epr(vcpu, new_epr);
1712 break;
1713 }
1714 #if defined(CONFIG_64BIT)
1715 case KVM_REG_PPC_EPCR: {
1716 u32 new_epcr = set_reg_val(id, *val);
1717 kvmppc_set_epcr(vcpu, new_epcr);
1718 break;
1719 }
1720 #endif
1721 case KVM_REG_PPC_OR_TSR: {
1722 u32 tsr_bits = set_reg_val(id, *val);
1723 kvmppc_set_tsr_bits(vcpu, tsr_bits);
1724 break;
1725 }
1726 case KVM_REG_PPC_CLEAR_TSR: {
1727 u32 tsr_bits = set_reg_val(id, *val);
1728 kvmppc_clr_tsr_bits(vcpu, tsr_bits);
1729 break;
1730 }
1731 case KVM_REG_PPC_TSR: {
1732 u32 tsr = set_reg_val(id, *val);
1733 kvmppc_set_tsr(vcpu, tsr);
1734 break;
1735 }
1736 case KVM_REG_PPC_TCR: {
1737 u32 tcr = set_reg_val(id, *val);
1738 kvmppc_set_tcr(vcpu, tcr);
1739 break;
1740 }
1741 case KVM_REG_PPC_VRSAVE:
1742 vcpu->arch.vrsave = set_reg_val(id, *val);
1743 break;
1744 default:
1745 r = vcpu->kvm->arch.kvm_ops->set_one_reg(vcpu, id, val);
1746 break;
1747 }
1748
1749 return r;
1750 }
1751
1752 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1753 {
1754 return -ENOTSUPP;
1755 }
1756
1757 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1758 {
1759 return -ENOTSUPP;
1760 }
1761
1762 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1763 struct kvm_translation *tr)
1764 {
1765 int r;
1766
1767 r = kvmppc_core_vcpu_translate(vcpu, tr);
1768 return r;
1769 }
1770
1771 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1772 {
1773 return -ENOTSUPP;
1774 }
1775
1776 void kvmppc_core_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
1777 struct kvm_memory_slot *dont)
1778 {
1779 }
1780
1781 int kvmppc_core_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
1782 unsigned long npages)
1783 {
1784 return 0;
1785 }
1786
1787 int kvmppc_core_prepare_memory_region(struct kvm *kvm,
1788 struct kvm_memory_slot *memslot,
1789 const struct kvm_userspace_memory_region *mem)
1790 {
1791 return 0;
1792 }
1793
1794 void kvmppc_core_commit_memory_region(struct kvm *kvm,
1795 const struct kvm_userspace_memory_region *mem,
1796 const struct kvm_memory_slot *old,
1797 const struct kvm_memory_slot *new)
1798 {
1799 }
1800
1801 void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot)
1802 {
1803 }
1804
1805 void kvmppc_set_epcr(struct kvm_vcpu *vcpu, u32 new_epcr)
1806 {
1807 #if defined(CONFIG_64BIT)
1808 vcpu->arch.epcr = new_epcr;
1809 #ifdef CONFIG_KVM_BOOKE_HV
1810 vcpu->arch.shadow_epcr &= ~SPRN_EPCR_GICM;
1811 if (vcpu->arch.epcr & SPRN_EPCR_ICM)
1812 vcpu->arch.shadow_epcr |= SPRN_EPCR_GICM;
1813 #endif
1814 #endif
1815 }
1816
1817 void kvmppc_set_tcr(struct kvm_vcpu *vcpu, u32 new_tcr)
1818 {
1819 vcpu->arch.tcr = new_tcr;
1820 arm_next_watchdog(vcpu);
1821 update_timer_ints(vcpu);
1822 }
1823
1824 void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1825 {
1826 set_bits(tsr_bits, &vcpu->arch.tsr);
1827 smp_wmb();
1828 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1829 kvm_vcpu_kick(vcpu);
1830 }
1831
1832 void kvmppc_clr_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
1833 {
1834 clear_bits(tsr_bits, &vcpu->arch.tsr);
1835
1836 /*
1837 * We may have stopped the watchdog due to
1838 * being stuck on final expiration.
1839 */
1840 if (tsr_bits & (TSR_ENW | TSR_WIS))
1841 arm_next_watchdog(vcpu);
1842
1843 update_timer_ints(vcpu);
1844 }
1845
1846 void kvmppc_decrementer_func(struct kvm_vcpu *vcpu)
1847 {
1848 if (vcpu->arch.tcr & TCR_ARE) {
1849 vcpu->arch.dec = vcpu->arch.decar;
1850 kvmppc_emulate_dec(vcpu);
1851 }
1852
1853 kvmppc_set_tsr_bits(vcpu, TSR_DIS);
1854 }
1855
1856 static int kvmppc_booke_add_breakpoint(struct debug_reg *dbg_reg,
1857 uint64_t addr, int index)
1858 {
1859 switch (index) {
1860 case 0:
1861 dbg_reg->dbcr0 |= DBCR0_IAC1;
1862 dbg_reg->iac1 = addr;
1863 break;
1864 case 1:
1865 dbg_reg->dbcr0 |= DBCR0_IAC2;
1866 dbg_reg->iac2 = addr;
1867 break;
1868 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1869 case 2:
1870 dbg_reg->dbcr0 |= DBCR0_IAC3;
1871 dbg_reg->iac3 = addr;
1872 break;
1873 case 3:
1874 dbg_reg->dbcr0 |= DBCR0_IAC4;
1875 dbg_reg->iac4 = addr;
1876 break;
1877 #endif
1878 default:
1879 return -EINVAL;
1880 }
1881
1882 dbg_reg->dbcr0 |= DBCR0_IDM;
1883 return 0;
1884 }
1885
1886 static int kvmppc_booke_add_watchpoint(struct debug_reg *dbg_reg, uint64_t addr,
1887 int type, int index)
1888 {
1889 switch (index) {
1890 case 0:
1891 if (type & KVMPPC_DEBUG_WATCH_READ)
1892 dbg_reg->dbcr0 |= DBCR0_DAC1R;
1893 if (type & KVMPPC_DEBUG_WATCH_WRITE)
1894 dbg_reg->dbcr0 |= DBCR0_DAC1W;
1895 dbg_reg->dac1 = addr;
1896 break;
1897 case 1:
1898 if (type & KVMPPC_DEBUG_WATCH_READ)
1899 dbg_reg->dbcr0 |= DBCR0_DAC2R;
1900 if (type & KVMPPC_DEBUG_WATCH_WRITE)
1901 dbg_reg->dbcr0 |= DBCR0_DAC2W;
1902 dbg_reg->dac2 = addr;
1903 break;
1904 default:
1905 return -EINVAL;
1906 }
1907
1908 dbg_reg->dbcr0 |= DBCR0_IDM;
1909 return 0;
1910 }
1911 void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap, bool set)
1912 {
1913 /* XXX: Add similar MSR protection for BookE-PR */
1914 #ifdef CONFIG_KVM_BOOKE_HV
1915 BUG_ON(prot_bitmap & ~(MSRP_UCLEP | MSRP_DEP | MSRP_PMMP));
1916 if (set) {
1917 if (prot_bitmap & MSR_UCLE)
1918 vcpu->arch.shadow_msrp |= MSRP_UCLEP;
1919 if (prot_bitmap & MSR_DE)
1920 vcpu->arch.shadow_msrp |= MSRP_DEP;
1921 if (prot_bitmap & MSR_PMM)
1922 vcpu->arch.shadow_msrp |= MSRP_PMMP;
1923 } else {
1924 if (prot_bitmap & MSR_UCLE)
1925 vcpu->arch.shadow_msrp &= ~MSRP_UCLEP;
1926 if (prot_bitmap & MSR_DE)
1927 vcpu->arch.shadow_msrp &= ~MSRP_DEP;
1928 if (prot_bitmap & MSR_PMM)
1929 vcpu->arch.shadow_msrp &= ~MSRP_PMMP;
1930 }
1931 #endif
1932 }
1933
1934 int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr, enum xlate_instdata xlid,
1935 enum xlate_readwrite xlrw, struct kvmppc_pte *pte)
1936 {
1937 int gtlb_index;
1938 gpa_t gpaddr;
1939
1940 #ifdef CONFIG_KVM_E500V2
1941 if (!(vcpu->arch.shared->msr & MSR_PR) &&
1942 (eaddr & PAGE_MASK) == vcpu->arch.magic_page_ea) {
1943 pte->eaddr = eaddr;
1944 pte->raddr = (vcpu->arch.magic_page_pa & PAGE_MASK) |
1945 (eaddr & ~PAGE_MASK);
1946 pte->vpage = eaddr >> PAGE_SHIFT;
1947 pte->may_read = true;
1948 pte->may_write = true;
1949 pte->may_execute = true;
1950
1951 return 0;
1952 }
1953 #endif
1954
1955 /* Check the guest TLB. */
1956 switch (xlid) {
1957 case XLATE_INST:
1958 gtlb_index = kvmppc_mmu_itlb_index(vcpu, eaddr);
1959 break;
1960 case XLATE_DATA:
1961 gtlb_index = kvmppc_mmu_dtlb_index(vcpu, eaddr);
1962 break;
1963 default:
1964 BUG();
1965 }
1966
1967 /* Do we have a TLB entry at all? */
1968 if (gtlb_index < 0)
1969 return -ENOENT;
1970
1971 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1972
1973 pte->eaddr = eaddr;
1974 pte->raddr = (gpaddr & PAGE_MASK) | (eaddr & ~PAGE_MASK);
1975 pte->vpage = eaddr >> PAGE_SHIFT;
1976
1977 /* XXX read permissions from the guest TLB */
1978 pte->may_read = true;
1979 pte->may_write = true;
1980 pte->may_execute = true;
1981
1982 return 0;
1983 }
1984
1985 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
1986 struct kvm_guest_debug *dbg)
1987 {
1988 struct debug_reg *dbg_reg;
1989 int n, b = 0, w = 0;
1990
1991 if (!(dbg->control & KVM_GUESTDBG_ENABLE)) {
1992 vcpu->arch.dbg_reg.dbcr0 = 0;
1993 vcpu->guest_debug = 0;
1994 kvm_guest_protect_msr(vcpu, MSR_DE, false);
1995 return 0;
1996 }
1997
1998 kvm_guest_protect_msr(vcpu, MSR_DE, true);
1999 vcpu->guest_debug = dbg->control;
2000 vcpu->arch.dbg_reg.dbcr0 = 0;
2001
2002 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2003 vcpu->arch.dbg_reg.dbcr0 |= DBCR0_IDM | DBCR0_IC;
2004
2005 /* Code below handles only HW breakpoints */
2006 dbg_reg = &(vcpu->arch.dbg_reg);
2007
2008 #ifdef CONFIG_KVM_BOOKE_HV
2009 /*
2010 * On BookE-HV (e500mc) the guest is always executed with MSR.GS=1
2011 * DBCR1 and DBCR2 are set to trigger debug events when MSR.PR is 0
2012 */
2013 dbg_reg->dbcr1 = 0;
2014 dbg_reg->dbcr2 = 0;
2015 #else
2016 /*
2017 * On BookE-PR (e500v2) the guest is always executed with MSR.PR=1
2018 * We set DBCR1 and DBCR2 to only trigger debug events when MSR.PR
2019 * is set.
2020 */
2021 dbg_reg->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | DBCR1_IAC3US |
2022 DBCR1_IAC4US;
2023 dbg_reg->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
2024 #endif
2025
2026 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2027 return 0;
2028
2029 for (n = 0; n < (KVMPPC_BOOKE_IAC_NUM + KVMPPC_BOOKE_DAC_NUM); n++) {
2030 uint64_t addr = dbg->arch.bp[n].addr;
2031 uint32_t type = dbg->arch.bp[n].type;
2032
2033 if (type == KVMPPC_DEBUG_NONE)
2034 continue;
2035
2036 if (type & !(KVMPPC_DEBUG_WATCH_READ |
2037 KVMPPC_DEBUG_WATCH_WRITE |
2038 KVMPPC_DEBUG_BREAKPOINT))
2039 return -EINVAL;
2040
2041 if (type & KVMPPC_DEBUG_BREAKPOINT) {
2042 /* Setting H/W breakpoint */
2043 if (kvmppc_booke_add_breakpoint(dbg_reg, addr, b++))
2044 return -EINVAL;
2045 } else {
2046 /* Setting H/W watchpoint */
2047 if (kvmppc_booke_add_watchpoint(dbg_reg, addr,
2048 type, w++))
2049 return -EINVAL;
2050 }
2051 }
2052
2053 return 0;
2054 }
2055
2056 void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2057 {
2058 vcpu->cpu = smp_processor_id();
2059 current->thread.kvm_vcpu = vcpu;
2060 }
2061
2062 void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu)
2063 {
2064 current->thread.kvm_vcpu = NULL;
2065 vcpu->cpu = -1;
2066
2067 /* Clear pending debug event in DBSR */
2068 kvmppc_clear_dbsr();
2069 }
2070
2071 void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
2072 {
2073 vcpu->kvm->arch.kvm_ops->mmu_destroy(vcpu);
2074 }
2075
2076 int kvmppc_core_init_vm(struct kvm *kvm)
2077 {
2078 return kvm->arch.kvm_ops->init_vm(kvm);
2079 }
2080
2081 struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
2082 {
2083 return kvm->arch.kvm_ops->vcpu_create(kvm, id);
2084 }
2085
2086 void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
2087 {
2088 vcpu->kvm->arch.kvm_ops->vcpu_free(vcpu);
2089 }
2090
2091 void kvmppc_core_destroy_vm(struct kvm *kvm)
2092 {
2093 kvm->arch.kvm_ops->destroy_vm(kvm);
2094 }
2095
2096 void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2097 {
2098 vcpu->kvm->arch.kvm_ops->vcpu_load(vcpu, cpu);
2099 }
2100
2101 void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu)
2102 {
2103 vcpu->kvm->arch.kvm_ops->vcpu_put(vcpu);
2104 }
2105
2106 int __init kvmppc_booke_init(void)
2107 {
2108 #ifndef CONFIG_KVM_BOOKE_HV
2109 unsigned long ivor[16];
2110 unsigned long *handler = kvmppc_booke_handler_addr;
2111 unsigned long max_ivor = 0;
2112 unsigned long handler_len;
2113 int i;
2114
2115 /* We install our own exception handlers by hijacking IVPR. IVPR must
2116 * be 16-bit aligned, so we need a 64KB allocation. */
2117 kvmppc_booke_handlers = __get_free_pages(GFP_KERNEL | __GFP_ZERO,
2118 VCPU_SIZE_ORDER);
2119 if (!kvmppc_booke_handlers)
2120 return -ENOMEM;
2121
2122 /* XXX make sure our handlers are smaller than Linux's */
2123
2124 /* Copy our interrupt handlers to match host IVORs. That way we don't
2125 * have to swap the IVORs on every guest/host transition. */
2126 ivor[0] = mfspr(SPRN_IVOR0);
2127 ivor[1] = mfspr(SPRN_IVOR1);
2128 ivor[2] = mfspr(SPRN_IVOR2);
2129 ivor[3] = mfspr(SPRN_IVOR3);
2130 ivor[4] = mfspr(SPRN_IVOR4);
2131 ivor[5] = mfspr(SPRN_IVOR5);
2132 ivor[6] = mfspr(SPRN_IVOR6);
2133 ivor[7] = mfspr(SPRN_IVOR7);
2134 ivor[8] = mfspr(SPRN_IVOR8);
2135 ivor[9] = mfspr(SPRN_IVOR9);
2136 ivor[10] = mfspr(SPRN_IVOR10);
2137 ivor[11] = mfspr(SPRN_IVOR11);
2138 ivor[12] = mfspr(SPRN_IVOR12);
2139 ivor[13] = mfspr(SPRN_IVOR13);
2140 ivor[14] = mfspr(SPRN_IVOR14);
2141 ivor[15] = mfspr(SPRN_IVOR15);
2142
2143 for (i = 0; i < 16; i++) {
2144 if (ivor[i] > max_ivor)
2145 max_ivor = i;
2146
2147 handler_len = handler[i + 1] - handler[i];
2148 memcpy((void *)kvmppc_booke_handlers + ivor[i],
2149 (void *)handler[i], handler_len);
2150 }
2151
2152 handler_len = handler[max_ivor + 1] - handler[max_ivor];
2153 flush_icache_range(kvmppc_booke_handlers, kvmppc_booke_handlers +
2154 ivor[max_ivor] + handler_len);
2155 #endif /* !BOOKE_HV */
2156 return 0;
2157 }
2158
2159 void __exit kvmppc_booke_exit(void)
2160 {
2161 free_pages(kvmppc_booke_handlers, VCPU_SIZE_ORDER);
2162 kvm_exit();
2163 }
Linux with added FPC-III support