2 * This file contains assembly-language implementations
3 * of IP-style 1's complement checksum routines.
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
12 * Severely hacked about by Paul Mackerras (paulus@cs.anu.edu.au).
15 #include <linux/sys.h>
16 #include <asm/processor.h>
17 #include <asm/errno.h>
18 #include <asm/ppc_asm.h>
21 * ip_fast_csum(r3=buf, r4=len) -- Optimized for IP header
22 * len is in words and is always >= 5.
24 * In practice len == 5, but this is not guaranteed. So this code does not
25 * attempt to use doubleword instructions.
37 addze r0,r0 /* add in final carry */
38 rldicl r4,r0,32,0 /* fold two 32-bit halves together */
41 rlwinm r3,r0,16,0,31 /* fold two halves together */
48 * Computes the checksum of a memory block at buff, length len,
49 * and adds in "sum" (32-bit).
51 * csum_partial(r3=buff, r4=len, r5=sum)
54 addic r0,r5,0 /* clear carry */
56 srdi. r6,r4,3 /* less than 8 bytes? */
60 * If only halfword aligned, align to a double word. Since odd
61 * aligned addresses should be rare and they would require more
62 * work to calculate the correct checksum, we ignore that case
63 * and take the potential slowdown of unaligned loads.
65 rldicl. r6,r3,64-1,64-2 /* r6 = (r3 & 0x3) >> 1 */
73 lhz r6,0(r3) /* align to doubleword */
81 * We unroll the loop such that each iteration is 64 bytes with an
82 * entry and exit limb of 64 bytes, meaning a minimum size of
86 beq .Lcsum_tail_doublewords /* len < 128 */
92 stdu r1,-STACKFRAMESIZE(r1)
93 std r14,STK_REG(R14)(r1)
94 std r15,STK_REG(R15)(r1)
95 std r16,STK_REG(R16)(r1)
104 * On POWER6 and POWER7 back to back addes take 2 cycles because of
105 * the XER dependency. This means the fastest this loop can go is
106 * 16 cycles per iteration. The scheduling of the loop below has
107 * been shown to hit this on both POWER6 and POWER7.
154 ld r14,STK_REG(R14)(r1)
155 ld r15,STK_REG(R15)(r1)
156 ld r16,STK_REG(R16)(r1)
157 addi r1,r1,STACKFRAMESIZE
161 .Lcsum_tail_doublewords: /* Up to 127 bytes to go */
174 .Lcsum_tail_word: /* Up to 7 bytes to go */
176 beq .Lcsum_tail_halfword
183 .Lcsum_tail_halfword: /* Up to 3 bytes to go */
192 .Lcsum_tail_byte: /* Up to 1 byte to go */
197 sldi r9,r6,8 /* Pad the byte out to 16 bits */
201 addze r0,r0 /* add in final carry */
202 rldicl r4,r0,32,0 /* fold two 32 bit halves together */
210 .section __ex_table,"a"
212 .llong 100b,.Lsrc_error_nr
218 .section __ex_table,"a"
220 .llong 150b,.Lsrc_error
226 .section __ex_table,"a"
228 .llong 200b,.Ldest_error_nr
234 .section __ex_table,"a"
236 .llong 250b,.Ldest_error
241 * Computes the checksum of a memory block at src, length len,
242 * and adds in "sum" (32-bit), while copying the block to dst.
243 * If an access exception occurs on src or dst, it stores -EFAULT
244 * to *src_err or *dst_err respectively. The caller must take any action
245 * required in this case (zeroing memory, recalculating partial checksum etc).
247 * csum_partial_copy_generic(r3=src, r4=dst, r5=len, r6=sum, r7=src_err, r8=dst_err)
249 _GLOBAL(csum_partial_copy_generic)
250 addic r0,r6,0 /* clear carry */
252 srdi. r6,r5,3 /* less than 8 bytes? */
256 * If only halfword aligned, align to a double word. Since odd
257 * aligned addresses should be rare and they would require more
258 * work to calculate the correct checksum, we ignore that case
259 * and take the potential slowdown of unaligned loads.
261 * If the source and destination are relatively unaligned we only
262 * align the source. This keeps things simple.
264 rldicl. r6,r3,64-1,64-2 /* r6 = (r3 & 0x3) >> 1 */
272 srcnr; lhz r6,0(r3) /* align to doubleword */
282 * We unroll the loop such that each iteration is 64 bytes with an
283 * entry and exit limb of 64 bytes, meaning a minimum size of
287 beq .Lcopy_tail_doublewords /* len < 128 */
293 stdu r1,-STACKFRAMESIZE(r1)
294 std r14,STK_REG(R14)(r1)
295 std r15,STK_REG(R15)(r1)
296 std r16,STK_REG(R16)(r1)
301 source; ld r10,16(r3)
302 source; ld r11,24(r3)
305 * On POWER6 and POWER7 back to back addes take 2 cycles because of
306 * the XER dependency. This means the fastest this loop can go is
307 * 16 cycles per iteration. The scheduling of the loop below has
308 * been shown to hit this on both POWER6 and POWER7.
313 source; ld r12,32(r3)
314 source; ld r14,40(r3)
317 source; ld r15,48(r3)
318 source; ld r16,56(r3)
343 source; ld r10,16(r3)
344 source; ld r11,24(r3)
349 source; ld r12,32(r3)
350 source; ld r14,40(r3)
353 source; ld r15,48(r3)
354 source; ld r16,56(r3)
377 ld r14,STK_REG(R14)(r1)
378 ld r15,STK_REG(R15)(r1)
379 ld r16,STK_REG(R16)(r1)
380 addi r1,r1,STACKFRAMESIZE
384 .Lcopy_tail_doublewords: /* Up to 127 bytes to go */
399 .Lcopy_tail_word: /* Up to 7 bytes to go */
401 beq .Lcopy_tail_halfword
410 .Lcopy_tail_halfword: /* Up to 3 bytes to go */
421 .Lcopy_tail_byte: /* Up to 1 byte to go */
426 sldi r9,r6,8 /* Pad the byte out to 16 bits */
431 addze r0,r0 /* add in final carry */
432 rldicl r4,r0,32,0 /* fold two 32 bit halves together */
438 ld r14,STK_REG(R14)(r1)
439 ld r15,STK_REG(R15)(r1)
440 ld r16,STK_REG(R16)(r1)
441 addi r1,r1,STACKFRAMESIZE
450 ld r14,STK_REG(R14)(r1)
451 ld r15,STK_REG(R15)(r1)
452 ld r16,STK_REG(R16)(r1)
453 addi r1,r1,STACKFRAMESIZE