arch/x86/kernel/fpu/init.c

   1 /*
   2  * x86 FPU boot time init code:
   3  */
   4 #include <asm/fpu/internal.h>
   5 #include <asm/tlbflush.h>
   6
   7 #include <linux/sched.h>
   8
   9 /*
  10  * Initialize the TS bit in CR0 according to the style of context-switches
  11  * we are using:
  12  */
  13 static void fpu__init_cpu_ctx_switch(void)
  14 {
  15         if (!boot_cpu_has(X86_FEATURE_EAGER_FPU))
  16                 stts();
  17         else
  18                 clts();
  19 }
  20
  21 /*
  22  * Initialize the registers found in all CPUs, CR0 and CR4:
  23  */
  24 static void fpu__init_cpu_generic(void)
  25 {
  26         unsigned long cr0;
  27         unsigned long cr4_mask = 0;
  28
  29         if (cpu_has_fxsr)
  30                 cr4_mask |= X86_CR4_OSFXSR;
  31         if (cpu_has_xmm)
  32                 cr4_mask |= X86_CR4_OSXMMEXCPT;
  33         if (cr4_mask)
  34                 cr4_set_bits(cr4_mask);
  35
  36         cr0 = read_cr0();
  37         cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */
  38         if (!cpu_has_fpu)
  39                 cr0 |= X86_CR0_EM;
  40         write_cr0(cr0);
  41
  42         /* Flush out any pending x87 state: */
  43 #ifdef CONFIG_MATH_EMULATION
  44         if (!cpu_has_fpu)
  45                 fpstate_init_soft(&current->thread.fpu.state.soft);
  46         else
  47 #endif
  48                 asm volatile ("fninit");
  49 }
  50
  51 /*
  52  * Enable all supported FPU features. Called when a CPU is brought online:
  53  */
  54 void fpu__init_cpu(void)
  55 {
  56         fpu__init_cpu_generic();
  57         fpu__init_cpu_xstate();
  58         fpu__init_cpu_ctx_switch();
  59 }
  60
  61 /*
  62  * The earliest FPU detection code.
  63  *
  64  * Set the X86_FEATURE_FPU CPU-capability bit based on
  65  * trying to execute an actual sequence of FPU instructions:
  66  */
  67 static void fpu__init_system_early_generic(struct cpuinfo_x86 *c)
  68 {
  69         unsigned long cr0;
  70         u16 fsw, fcw;
  71
  72         fsw = fcw = 0xffff;
  73
  74         cr0 = read_cr0();
  75         cr0 &= ~(X86_CR0_TS | X86_CR0_EM);
  76         write_cr0(cr0);
  77
  78         asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
  79                      : "+m" (fsw), "+m" (fcw));
  80
  81         if (fsw == 0 && (fcw & 0x103f) == 0x003f)
  82                 set_cpu_cap(c, X86_FEATURE_FPU);
  83         else
  84                 clear_cpu_cap(c, X86_FEATURE_FPU);
  85
  86 #ifndef CONFIG_MATH_EMULATION
  87         if (!cpu_has_fpu) {
  88                 pr_emerg("x86/fpu: Giving up, no FPU found and no math emulation present\n");
  89                 for (;;)
  90                         asm volatile("hlt");
  91         }
  92 #endif
  93 }
  94
  95 /*
  96  * Boot time FPU feature detection code:
  97  */
  98 unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu;
  99
 100 static void __init fpu__init_system_mxcsr(void)
 101 {
 102         unsigned int mask = 0;
 103
 104         if (cpu_has_fxsr) {
 105                 /* Static because GCC does not get 16-byte stack alignment right: */
 106                 static struct fxregs_state fxregs __initdata;
 107
 108                 asm volatile("fxsave %0" : "+m" (fxregs));
 109
 110                 mask = fxregs.mxcsr_mask;
 111
 112                 /*
 113                  * If zero then use the default features mask,
 114                  * which has all features set, except the
 115                  * denormals-are-zero feature bit:
 116                  */
 117                 if (mask == 0)
 118                         mask = 0x0000ffbf;
 119         }
 120         mxcsr_feature_mask &= mask;
 121 }
 122
 123 /*
 124  * Once per bootup FPU initialization sequences that will run on most x86 CPUs:
 125  */
 126 static void __init fpu__init_system_generic(void)
 127 {
 128         /*
 129          * Set up the legacy init FPU context. (xstate init might overwrite this
 130          * with a more modern format, if the CPU supports it.)
 131          */
 132         fpstate_init_fxstate(&init_fpstate.fxsave);
 133
 134         fpu__init_system_mxcsr();
 135 }
 136
 137 /*
 138  * Size of the FPU context state. All tasks in the system use the
 139  * same context size, regardless of what portion they use.
 140  * This is inherent to the XSAVE architecture which puts all state
 141  * components into a single, continuous memory block:
 142  */
 143 unsigned int xstate_size;
 144 EXPORT_SYMBOL_GPL(xstate_size);
 145
 146 /* Get alignment of the TYPE. */
 147 #define TYPE_ALIGN(TYPE) offsetof(struct { char x; TYPE test; }, test)
 148
 149 /*
 150  * Enforce that 'MEMBER' is the last field of 'TYPE'.
 151  *
 152  * Align the computed size with alignment of the TYPE,
 153  * because that's how C aligns structs.
 154  */
 155 #define CHECK_MEMBER_AT_END_OF(TYPE, MEMBER) \
 156         BUILD_BUG_ON(sizeof(TYPE) != ALIGN(offsetofend(TYPE, MEMBER), \
 157                                            TYPE_ALIGN(TYPE)))
 158
 159 /*
 160  * We append the 'struct fpu' to the task_struct:
 161  */
 162 static void __init fpu__init_task_struct_size(void)
 163 {
 164         int task_size = sizeof(struct task_struct);
 165
 166         /*
 167          * Subtract off the static size of the register state.
 168          * It potentially has a bunch of padding.
 169          */
 170         task_size -= sizeof(((struct task_struct *)0)->thread.fpu.state);
 171
 172         /*
 173          * Add back the dynamically-calculated register state
 174          * size.
 175          */
 176         task_size += xstate_size;
 177
 178         /*
 179          * We dynamically size 'struct fpu', so we require that
 180          * it be at the end of 'thread_struct' and that
 181          * 'thread_struct' be at the end of 'task_struct'.  If
 182          * you hit a compile error here, check the structure to
 183          * see if something got added to the end.
 184          */
 185         CHECK_MEMBER_AT_END_OF(struct fpu, state);
 186         CHECK_MEMBER_AT_END_OF(struct thread_struct, fpu);
 187         CHECK_MEMBER_AT_END_OF(struct task_struct, thread);
 188
 189         arch_task_struct_size = task_size;
 190 }
 191
 192 /*
 193  * Set up the xstate_size based on the legacy FPU context size.
 194  *
 195  * We set this up first, and later it will be overwritten by
 196  * fpu__init_system_xstate() if the CPU knows about xstates.
 197  */
 198 static void __init fpu__init_system_xstate_size_legacy(void)
 199 {
 200         static int on_boot_cpu __initdata = 1;
 201
 202         WARN_ON_FPU(!on_boot_cpu);
 203         on_boot_cpu = 0;
 204
 205         /*
 206          * Note that xstate_size might be overwriten later during
 207          * fpu__init_system_xstate().
 208          */
 209
 210         if (!cpu_has_fpu) {
 211                 /*
 212                  * Disable xsave as we do not support it if i387
 213                  * emulation is enabled.
 214                  */
 215                 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
 216                 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
 217                 xstate_size = sizeof(struct swregs_state);
 218         } else {
 219                 if (cpu_has_fxsr)
 220                         xstate_size = sizeof(struct fxregs_state);
 221                 else
 222                         xstate_size = sizeof(struct fregs_state);
 223         }
 224         /*
 225          * Quirk: we don't yet handle the XSAVES* instructions
 226          * correctly, as we don't correctly convert between
 227          * standard and compacted format when interfacing
 228          * with user-space - so disable it for now.
 229          *
 230          * The difference is small: with recent CPUs the
 231          * compacted format is only marginally smaller than
 232          * the standard FPU state format.
 233          *
 234          * ( This is easy to backport while we are fixing
 235          *   XSAVES* support. )
 236          */
 237         setup_clear_cpu_cap(X86_FEATURE_XSAVES);
 238 }
 239
 240 /*
 241  * FPU context switching strategies:
 242  *
 243  * Against popular belief, we don't do lazy FPU saves, due to the
 244  * task migration complications it brings on SMP - we only do
 245  * lazy FPU restores.
 246  *
 247  * 'lazy' is the traditional strategy, which is based on setting
 248  * CR0::TS to 1 during context-switch (instead of doing a full
 249  * restore of the FPU state), which causes the first FPU instruction
 250  * after the context switch (whenever it is executed) to fault - at
 251  * which point we lazily restore the FPU state into FPU registers.
 252  *
 253  * Tasks are of course under no obligation to execute FPU instructions,
 254  * so it can easily happen that another context-switch occurs without
 255  * a single FPU instruction being executed. If we eventually switch
 256  * back to the original task (that still owns the FPU) then we have
 257  * not only saved the restores along the way, but we also have the
 258  * FPU ready to be used for the original task.
 259  *
 260  * 'eager' switching is used on modern CPUs, there we switch the FPU
 261  * state during every context switch, regardless of whether the task
 262  * has used FPU instructions in that time slice or not. This is done
 263  * because modern FPU context saving instructions are able to optimize
 264  * state saving and restoration in hardware: they can detect both
 265  * unused and untouched FPU state and optimize accordingly.
 266  *
 267  * [ Note that even in 'lazy' mode we might optimize context switches
 268  *   to use 'eager' restores, if we detect that a task is using the FPU
 269  *   frequently. See the fpu->counter logic in fpu/internal.h for that. ]
 270  */
 271 static enum { AUTO, ENABLE, DISABLE } eagerfpu = AUTO;
 272
 273 static int __init eager_fpu_setup(char *s)
 274 {
 275         if (!strcmp(s, "on"))
 276                 eagerfpu = ENABLE;
 277         else if (!strcmp(s, "off"))
 278                 eagerfpu = DISABLE;
 279         else if (!strcmp(s, "auto"))
 280                 eagerfpu = AUTO;
 281         return 1;
 282 }
 283 __setup("eagerfpu=", eager_fpu_setup);
 284
 285 /*
 286  * Pick the FPU context switching strategy:
 287  */
 288 static void __init fpu__init_system_ctx_switch(void)
 289 {
 290         static bool on_boot_cpu __initdata = 1;
 291
 292         WARN_ON_FPU(!on_boot_cpu);
 293         on_boot_cpu = 0;
 294
 295         WARN_ON_FPU(current->thread.fpu.fpstate_active);
 296         current_thread_info()->status = 0;
 297
 298         /* Auto enable eagerfpu for xsaveopt */
 299         if (boot_cpu_has(X86_FEATURE_XSAVEOPT) && eagerfpu != DISABLE)
 300                 eagerfpu = ENABLE;
 301
 302         if (xfeatures_mask & XFEATURE_MASK_EAGER) {
 303                 if (eagerfpu == DISABLE) {
 304                         pr_err("x86/fpu: eagerfpu switching disabled, disabling the following xstate features: 0x%llx.\n",
 305                                xfeatures_mask & XFEATURE_MASK_EAGER);
 306                         xfeatures_mask &= ~XFEATURE_MASK_EAGER;
 307                 } else {
 308                         eagerfpu = ENABLE;
 309                 }
 310         }
 311
 312         if (eagerfpu == ENABLE)
 313                 setup_force_cpu_cap(X86_FEATURE_EAGER_FPU);
 314
 315         printk(KERN_INFO "x86/fpu: Using '%s' FPU context switches.\n", eagerfpu == ENABLE ? "eager" : "lazy");
 316 }
 317
 318 /*
 319  * Called on the boot CPU once per system bootup, to set up the initial
 320  * FPU state that is later cloned into all processes:
 321  */
 322 void __init fpu__init_system(struct cpuinfo_x86 *c)
 323 {
 324         fpu__init_system_early_generic(c);
 325
 326         /*
 327          * The FPU has to be operational for some of the
 328          * later FPU init activities:
 329          */
 330         fpu__init_cpu();
 331
 332         /*
 333          * But don't leave CR0::TS set yet, as some of the FPU setup
 334          * methods depend on being able to execute FPU instructions
 335          * that will fault on a set TS, such as the FXSAVE in
 336          * fpu__init_system_mxcsr().
 337          */
 338         clts();
 339
 340         fpu__init_system_generic();
 341         fpu__init_system_xstate_size_legacy();
 342         fpu__init_system_xstate();
 343         fpu__init_task_struct_size();
 344
 345         fpu__init_system_ctx_switch();
 346 }
 347
 348 /*
 349  * Boot parameter to turn off FPU support and fall back to math-emu:
 350  */
 351 static int __init no_387(char *s)
 352 {
 353         setup_clear_cpu_cap(X86_FEATURE_FPU);
 354         return 1;
 355 }
 356 __setup("no387", no_387);
 357
 358 /*
 359  * Disable all xstate CPU features:
 360  */
 361 static int __init x86_noxsave_setup(char *s)
 362 {
 363         if (strlen(s))
 364                 return 0;
 365
 366         fpu__xstate_clear_all_cpu_caps();
 367
 368         return 1;
 369 }
 370 __setup("noxsave", x86_noxsave_setup);
 371
 372 /*
 373  * Disable the XSAVEOPT instruction specifically:
 374  */
 375 static int __init x86_noxsaveopt_setup(char *s)
 376 {
 377         setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
 378
 379         return 1;
 380 }
 381 __setup("noxsaveopt", x86_noxsaveopt_setup);
 382
 383 /*
 384  * Disable the XSAVES instruction:
 385  */
 386 static int __init x86_noxsaves_setup(char *s)
 387 {
 388         setup_clear_cpu_cap(X86_FEATURE_XSAVES);
 389
 390         return 1;
 391 }
 392 __setup("noxsaves", x86_noxsaves_setup);
 393
 394 /*
 395  * Disable FX save/restore and SSE support:
 396  */
 397 static int __init x86_nofxsr_setup(char *s)
 398 {
 399         setup_clear_cpu_cap(X86_FEATURE_FXSR);
 400         setup_clear_cpu_cap(X86_FEATURE_FXSR_OPT);
 401         setup_clear_cpu_cap(X86_FEATURE_XMM);
 402
 403         return 1;
 404 }
 405 __setup("nofxsr", x86_nofxsr_setup);