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of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / arch / x86 / kvm / lapic.c
blob4d30b865be30641f4964a3279939020e9f1a057a
1
2 /*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
23 #include <linux/mm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
32 #include <asm/msr.h>
33 #include <asm/page.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
40 #include "irq.h"
41 #include "trace.h"
42 #include "x86.h"
43 #include "cpuid.h"
44
45 #ifndef CONFIG_X86_64
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47 #else
48 #define mod_64(x, y) ((x) % (y))
49 #endif
50
51 #define PRId64 "d"
52 #define PRIx64 "llx"
53 #define PRIu64 "u"
54 #define PRIo64 "o"
55
56 #define APIC_BUS_CYCLE_NS 1
57
58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59 #define apic_debug(fmt, arg...)
60
61 #define APIC_LVT_NUM 6
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
71
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
74
75 #define VEC_POS(v) ((v) & (32 - 1))
76 #define REG_POS(v) (((v) >> 5) << 4)
77
78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79 {
80 *((u32 *) (apic->regs + reg_off)) = val;
81 }
82
83 static inline int apic_test_vector(int vec, void *bitmap)
84 {
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86 }
87
88 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89 {
90 struct kvm_lapic *apic = vcpu->arch.apic;
91
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
94 }
95
96 static inline void apic_set_vector(int vec, void *bitmap)
97 {
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99 }
100
101 static inline void apic_clear_vector(int vec, void *bitmap)
102 {
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104 }
105
106 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107 {
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109 }
110
111 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112 {
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114 }
115
116 struct static_key_deferred apic_hw_disabled __read_mostly;
117 struct static_key_deferred apic_sw_disabled __read_mostly;
118
119 static inline int apic_enabled(struct kvm_lapic *apic)
120 {
121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
122 }
123
124 #define LVT_MASK \
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126
127 #define LINT_MASK \
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130
131 static inline int kvm_apic_id(struct kvm_lapic *apic)
132 {
133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
134 }
135
136 /* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
138 */
139 static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
140 {
141 return !(map->mode & (map->mode - 1));
142 }
143
144 static inline void
145 apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
146 {
147 unsigned lid_bits;
148
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
152 lid_bits = map->mode;
153
154 *cid = dest_id >> lid_bits;
155 *lid = dest_id & ((1 << lid_bits) - 1);
156 }
157
158 static void recalculate_apic_map(struct kvm *kvm)
159 {
160 struct kvm_apic_map *new, *old = NULL;
161 struct kvm_vcpu *vcpu;
162 int i;
163
164 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
165
166 mutex_lock(&kvm->arch.apic_map_lock);
167
168 if (!new)
169 goto out;
170
171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
173 u16 cid, lid;
174 u32 ldr, aid;
175
176 if (!kvm_apic_present(vcpu))
177 continue;
178
179 aid = kvm_apic_id(apic);
180 ldr = kvm_apic_get_reg(apic, APIC_LDR);
181
182 if (aid < ARRAY_SIZE(new->phys_map))
183 new->phys_map[aid] = apic;
184
185 if (apic_x2apic_mode(apic)) {
186 new->mode |= KVM_APIC_MODE_X2APIC;
187 } else if (ldr) {
188 ldr = GET_APIC_LOGICAL_ID(ldr);
189 if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
191 else
192 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
193 }
194
195 if (!kvm_apic_logical_map_valid(new))
196 continue;
197
198 apic_logical_id(new, ldr, &cid, &lid);
199
200 if (lid && cid < ARRAY_SIZE(new->logical_map))
201 new->logical_map[cid][ffs(lid) - 1] = apic;
202 }
203 out:
204 old = rcu_dereference_protected(kvm->arch.apic_map,
205 lockdep_is_held(&kvm->arch.apic_map_lock));
206 rcu_assign_pointer(kvm->arch.apic_map, new);
207 mutex_unlock(&kvm->arch.apic_map_lock);
208
209 if (old)
210 kfree_rcu(old, rcu);
211
212 kvm_make_scan_ioapic_request(kvm);
213 }
214
215 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
216 {
217 bool enabled = val & APIC_SPIV_APIC_ENABLED;
218
219 apic_set_reg(apic, APIC_SPIV, val);
220
221 if (enabled != apic->sw_enabled) {
222 apic->sw_enabled = enabled;
223 if (enabled) {
224 static_key_slow_dec_deferred(&apic_sw_disabled);
225 recalculate_apic_map(apic->vcpu->kvm);
226 } else
227 static_key_slow_inc(&apic_sw_disabled.key);
228 }
229 }
230
231 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
232 {
233 apic_set_reg(apic, APIC_ID, id << 24);
234 recalculate_apic_map(apic->vcpu->kvm);
235 }
236
237 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
238 {
239 apic_set_reg(apic, APIC_LDR, id);
240 recalculate_apic_map(apic->vcpu->kvm);
241 }
242
243 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
244 {
245 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
246
247 apic_set_reg(apic, APIC_ID, id << 24);
248 apic_set_reg(apic, APIC_LDR, ldr);
249 recalculate_apic_map(apic->vcpu->kvm);
250 }
251
252 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
253 {
254 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
255 }
256
257 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
258 {
259 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
260 }
261
262 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
263 {
264 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
265 }
266
267 static inline int apic_lvtt_period(struct kvm_lapic *apic)
268 {
269 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
270 }
271
272 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
273 {
274 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
275 }
276
277 static inline int apic_lvt_nmi_mode(u32 lvt_val)
278 {
279 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
280 }
281
282 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
283 {
284 struct kvm_lapic *apic = vcpu->arch.apic;
285 struct kvm_cpuid_entry2 *feat;
286 u32 v = APIC_VERSION;
287
288 if (!kvm_vcpu_has_lapic(vcpu))
289 return;
290
291 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
292 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
293 v |= APIC_LVR_DIRECTED_EOI;
294 apic_set_reg(apic, APIC_LVR, v);
295 }
296
297 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
298 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
299 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
300 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
301 LINT_MASK, LINT_MASK, /* LVT0-1 */
302 LVT_MASK /* LVTERR */
303 };
304
305 static int find_highest_vector(void *bitmap)
306 {
307 int vec;
308 u32 *reg;
309
310 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
311 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
312 reg = bitmap + REG_POS(vec);
313 if (*reg)
314 return fls(*reg) - 1 + vec;
315 }
316
317 return -1;
318 }
319
320 static u8 count_vectors(void *bitmap)
321 {
322 int vec;
323 u32 *reg;
324 u8 count = 0;
325
326 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
327 reg = bitmap + REG_POS(vec);
328 count += hweight32(*reg);
329 }
330
331 return count;
332 }
333
334 void __kvm_apic_update_irr(u32 *pir, void *regs)
335 {
336 u32 i, pir_val;
337
338 for (i = 0; i <= 7; i++) {
339 pir_val = xchg(&pir[i], 0);
340 if (pir_val)
341 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
342 }
343 }
344 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
345
346 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
347 {
348 struct kvm_lapic *apic = vcpu->arch.apic;
349
350 __kvm_apic_update_irr(pir, apic->regs);
351
352 kvm_make_request(KVM_REQ_EVENT, vcpu);
353 }
354 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
355
356 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
357 {
358 apic_set_vector(vec, apic->regs + APIC_IRR);
359 /*
360 * irr_pending must be true if any interrupt is pending; set it after
361 * APIC_IRR to avoid race with apic_clear_irr
362 */
363 apic->irr_pending = true;
364 }
365
366 static inline int apic_search_irr(struct kvm_lapic *apic)
367 {
368 return find_highest_vector(apic->regs + APIC_IRR);
369 }
370
371 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
372 {
373 int result;
374
375 /*
376 * Note that irr_pending is just a hint. It will be always
377 * true with virtual interrupt delivery enabled.
378 */
379 if (!apic->irr_pending)
380 return -1;
381
382 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
383 result = apic_search_irr(apic);
384 ASSERT(result == -1 || result >= 16);
385
386 return result;
387 }
388
389 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
390 {
391 struct kvm_vcpu *vcpu;
392
393 vcpu = apic->vcpu;
394
395 if (unlikely(kvm_vcpu_apic_vid_enabled(vcpu))) {
396 /* try to update RVI */
397 apic_clear_vector(vec, apic->regs + APIC_IRR);
398 kvm_make_request(KVM_REQ_EVENT, vcpu);
399 } else {
400 apic->irr_pending = false;
401 apic_clear_vector(vec, apic->regs + APIC_IRR);
402 if (apic_search_irr(apic) != -1)
403 apic->irr_pending = true;
404 }
405 }
406
407 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
408 {
409 struct kvm_vcpu *vcpu;
410
411 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
412 return;
413
414 vcpu = apic->vcpu;
415
416 /*
417 * With APIC virtualization enabled, all caching is disabled
418 * because the processor can modify ISR under the hood. Instead
419 * just set SVI.
420 */
421 if (unlikely(kvm_x86_ops->hwapic_isr_update))
422 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
423 else {
424 ++apic->isr_count;
425 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
426 /*
427 * ISR (in service register) bit is set when injecting an interrupt.
428 * The highest vector is injected. Thus the latest bit set matches
429 * the highest bit in ISR.
430 */
431 apic->highest_isr_cache = vec;
432 }
433 }
434
435 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
436 {
437 int result;
438
439 /*
440 * Note that isr_count is always 1, and highest_isr_cache
441 * is always -1, with APIC virtualization enabled.
442 */
443 if (!apic->isr_count)
444 return -1;
445 if (likely(apic->highest_isr_cache != -1))
446 return apic->highest_isr_cache;
447
448 result = find_highest_vector(apic->regs + APIC_ISR);
449 ASSERT(result == -1 || result >= 16);
450
451 return result;
452 }
453
454 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
455 {
456 struct kvm_vcpu *vcpu;
457 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
458 return;
459
460 vcpu = apic->vcpu;
461
462 /*
463 * We do get here for APIC virtualization enabled if the guest
464 * uses the Hyper-V APIC enlightenment. In this case we may need
465 * to trigger a new interrupt delivery by writing the SVI field;
466 * on the other hand isr_count and highest_isr_cache are unused
467 * and must be left alone.
468 */
469 if (unlikely(kvm_x86_ops->hwapic_isr_update))
470 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
471 apic_find_highest_isr(apic));
472 else {
473 --apic->isr_count;
474 BUG_ON(apic->isr_count < 0);
475 apic->highest_isr_cache = -1;
476 }
477 }
478
479 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
480 {
481 int highest_irr;
482
483 /* This may race with setting of irr in __apic_accept_irq() and
484 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
485 * will cause vmexit immediately and the value will be recalculated
486 * on the next vmentry.
487 */
488 if (!kvm_vcpu_has_lapic(vcpu))
489 return 0;
490 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
491
492 return highest_irr;
493 }
494
495 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
496 int vector, int level, int trig_mode,
497 unsigned long *dest_map);
498
499 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
500 unsigned long *dest_map)
501 {
502 struct kvm_lapic *apic = vcpu->arch.apic;
503
504 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
505 irq->level, irq->trig_mode, dest_map);
506 }
507
508 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
509 {
510
511 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
512 sizeof(val));
513 }
514
515 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
516 {
517
518 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
519 sizeof(*val));
520 }
521
522 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
523 {
524 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
525 }
526
527 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
528 {
529 u8 val;
530 if (pv_eoi_get_user(vcpu, &val) < 0)
531 apic_debug("Can't read EOI MSR value: 0x%llx\n",
532 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
533 return val & 0x1;
534 }
535
536 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
537 {
538 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
539 apic_debug("Can't set EOI MSR value: 0x%llx\n",
540 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
541 return;
542 }
543 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
544 }
545
546 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
547 {
548 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
549 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
550 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
551 return;
552 }
553 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
554 }
555
556 static void apic_update_ppr(struct kvm_lapic *apic)
557 {
558 u32 tpr, isrv, ppr, old_ppr;
559 int isr;
560
561 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
562 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
563 isr = apic_find_highest_isr(apic);
564 isrv = (isr != -1) ? isr : 0;
565
566 if ((tpr & 0xf0) >= (isrv & 0xf0))
567 ppr = tpr & 0xff;
568 else
569 ppr = isrv & 0xf0;
570
571 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
572 apic, ppr, isr, isrv);
573
574 if (old_ppr != ppr) {
575 apic_set_reg(apic, APIC_PROCPRI, ppr);
576 if (ppr < old_ppr)
577 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
578 }
579 }
580
581 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
582 {
583 apic_set_reg(apic, APIC_TASKPRI, tpr);
584 apic_update_ppr(apic);
585 }
586
587 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
588 {
589 if (apic_x2apic_mode(apic))
590 return mda == X2APIC_BROADCAST;
591
592 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
593 }
594
595 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
596 {
597 if (kvm_apic_broadcast(apic, mda))
598 return true;
599
600 if (apic_x2apic_mode(apic))
601 return mda == kvm_apic_id(apic);
602
603 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
604 }
605
606 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
607 {
608 u32 logical_id;
609
610 if (kvm_apic_broadcast(apic, mda))
611 return true;
612
613 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
614
615 if (apic_x2apic_mode(apic))
616 return ((logical_id >> 16) == (mda >> 16))
617 && (logical_id & mda & 0xffff) != 0;
618
619 logical_id = GET_APIC_LOGICAL_ID(logical_id);
620 mda = GET_APIC_DEST_FIELD(mda);
621
622 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
623 case APIC_DFR_FLAT:
624 return (logical_id & mda) != 0;
625 case APIC_DFR_CLUSTER:
626 return ((logical_id >> 4) == (mda >> 4))
627 && (logical_id & mda & 0xf) != 0;
628 default:
629 apic_debug("Bad DFR vcpu %d: %08x\n",
630 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
631 return false;
632 }
633 }
634
635 /* KVM APIC implementation has two quirks
636 * - dest always begins at 0 while xAPIC MDA has offset 24,
637 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
638 */
639 static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
640 struct kvm_lapic *target)
641 {
642 bool ipi = source != NULL;
643 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
644
645 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
646 return X2APIC_BROADCAST;
647
648 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
649 }
650
651 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
652 int short_hand, unsigned int dest, int dest_mode)
653 {
654 struct kvm_lapic *target = vcpu->arch.apic;
655 u32 mda = kvm_apic_mda(dest, source, target);
656
657 apic_debug("target %p, source %p, dest 0x%x, "
658 "dest_mode 0x%x, short_hand 0x%x\n",
659 target, source, dest, dest_mode, short_hand);
660
661 ASSERT(target);
662 switch (short_hand) {
663 case APIC_DEST_NOSHORT:
664 if (dest_mode == APIC_DEST_PHYSICAL)
665 return kvm_apic_match_physical_addr(target, mda);
666 else
667 return kvm_apic_match_logical_addr(target, mda);
668 case APIC_DEST_SELF:
669 return target == source;
670 case APIC_DEST_ALLINC:
671 return true;
672 case APIC_DEST_ALLBUT:
673 return target != source;
674 default:
675 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
676 short_hand);
677 return false;
678 }
679 }
680
681 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
682 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
683 {
684 struct kvm_apic_map *map;
685 unsigned long bitmap = 1;
686 struct kvm_lapic **dst;
687 int i;
688 bool ret, x2apic_ipi;
689
690 *r = -1;
691
692 if (irq->shorthand == APIC_DEST_SELF) {
693 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
694 return true;
695 }
696
697 if (irq->shorthand)
698 return false;
699
700 x2apic_ipi = src && apic_x2apic_mode(src);
701 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
702 return false;
703
704 ret = true;
705 rcu_read_lock();
706 map = rcu_dereference(kvm->arch.apic_map);
707
708 if (!map) {
709 ret = false;
710 goto out;
711 }
712
713 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
714 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
715 goto out;
716
717 dst = &map->phys_map[irq->dest_id];
718 } else {
719 u16 cid;
720
721 if (!kvm_apic_logical_map_valid(map)) {
722 ret = false;
723 goto out;
724 }
725
726 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
727
728 if (cid >= ARRAY_SIZE(map->logical_map))
729 goto out;
730
731 dst = map->logical_map[cid];
732
733 if (kvm_lowest_prio_delivery(irq)) {
734 int l = -1;
735 for_each_set_bit(i, &bitmap, 16) {
736 if (!dst[i])
737 continue;
738 if (l < 0)
739 l = i;
740 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
741 l = i;
742 }
743
744 bitmap = (l >= 0) ? 1 << l : 0;
745 }
746 }
747
748 for_each_set_bit(i, &bitmap, 16) {
749 if (!dst[i])
750 continue;
751 if (*r < 0)
752 *r = 0;
753 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
754 }
755 out:
756 rcu_read_unlock();
757 return ret;
758 }
759
760 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
761 struct kvm_vcpu **dest_vcpu)
762 {
763 struct kvm_apic_map *map;
764 bool ret = false;
765 struct kvm_lapic *dst = NULL;
766
767 if (irq->shorthand)
768 return false;
769
770 rcu_read_lock();
771 map = rcu_dereference(kvm->arch.apic_map);
772
773 if (!map)
774 goto out;
775
776 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
777 if (irq->dest_id == 0xFF)
778 goto out;
779
780 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
781 goto out;
782
783 dst = map->phys_map[irq->dest_id];
784 if (dst && kvm_apic_present(dst->vcpu))
785 *dest_vcpu = dst->vcpu;
786 else
787 goto out;
788 } else {
789 u16 cid;
790 unsigned long bitmap = 1;
791 int i, r = 0;
792
793 if (!kvm_apic_logical_map_valid(map))
794 goto out;
795
796 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
797
798 if (cid >= ARRAY_SIZE(map->logical_map))
799 goto out;
800
801 for_each_set_bit(i, &bitmap, 16) {
802 dst = map->logical_map[cid][i];
803 if (++r == 2)
804 goto out;
805 }
806
807 if (dst && kvm_apic_present(dst->vcpu))
808 *dest_vcpu = dst->vcpu;
809 else
810 goto out;
811 }
812
813 ret = true;
814 out:
815 rcu_read_unlock();
816 return ret;
817 }
818
819 /*
820 * Add a pending IRQ into lapic.
821 * Return 1 if successfully added and 0 if discarded.
822 */
823 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
824 int vector, int level, int trig_mode,
825 unsigned long *dest_map)
826 {
827 int result = 0;
828 struct kvm_vcpu *vcpu = apic->vcpu;
829
830 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
831 trig_mode, vector);
832 switch (delivery_mode) {
833 case APIC_DM_LOWEST:
834 vcpu->arch.apic_arb_prio++;
835 case APIC_DM_FIXED:
836 if (unlikely(trig_mode && !level))
837 break;
838
839 /* FIXME add logic for vcpu on reset */
840 if (unlikely(!apic_enabled(apic)))
841 break;
842
843 result = 1;
844
845 if (dest_map)
846 __set_bit(vcpu->vcpu_id, dest_map);
847
848 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
849 if (trig_mode)
850 apic_set_vector(vector, apic->regs + APIC_TMR);
851 else
852 apic_clear_vector(vector, apic->regs + APIC_TMR);
853 }
854
855 if (kvm_x86_ops->deliver_posted_interrupt)
856 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
857 else {
858 apic_set_irr(vector, apic);
859
860 kvm_make_request(KVM_REQ_EVENT, vcpu);
861 kvm_vcpu_kick(vcpu);
862 }
863 break;
864
865 case APIC_DM_REMRD:
866 result = 1;
867 vcpu->arch.pv.pv_unhalted = 1;
868 kvm_make_request(KVM_REQ_EVENT, vcpu);
869 kvm_vcpu_kick(vcpu);
870 break;
871
872 case APIC_DM_SMI:
873 result = 1;
874 kvm_make_request(KVM_REQ_SMI, vcpu);
875 kvm_vcpu_kick(vcpu);
876 break;
877
878 case APIC_DM_NMI:
879 result = 1;
880 kvm_inject_nmi(vcpu);
881 kvm_vcpu_kick(vcpu);
882 break;
883
884 case APIC_DM_INIT:
885 if (!trig_mode || level) {
886 result = 1;
887 /* assumes that there are only KVM_APIC_INIT/SIPI */
888 apic->pending_events = (1UL << KVM_APIC_INIT);
889 /* make sure pending_events is visible before sending
890 * the request */
891 smp_wmb();
892 kvm_make_request(KVM_REQ_EVENT, vcpu);
893 kvm_vcpu_kick(vcpu);
894 } else {
895 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
896 vcpu->vcpu_id);
897 }
898 break;
899
900 case APIC_DM_STARTUP:
901 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
902 vcpu->vcpu_id, vector);
903 result = 1;
904 apic->sipi_vector = vector;
905 /* make sure sipi_vector is visible for the receiver */
906 smp_wmb();
907 set_bit(KVM_APIC_SIPI, &apic->pending_events);
908 kvm_make_request(KVM_REQ_EVENT, vcpu);
909 kvm_vcpu_kick(vcpu);
910 break;
911
912 case APIC_DM_EXTINT:
913 /*
914 * Should only be called by kvm_apic_local_deliver() with LVT0,
915 * before NMI watchdog was enabled. Already handled by
916 * kvm_apic_accept_pic_intr().
917 */
918 break;
919
920 default:
921 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
922 delivery_mode);
923 break;
924 }
925 return result;
926 }
927
928 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
929 {
930 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
931 }
932
933 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
934 {
935 return test_bit(vector, (ulong *)apic->vcpu->arch.eoi_exit_bitmap);
936 }
937
938 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
939 {
940 int trigger_mode;
941
942 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
943 if (!kvm_ioapic_handles_vector(apic, vector))
944 return;
945
946 /* Request a KVM exit to inform the userspace IOAPIC. */
947 if (irqchip_split(apic->vcpu->kvm)) {
948 apic->vcpu->arch.pending_ioapic_eoi = vector;
949 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
950 return;
951 }
952
953 if (apic_test_vector(vector, apic->regs + APIC_TMR))
954 trigger_mode = IOAPIC_LEVEL_TRIG;
955 else
956 trigger_mode = IOAPIC_EDGE_TRIG;
957
958 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
959 }
960
961 static int apic_set_eoi(struct kvm_lapic *apic)
962 {
963 int vector = apic_find_highest_isr(apic);
964
965 trace_kvm_eoi(apic, vector);
966
967 /*
968 * Not every write EOI will has corresponding ISR,
969 * one example is when Kernel check timer on setup_IO_APIC
970 */
971 if (vector == -1)
972 return vector;
973
974 apic_clear_isr(vector, apic);
975 apic_update_ppr(apic);
976
977 kvm_ioapic_send_eoi(apic, vector);
978 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
979 return vector;
980 }
981
982 /*
983 * this interface assumes a trap-like exit, which has already finished
984 * desired side effect including vISR and vPPR update.
985 */
986 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
987 {
988 struct kvm_lapic *apic = vcpu->arch.apic;
989
990 trace_kvm_eoi(apic, vector);
991
992 kvm_ioapic_send_eoi(apic, vector);
993 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
994 }
995 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
996
997 static void apic_send_ipi(struct kvm_lapic *apic)
998 {
999 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
1000 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
1001 struct kvm_lapic_irq irq;
1002
1003 irq.vector = icr_low & APIC_VECTOR_MASK;
1004 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1005 irq.dest_mode = icr_low & APIC_DEST_MASK;
1006 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1007 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1008 irq.shorthand = icr_low & APIC_SHORT_MASK;
1009 irq.msi_redir_hint = false;
1010 if (apic_x2apic_mode(apic))
1011 irq.dest_id = icr_high;
1012 else
1013 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1014
1015 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1016
1017 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1018 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1019 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1020 "msi_redir_hint 0x%x\n",
1021 icr_high, icr_low, irq.shorthand, irq.dest_id,
1022 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1023 irq.vector, irq.msi_redir_hint);
1024
1025 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1026 }
1027
1028 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1029 {
1030 ktime_t remaining;
1031 s64 ns;
1032 u32 tmcct;
1033
1034 ASSERT(apic != NULL);
1035
1036 /* if initial count is 0, current count should also be 0 */
1037 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
1038 apic->lapic_timer.period == 0)
1039 return 0;
1040
1041 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
1042 if (ktime_to_ns(remaining) < 0)
1043 remaining = ktime_set(0, 0);
1044
1045 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1046 tmcct = div64_u64(ns,
1047 (APIC_BUS_CYCLE_NS * apic->divide_count));
1048
1049 return tmcct;
1050 }
1051
1052 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1053 {
1054 struct kvm_vcpu *vcpu = apic->vcpu;
1055 struct kvm_run *run = vcpu->run;
1056
1057 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1058 run->tpr_access.rip = kvm_rip_read(vcpu);
1059 run->tpr_access.is_write = write;
1060 }
1061
1062 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1063 {
1064 if (apic->vcpu->arch.tpr_access_reporting)
1065 __report_tpr_access(apic, write);
1066 }
1067
1068 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1069 {
1070 u32 val = 0;
1071
1072 if (offset >= LAPIC_MMIO_LENGTH)
1073 return 0;
1074
1075 switch (offset) {
1076 case APIC_ID:
1077 if (apic_x2apic_mode(apic))
1078 val = kvm_apic_id(apic);
1079 else
1080 val = kvm_apic_id(apic) << 24;
1081 break;
1082 case APIC_ARBPRI:
1083 apic_debug("Access APIC ARBPRI register which is for P6\n");
1084 break;
1085
1086 case APIC_TMCCT: /* Timer CCR */
1087 if (apic_lvtt_tscdeadline(apic))
1088 return 0;
1089
1090 val = apic_get_tmcct(apic);
1091 break;
1092 case APIC_PROCPRI:
1093 apic_update_ppr(apic);
1094 val = kvm_apic_get_reg(apic, offset);
1095 break;
1096 case APIC_TASKPRI:
1097 report_tpr_access(apic, false);
1098 /* fall thru */
1099 default:
1100 val = kvm_apic_get_reg(apic, offset);
1101 break;
1102 }
1103
1104 return val;
1105 }
1106
1107 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1108 {
1109 return container_of(dev, struct kvm_lapic, dev);
1110 }
1111
1112 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1113 void *data)
1114 {
1115 unsigned char alignment = offset & 0xf;
1116 u32 result;
1117 /* this bitmask has a bit cleared for each reserved register */
1118 static const u64 rmask = 0x43ff01ffffffe70cULL;
1119
1120 if ((alignment + len) > 4) {
1121 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1122 offset, len);
1123 return 1;
1124 }
1125
1126 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1127 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1128 offset);
1129 return 1;
1130 }
1131
1132 result = __apic_read(apic, offset & ~0xf);
1133
1134 trace_kvm_apic_read(offset, result);
1135
1136 switch (len) {
1137 case 1:
1138 case 2:
1139 case 4:
1140 memcpy(data, (char *)&result + alignment, len);
1141 break;
1142 default:
1143 printk(KERN_ERR "Local APIC read with len = %x, "
1144 "should be 1,2, or 4 instead\n", len);
1145 break;
1146 }
1147 return 0;
1148 }
1149
1150 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1151 {
1152 return kvm_apic_hw_enabled(apic) &&
1153 addr >= apic->base_address &&
1154 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1155 }
1156
1157 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1158 gpa_t address, int len, void *data)
1159 {
1160 struct kvm_lapic *apic = to_lapic(this);
1161 u32 offset = address - apic->base_address;
1162
1163 if (!apic_mmio_in_range(apic, address))
1164 return -EOPNOTSUPP;
1165
1166 apic_reg_read(apic, offset, len, data);
1167
1168 return 0;
1169 }
1170
1171 static void update_divide_count(struct kvm_lapic *apic)
1172 {
1173 u32 tmp1, tmp2, tdcr;
1174
1175 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1176 tmp1 = tdcr & 0xf;
1177 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1178 apic->divide_count = 0x1 << (tmp2 & 0x7);
1179
1180 apic_debug("timer divide count is 0x%x\n",
1181 apic->divide_count);
1182 }
1183
1184 static void apic_update_lvtt(struct kvm_lapic *apic)
1185 {
1186 u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
1187 apic->lapic_timer.timer_mode_mask;
1188
1189 if (apic->lapic_timer.timer_mode != timer_mode) {
1190 apic->lapic_timer.timer_mode = timer_mode;
1191 hrtimer_cancel(&apic->lapic_timer.timer);
1192 }
1193 }
1194
1195 static void apic_timer_expired(struct kvm_lapic *apic)
1196 {
1197 struct kvm_vcpu *vcpu = apic->vcpu;
1198 wait_queue_head_t *q = &vcpu->wq;
1199 struct kvm_timer *ktimer = &apic->lapic_timer;
1200
1201 if (atomic_read(&apic->lapic_timer.pending))
1202 return;
1203
1204 atomic_inc(&apic->lapic_timer.pending);
1205 kvm_set_pending_timer(vcpu);
1206
1207 if (waitqueue_active(q))
1208 wake_up_interruptible(q);
1209
1210 if (apic_lvtt_tscdeadline(apic))
1211 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1212 }
1213
1214 /*
1215 * On APICv, this test will cause a busy wait
1216 * during a higher-priority task.
1217 */
1218
1219 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1220 {
1221 struct kvm_lapic *apic = vcpu->arch.apic;
1222 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1223
1224 if (kvm_apic_hw_enabled(apic)) {
1225 int vec = reg & APIC_VECTOR_MASK;
1226 void *bitmap = apic->regs + APIC_ISR;
1227
1228 if (kvm_x86_ops->deliver_posted_interrupt)
1229 bitmap = apic->regs + APIC_IRR;
1230
1231 if (apic_test_vector(vec, bitmap))
1232 return true;
1233 }
1234 return false;
1235 }
1236
1237 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1238 {
1239 struct kvm_lapic *apic = vcpu->arch.apic;
1240 u64 guest_tsc, tsc_deadline;
1241
1242 if (!kvm_vcpu_has_lapic(vcpu))
1243 return;
1244
1245 if (apic->lapic_timer.expired_tscdeadline == 0)
1246 return;
1247
1248 if (!lapic_timer_int_injected(vcpu))
1249 return;
1250
1251 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1252 apic->lapic_timer.expired_tscdeadline = 0;
1253 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1254 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1255
1256 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1257 if (guest_tsc < tsc_deadline)
1258 __delay(tsc_deadline - guest_tsc);
1259 }
1260
1261 static void start_apic_timer(struct kvm_lapic *apic)
1262 {
1263 ktime_t now;
1264
1265 atomic_set(&apic->lapic_timer.pending, 0);
1266
1267 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1268 /* lapic timer in oneshot or periodic mode */
1269 now = apic->lapic_timer.timer.base->get_time();
1270 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1271 * APIC_BUS_CYCLE_NS * apic->divide_count;
1272
1273 if (!apic->lapic_timer.period)
1274 return;
1275 /*
1276 * Do not allow the guest to program periodic timers with small
1277 * interval, since the hrtimers are not throttled by the host
1278 * scheduler.
1279 */
1280 if (apic_lvtt_period(apic)) {
1281 s64 min_period = min_timer_period_us * 1000LL;
1282
1283 if (apic->lapic_timer.period < min_period) {
1284 pr_info_ratelimited(
1285 "kvm: vcpu %i: requested %lld ns "
1286 "lapic timer period limited to %lld ns\n",
1287 apic->vcpu->vcpu_id,
1288 apic->lapic_timer.period, min_period);
1289 apic->lapic_timer.period = min_period;
1290 }
1291 }
1292
1293 hrtimer_start(&apic->lapic_timer.timer,
1294 ktime_add_ns(now, apic->lapic_timer.period),
1295 HRTIMER_MODE_ABS);
1296
1297 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1298 PRIx64 ", "
1299 "timer initial count 0x%x, period %lldns, "
1300 "expire @ 0x%016" PRIx64 ".\n", __func__,
1301 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1302 kvm_apic_get_reg(apic, APIC_TMICT),
1303 apic->lapic_timer.period,
1304 ktime_to_ns(ktime_add_ns(now,
1305 apic->lapic_timer.period)));
1306 } else if (apic_lvtt_tscdeadline(apic)) {
1307 /* lapic timer in tsc deadline mode */
1308 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1309 u64 ns = 0;
1310 ktime_t expire;
1311 struct kvm_vcpu *vcpu = apic->vcpu;
1312 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1313 unsigned long flags;
1314
1315 if (unlikely(!tscdeadline || !this_tsc_khz))
1316 return;
1317
1318 local_irq_save(flags);
1319
1320 now = apic->lapic_timer.timer.base->get_time();
1321 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1322 if (likely(tscdeadline > guest_tsc)) {
1323 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1324 do_div(ns, this_tsc_khz);
1325 expire = ktime_add_ns(now, ns);
1326 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1327 hrtimer_start(&apic->lapic_timer.timer,
1328 expire, HRTIMER_MODE_ABS);
1329 } else
1330 apic_timer_expired(apic);
1331
1332 local_irq_restore(flags);
1333 }
1334 }
1335
1336 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1337 {
1338 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1339
1340 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1341 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1342 if (lvt0_in_nmi_mode) {
1343 apic_debug("Receive NMI setting on APIC_LVT0 "
1344 "for cpu %d\n", apic->vcpu->vcpu_id);
1345 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1346 } else
1347 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1348 }
1349 }
1350
1351 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1352 {
1353 int ret = 0;
1354
1355 trace_kvm_apic_write(reg, val);
1356
1357 switch (reg) {
1358 case APIC_ID: /* Local APIC ID */
1359 if (!apic_x2apic_mode(apic))
1360 kvm_apic_set_id(apic, val >> 24);
1361 else
1362 ret = 1;
1363 break;
1364
1365 case APIC_TASKPRI:
1366 report_tpr_access(apic, true);
1367 apic_set_tpr(apic, val & 0xff);
1368 break;
1369
1370 case APIC_EOI:
1371 apic_set_eoi(apic);
1372 break;
1373
1374 case APIC_LDR:
1375 if (!apic_x2apic_mode(apic))
1376 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1377 else
1378 ret = 1;
1379 break;
1380
1381 case APIC_DFR:
1382 if (!apic_x2apic_mode(apic)) {
1383 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1384 recalculate_apic_map(apic->vcpu->kvm);
1385 } else
1386 ret = 1;
1387 break;
1388
1389 case APIC_SPIV: {
1390 u32 mask = 0x3ff;
1391 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1392 mask |= APIC_SPIV_DIRECTED_EOI;
1393 apic_set_spiv(apic, val & mask);
1394 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1395 int i;
1396 u32 lvt_val;
1397
1398 for (i = 0; i < APIC_LVT_NUM; i++) {
1399 lvt_val = kvm_apic_get_reg(apic,
1400 APIC_LVTT + 0x10 * i);
1401 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1402 lvt_val | APIC_LVT_MASKED);
1403 }
1404 apic_update_lvtt(apic);
1405 atomic_set(&apic->lapic_timer.pending, 0);
1406
1407 }
1408 break;
1409 }
1410 case APIC_ICR:
1411 /* No delay here, so we always clear the pending bit */
1412 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1413 apic_send_ipi(apic);
1414 break;
1415
1416 case APIC_ICR2:
1417 if (!apic_x2apic_mode(apic))
1418 val &= 0xff000000;
1419 apic_set_reg(apic, APIC_ICR2, val);
1420 break;
1421
1422 case APIC_LVT0:
1423 apic_manage_nmi_watchdog(apic, val);
1424 case APIC_LVTTHMR:
1425 case APIC_LVTPC:
1426 case APIC_LVT1:
1427 case APIC_LVTERR:
1428 /* TODO: Check vector */
1429 if (!kvm_apic_sw_enabled(apic))
1430 val |= APIC_LVT_MASKED;
1431
1432 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1433 apic_set_reg(apic, reg, val);
1434
1435 break;
1436
1437 case APIC_LVTT:
1438 if (!kvm_apic_sw_enabled(apic))
1439 val |= APIC_LVT_MASKED;
1440 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1441 apic_set_reg(apic, APIC_LVTT, val);
1442 apic_update_lvtt(apic);
1443 break;
1444
1445 case APIC_TMICT:
1446 if (apic_lvtt_tscdeadline(apic))
1447 break;
1448
1449 hrtimer_cancel(&apic->lapic_timer.timer);
1450 apic_set_reg(apic, APIC_TMICT, val);
1451 start_apic_timer(apic);
1452 break;
1453
1454 case APIC_TDCR:
1455 if (val & 4)
1456 apic_debug("KVM_WRITE:TDCR %x\n", val);
1457 apic_set_reg(apic, APIC_TDCR, val);
1458 update_divide_count(apic);
1459 break;
1460
1461 case APIC_ESR:
1462 if (apic_x2apic_mode(apic) && val != 0) {
1463 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1464 ret = 1;
1465 }
1466 break;
1467
1468 case APIC_SELF_IPI:
1469 if (apic_x2apic_mode(apic)) {
1470 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1471 } else
1472 ret = 1;
1473 break;
1474 default:
1475 ret = 1;
1476 break;
1477 }
1478 if (ret)
1479 apic_debug("Local APIC Write to read-only register %x\n", reg);
1480 return ret;
1481 }
1482
1483 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1484 gpa_t address, int len, const void *data)
1485 {
1486 struct kvm_lapic *apic = to_lapic(this);
1487 unsigned int offset = address - apic->base_address;
1488 u32 val;
1489
1490 if (!apic_mmio_in_range(apic, address))
1491 return -EOPNOTSUPP;
1492
1493 /*
1494 * APIC register must be aligned on 128-bits boundary.
1495 * 32/64/128 bits registers must be accessed thru 32 bits.
1496 * Refer SDM 8.4.1
1497 */
1498 if (len != 4 || (offset & 0xf)) {
1499 /* Don't shout loud, $infamous_os would cause only noise. */
1500 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1501 return 0;
1502 }
1503
1504 val = *(u32*)data;
1505
1506 /* too common printing */
1507 if (offset != APIC_EOI)
1508 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1509 "0x%x\n", __func__, offset, len, val);
1510
1511 apic_reg_write(apic, offset & 0xff0, val);
1512
1513 return 0;
1514 }
1515
1516 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1517 {
1518 if (kvm_vcpu_has_lapic(vcpu))
1519 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1520 }
1521 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1522
1523 /* emulate APIC access in a trap manner */
1524 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1525 {
1526 u32 val = 0;
1527
1528 /* hw has done the conditional check and inst decode */
1529 offset &= 0xff0;
1530
1531 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1532
1533 /* TODO: optimize to just emulate side effect w/o one more write */
1534 apic_reg_write(vcpu->arch.apic, offset, val);
1535 }
1536 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1537
1538 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1539 {
1540 struct kvm_lapic *apic = vcpu->arch.apic;
1541
1542 if (!vcpu->arch.apic)
1543 return;
1544
1545 hrtimer_cancel(&apic->lapic_timer.timer);
1546
1547 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1548 static_key_slow_dec_deferred(&apic_hw_disabled);
1549
1550 if (!apic->sw_enabled)
1551 static_key_slow_dec_deferred(&apic_sw_disabled);
1552
1553 if (apic->regs)
1554 free_page((unsigned long)apic->regs);
1555
1556 kfree(apic);
1557 }
1558
1559 /*
1560 *----------------------------------------------------------------------
1561 * LAPIC interface
1562 *----------------------------------------------------------------------
1563 */
1564
1565 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1566 {
1567 struct kvm_lapic *apic = vcpu->arch.apic;
1568
1569 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1570 apic_lvtt_period(apic))
1571 return 0;
1572
1573 return apic->lapic_timer.tscdeadline;
1574 }
1575
1576 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1577 {
1578 struct kvm_lapic *apic = vcpu->arch.apic;
1579
1580 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1581 apic_lvtt_period(apic))
1582 return;
1583
1584 hrtimer_cancel(&apic->lapic_timer.timer);
1585 apic->lapic_timer.tscdeadline = data;
1586 start_apic_timer(apic);
1587 }
1588
1589 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1590 {
1591 struct kvm_lapic *apic = vcpu->arch.apic;
1592
1593 if (!kvm_vcpu_has_lapic(vcpu))
1594 return;
1595
1596 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1597 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1598 }
1599
1600 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1601 {
1602 u64 tpr;
1603
1604 if (!kvm_vcpu_has_lapic(vcpu))
1605 return 0;
1606
1607 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1608
1609 return (tpr & 0xf0) >> 4;
1610 }
1611
1612 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1613 {
1614 u64 old_value = vcpu->arch.apic_base;
1615 struct kvm_lapic *apic = vcpu->arch.apic;
1616
1617 if (!apic) {
1618 value |= MSR_IA32_APICBASE_BSP;
1619 vcpu->arch.apic_base = value;
1620 return;
1621 }
1622
1623 vcpu->arch.apic_base = value;
1624
1625 /* update jump label if enable bit changes */
1626 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1627 if (value & MSR_IA32_APICBASE_ENABLE)
1628 static_key_slow_dec_deferred(&apic_hw_disabled);
1629 else
1630 static_key_slow_inc(&apic_hw_disabled.key);
1631 recalculate_apic_map(vcpu->kvm);
1632 }
1633
1634 if ((old_value ^ value) & X2APIC_ENABLE) {
1635 if (value & X2APIC_ENABLE) {
1636 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1637 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1638 } else
1639 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1640 }
1641
1642 apic->base_address = apic->vcpu->arch.apic_base &
1643 MSR_IA32_APICBASE_BASE;
1644
1645 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1646 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1647 pr_warn_once("APIC base relocation is unsupported by KVM");
1648
1649 /* with FSB delivery interrupt, we can restart APIC functionality */
1650 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1651 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1652
1653 }
1654
1655 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1656 {
1657 struct kvm_lapic *apic;
1658 int i;
1659
1660 apic_debug("%s\n", __func__);
1661
1662 ASSERT(vcpu);
1663 apic = vcpu->arch.apic;
1664 ASSERT(apic != NULL);
1665
1666 /* Stop the timer in case it's a reset to an active apic */
1667 hrtimer_cancel(&apic->lapic_timer.timer);
1668
1669 if (!init_event)
1670 kvm_apic_set_id(apic, vcpu->vcpu_id);
1671 kvm_apic_set_version(apic->vcpu);
1672
1673 for (i = 0; i < APIC_LVT_NUM; i++)
1674 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1675 apic_update_lvtt(apic);
1676 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1677 apic_set_reg(apic, APIC_LVT0,
1678 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1679 apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
1680
1681 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1682 apic_set_spiv(apic, 0xff);
1683 apic_set_reg(apic, APIC_TASKPRI, 0);
1684 if (!apic_x2apic_mode(apic))
1685 kvm_apic_set_ldr(apic, 0);
1686 apic_set_reg(apic, APIC_ESR, 0);
1687 apic_set_reg(apic, APIC_ICR, 0);
1688 apic_set_reg(apic, APIC_ICR2, 0);
1689 apic_set_reg(apic, APIC_TDCR, 0);
1690 apic_set_reg(apic, APIC_TMICT, 0);
1691 for (i = 0; i < 8; i++) {
1692 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1693 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1694 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1695 }
1696 apic->irr_pending = kvm_vcpu_apic_vid_enabled(vcpu);
1697 apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
1698 apic->highest_isr_cache = -1;
1699 update_divide_count(apic);
1700 atomic_set(&apic->lapic_timer.pending, 0);
1701 if (kvm_vcpu_is_bsp(vcpu))
1702 kvm_lapic_set_base(vcpu,
1703 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1704 vcpu->arch.pv_eoi.msr_val = 0;
1705 apic_update_ppr(apic);
1706
1707 vcpu->arch.apic_arb_prio = 0;
1708 vcpu->arch.apic_attention = 0;
1709
1710 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1711 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1712 vcpu, kvm_apic_id(apic),
1713 vcpu->arch.apic_base, apic->base_address);
1714 }
1715
1716 /*
1717 *----------------------------------------------------------------------
1718 * timer interface
1719 *----------------------------------------------------------------------
1720 */
1721
1722 static bool lapic_is_periodic(struct kvm_lapic *apic)
1723 {
1724 return apic_lvtt_period(apic);
1725 }
1726
1727 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1728 {
1729 struct kvm_lapic *apic = vcpu->arch.apic;
1730
1731 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1732 apic_lvt_enabled(apic, APIC_LVTT))
1733 return atomic_read(&apic->lapic_timer.pending);
1734
1735 return 0;
1736 }
1737
1738 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1739 {
1740 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1741 int vector, mode, trig_mode;
1742
1743 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1744 vector = reg & APIC_VECTOR_MASK;
1745 mode = reg & APIC_MODE_MASK;
1746 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1747 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1748 NULL);
1749 }
1750 return 0;
1751 }
1752
1753 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1754 {
1755 struct kvm_lapic *apic = vcpu->arch.apic;
1756
1757 if (apic)
1758 kvm_apic_local_deliver(apic, APIC_LVT0);
1759 }
1760
1761 static const struct kvm_io_device_ops apic_mmio_ops = {
1762 .read = apic_mmio_read,
1763 .write = apic_mmio_write,
1764 };
1765
1766 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1767 {
1768 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1769 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1770
1771 apic_timer_expired(apic);
1772
1773 if (lapic_is_periodic(apic)) {
1774 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1775 return HRTIMER_RESTART;
1776 } else
1777 return HRTIMER_NORESTART;
1778 }
1779
1780 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1781 {
1782 struct kvm_lapic *apic;
1783
1784 ASSERT(vcpu != NULL);
1785 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1786
1787 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1788 if (!apic)
1789 goto nomem;
1790
1791 vcpu->arch.apic = apic;
1792
1793 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1794 if (!apic->regs) {
1795 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1796 vcpu->vcpu_id);
1797 goto nomem_free_apic;
1798 }
1799 apic->vcpu = vcpu;
1800
1801 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1802 HRTIMER_MODE_ABS);
1803 apic->lapic_timer.timer.function = apic_timer_fn;
1804
1805 /*
1806 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1807 * thinking that APIC satet has changed.
1808 */
1809 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1810 kvm_lapic_set_base(vcpu,
1811 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1812
1813 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1814 kvm_lapic_reset(vcpu, false);
1815 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1816
1817 return 0;
1818 nomem_free_apic:
1819 kfree(apic);
1820 nomem:
1821 return -ENOMEM;
1822 }
1823
1824 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1825 {
1826 struct kvm_lapic *apic = vcpu->arch.apic;
1827 int highest_irr;
1828
1829 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1830 return -1;
1831
1832 apic_update_ppr(apic);
1833 highest_irr = apic_find_highest_irr(apic);
1834 if ((highest_irr == -1) ||
1835 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1836 return -1;
1837 return highest_irr;
1838 }
1839
1840 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1841 {
1842 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1843 int r = 0;
1844
1845 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1846 r = 1;
1847 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1848 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1849 r = 1;
1850 return r;
1851 }
1852
1853 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1854 {
1855 struct kvm_lapic *apic = vcpu->arch.apic;
1856
1857 if (!kvm_vcpu_has_lapic(vcpu))
1858 return;
1859
1860 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1861 kvm_apic_local_deliver(apic, APIC_LVTT);
1862 if (apic_lvtt_tscdeadline(apic))
1863 apic->lapic_timer.tscdeadline = 0;
1864 atomic_set(&apic->lapic_timer.pending, 0);
1865 }
1866 }
1867
1868 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1869 {
1870 int vector = kvm_apic_has_interrupt(vcpu);
1871 struct kvm_lapic *apic = vcpu->arch.apic;
1872
1873 if (vector == -1)
1874 return -1;
1875
1876 /*
1877 * We get here even with APIC virtualization enabled, if doing
1878 * nested virtualization and L1 runs with the "acknowledge interrupt
1879 * on exit" mode. Then we cannot inject the interrupt via RVI,
1880 * because the process would deliver it through the IDT.
1881 */
1882
1883 apic_set_isr(vector, apic);
1884 apic_update_ppr(apic);
1885 apic_clear_irr(vector, apic);
1886 return vector;
1887 }
1888
1889 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1890 struct kvm_lapic_state *s)
1891 {
1892 struct kvm_lapic *apic = vcpu->arch.apic;
1893
1894 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1895 /* set SPIV separately to get count of SW disabled APICs right */
1896 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1897 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1898 /* call kvm_apic_set_id() to put apic into apic_map */
1899 kvm_apic_set_id(apic, kvm_apic_id(apic));
1900 kvm_apic_set_version(vcpu);
1901
1902 apic_update_ppr(apic);
1903 hrtimer_cancel(&apic->lapic_timer.timer);
1904 apic_update_lvtt(apic);
1905 apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
1906 update_divide_count(apic);
1907 start_apic_timer(apic);
1908 apic->irr_pending = true;
1909 apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
1910 1 : count_vectors(apic->regs + APIC_ISR);
1911 apic->highest_isr_cache = -1;
1912 if (kvm_x86_ops->hwapic_irr_update)
1913 kvm_x86_ops->hwapic_irr_update(vcpu,
1914 apic_find_highest_irr(apic));
1915 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1916 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1917 apic_find_highest_isr(apic));
1918 kvm_make_request(KVM_REQ_EVENT, vcpu);
1919 if (ioapic_in_kernel(vcpu->kvm))
1920 kvm_rtc_eoi_tracking_restore_one(vcpu);
1921
1922 vcpu->arch.apic_arb_prio = 0;
1923 }
1924
1925 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1926 {
1927 struct hrtimer *timer;
1928
1929 if (!kvm_vcpu_has_lapic(vcpu))
1930 return;
1931
1932 timer = &vcpu->arch.apic->lapic_timer.timer;
1933 if (hrtimer_cancel(timer))
1934 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1935 }
1936
1937 /*
1938 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1939 *
1940 * Detect whether guest triggered PV EOI since the
1941 * last entry. If yes, set EOI on guests's behalf.
1942 * Clear PV EOI in guest memory in any case.
1943 */
1944 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1945 struct kvm_lapic *apic)
1946 {
1947 bool pending;
1948 int vector;
1949 /*
1950 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1951 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1952 *
1953 * KVM_APIC_PV_EOI_PENDING is unset:
1954 * -> host disabled PV EOI.
1955 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1956 * -> host enabled PV EOI, guest did not execute EOI yet.
1957 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1958 * -> host enabled PV EOI, guest executed EOI.
1959 */
1960 BUG_ON(!pv_eoi_enabled(vcpu));
1961 pending = pv_eoi_get_pending(vcpu);
1962 /*
1963 * Clear pending bit in any case: it will be set again on vmentry.
1964 * While this might not be ideal from performance point of view,
1965 * this makes sure pv eoi is only enabled when we know it's safe.
1966 */
1967 pv_eoi_clr_pending(vcpu);
1968 if (pending)
1969 return;
1970 vector = apic_set_eoi(apic);
1971 trace_kvm_pv_eoi(apic, vector);
1972 }
1973
1974 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1975 {
1976 u32 data;
1977
1978 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1979 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1980
1981 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1982 return;
1983
1984 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1985 sizeof(u32)))
1986 return;
1987
1988 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1989 }
1990
1991 /*
1992 * apic_sync_pv_eoi_to_guest - called before vmentry
1993 *
1994 * Detect whether it's safe to enable PV EOI and
1995 * if yes do so.
1996 */
1997 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1998 struct kvm_lapic *apic)
1999 {
2000 if (!pv_eoi_enabled(vcpu) ||
2001 /* IRR set or many bits in ISR: could be nested. */
2002 apic->irr_pending ||
2003 /* Cache not set: could be safe but we don't bother. */
2004 apic->highest_isr_cache == -1 ||
2005 /* Need EOI to update ioapic. */
2006 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2007 /*
2008 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2009 * so we need not do anything here.
2010 */
2011 return;
2012 }
2013
2014 pv_eoi_set_pending(apic->vcpu);
2015 }
2016
2017 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2018 {
2019 u32 data, tpr;
2020 int max_irr, max_isr;
2021 struct kvm_lapic *apic = vcpu->arch.apic;
2022
2023 apic_sync_pv_eoi_to_guest(vcpu, apic);
2024
2025 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2026 return;
2027
2028 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
2029 max_irr = apic_find_highest_irr(apic);
2030 if (max_irr < 0)
2031 max_irr = 0;
2032 max_isr = apic_find_highest_isr(apic);
2033 if (max_isr < 0)
2034 max_isr = 0;
2035 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2036
2037 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2038 sizeof(u32));
2039 }
2040
2041 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2042 {
2043 if (vapic_addr) {
2044 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2045 &vcpu->arch.apic->vapic_cache,
2046 vapic_addr, sizeof(u32)))
2047 return -EINVAL;
2048 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2049 } else {
2050 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2051 }
2052
2053 vcpu->arch.apic->vapic_addr = vapic_addr;
2054 return 0;
2055 }
2056
2057 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2058 {
2059 struct kvm_lapic *apic = vcpu->arch.apic;
2060 u32 reg = (msr - APIC_BASE_MSR) << 4;
2061
2062 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2063 return 1;
2064
2065 if (reg == APIC_ICR2)
2066 return 1;
2067
2068 /* if this is ICR write vector before command */
2069 if (reg == APIC_ICR)
2070 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2071 return apic_reg_write(apic, reg, (u32)data);
2072 }
2073
2074 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2075 {
2076 struct kvm_lapic *apic = vcpu->arch.apic;
2077 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2078
2079 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2080 return 1;
2081
2082 if (reg == APIC_DFR || reg == APIC_ICR2) {
2083 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2084 reg);
2085 return 1;
2086 }
2087
2088 if (apic_reg_read(apic, reg, 4, &low))
2089 return 1;
2090 if (reg == APIC_ICR)
2091 apic_reg_read(apic, APIC_ICR2, 4, &high);
2092
2093 *data = (((u64)high) << 32) | low;
2094
2095 return 0;
2096 }
2097
2098 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2099 {
2100 struct kvm_lapic *apic = vcpu->arch.apic;
2101
2102 if (!kvm_vcpu_has_lapic(vcpu))
2103 return 1;
2104
2105 /* if this is ICR write vector before command */
2106 if (reg == APIC_ICR)
2107 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2108 return apic_reg_write(apic, reg, (u32)data);
2109 }
2110
2111 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2112 {
2113 struct kvm_lapic *apic = vcpu->arch.apic;
2114 u32 low, high = 0;
2115
2116 if (!kvm_vcpu_has_lapic(vcpu))
2117 return 1;
2118
2119 if (apic_reg_read(apic, reg, 4, &low))
2120 return 1;
2121 if (reg == APIC_ICR)
2122 apic_reg_read(apic, APIC_ICR2, 4, &high);
2123
2124 *data = (((u64)high) << 32) | low;
2125
2126 return 0;
2127 }
2128
2129 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2130 {
2131 u64 addr = data & ~KVM_MSR_ENABLED;
2132 if (!IS_ALIGNED(addr, 4))
2133 return 1;
2134
2135 vcpu->arch.pv_eoi.msr_val = data;
2136 if (!pv_eoi_enabled(vcpu))
2137 return 0;
2138 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2139 addr, sizeof(u8));
2140 }
2141
2142 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2143 {
2144 struct kvm_lapic *apic = vcpu->arch.apic;
2145 u8 sipi_vector;
2146 unsigned long pe;
2147
2148 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2149 return;
2150
2151 /*
2152 * INITs are latched while in SMM. Because an SMM CPU cannot
2153 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2154 * and delay processing of INIT until the next RSM.
2155 */
2156 if (is_smm(vcpu)) {
2157 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2158 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2159 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2160 return;
2161 }
2162
2163 pe = xchg(&apic->pending_events, 0);
2164 if (test_bit(KVM_APIC_INIT, &pe)) {
2165 kvm_lapic_reset(vcpu, true);
2166 kvm_vcpu_reset(vcpu, true);
2167 if (kvm_vcpu_is_bsp(apic->vcpu))
2168 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2169 else
2170 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2171 }
2172 if (test_bit(KVM_APIC_SIPI, &pe) &&
2173 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2174 /* evaluate pending_events before reading the vector */
2175 smp_rmb();
2176 sipi_vector = apic->sipi_vector;
2177 apic_debug("vcpu %d received sipi with vector # %x\n",
2178 vcpu->vcpu_id, sipi_vector);
2179 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2180 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2181 }
2182 }
2183
2184 void kvm_lapic_init(void)
2185 {
2186 /* do not patch jump label more than once per second */
2187 jump_label_rate_limit(&apic_hw_disabled, HZ);
2188 jump_label_rate_limit(&apic_sw_disabled, HZ);
2189 }
Linux with added FPC-III support