drivers/clk/rockchip/clk-pll.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <asm/div64.h>
  17 #include <linux/slab.h>
  18 #include <linux/io.h>
  19 #include <linux/delay.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/regmap.h>
  22 #include "clk.h"
  23
  24 #define PLL_MODE_MASK           0x3
  25 #define PLL_MODE_SLOW           0x0
  26 #define PLL_MODE_NORM           0x1
  27 #define PLL_MODE_DEEP           0x2
  28
  29 struct rockchip_clk_pll {
  30         struct clk_hw           hw;
  31
  32         struct clk_mux          pll_mux;
  33         const struct clk_ops    *pll_mux_ops;
  34
  35         struct notifier_block   clk_nb;
  36
  37         void __iomem            *reg_base;
  38         int                     lock_offset;
  39         unsigned int            lock_shift;
  40         enum rockchip_pll_type  type;
  41         u8                      flags;
  42         const struct rockchip_pll_rate_table *rate_table;
  43         unsigned int            rate_count;
  44         spinlock_t              *lock;
  45 };
  46
  47 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
  48 #define to_rockchip_clk_pll_nb(nb) \
  49                         container_of(nb, struct rockchip_clk_pll, clk_nb)
  50
  51 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
  52                             struct rockchip_clk_pll *pll, unsigned long rate)
  53 {
  54         const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;
  55         int i;
  56
  57         for (i = 0; i < pll->rate_count; i++) {
  58                 if (rate == rate_table[i].rate)
  59                         return &rate_table[i];
  60         }
  61
  62         return NULL;
  63 }
  64
  65 static long rockchip_pll_round_rate(struct clk_hw *hw,
  66                             unsigned long drate, unsigned long *prate)
  67 {
  68         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
  69         const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
  70         int i;
  71
  72         /* Assumming rate_table is in descending order */
  73         for (i = 0; i < pll->rate_count; i++) {
  74                 if (drate >= rate_table[i].rate)
  75                         return rate_table[i].rate;
  76         }
  77
  78         /* return minimum supported value */
  79         return rate_table[i - 1].rate;
  80 }
  81
  82 /*
  83  * Wait for the pll to reach the locked state.
  84  * The calling set_rate function is responsible for making sure the
  85  * grf regmap is available.
  86  */
  87 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
  88 {
  89         struct regmap *grf = rockchip_clk_get_grf();
  90         unsigned int val;
  91         int delay = 24000000, ret;
  92
  93         while (delay > 0) {
  94                 ret = regmap_read(grf, pll->lock_offset, &val);
  95                 if (ret) {
  96                         pr_err("%s: failed to read pll lock status: %d\n",
  97                                __func__, ret);
  98                         return ret;
  99                 }
 100
 101                 if (val & BIT(pll->lock_shift))
 102                         return 0;
 103                 delay--;
 104         }
 105
 106         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 107         return -ETIMEDOUT;
 108 }
 109
 110 /**
 111  * PLL used in RK3066, RK3188 and RK3288
 112  */
 113
 114 #define RK3066_PLL_RESET_DELAY(nr)      ((nr * 500) / 24 + 1)
 115
 116 #define RK3066_PLLCON(i)                (i * 0x4)
 117 #define RK3066_PLLCON0_OD_MASK          0xf
 118 #define RK3066_PLLCON0_OD_SHIFT         0
 119 #define RK3066_PLLCON0_NR_MASK          0x3f
 120 #define RK3066_PLLCON0_NR_SHIFT         8
 121 #define RK3066_PLLCON1_NF_MASK          0x1fff
 122 #define RK3066_PLLCON1_NF_SHIFT         0
 123 #define RK3066_PLLCON2_NB_MASK          0xfff
 124 #define RK3066_PLLCON2_NB_SHIFT         0
 125 #define RK3066_PLLCON3_RESET            (1 << 5)
 126 #define RK3066_PLLCON3_PWRDOWN          (1 << 1)
 127 #define RK3066_PLLCON3_BYPASS           (1 << 0)
 128
 129 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,
 130                                         struct rockchip_pll_rate_table *rate)
 131 {
 132         u32 pllcon;
 133
 134         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
 135         rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)
 136                                 & RK3066_PLLCON0_NR_MASK) + 1;
 137         rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)
 138                                 & RK3066_PLLCON0_OD_MASK) + 1;
 139
 140         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
 141         rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)
 142                                 & RK3066_PLLCON1_NF_MASK) + 1;
 143
 144         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
 145         rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)
 146                                 & RK3066_PLLCON2_NB_MASK) + 1;
 147 }
 148
 149 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
 150                                                      unsigned long prate)
 151 {
 152         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 153         struct rockchip_pll_rate_table cur;
 154         u64 rate64 = prate;
 155         u32 pllcon;
 156
 157         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
 158         if (pllcon & RK3066_PLLCON3_BYPASS) {
 159                 pr_debug("%s: pll %s is bypassed\n", __func__,
 160                         clk_hw_get_name(hw));
 161                 return prate;
 162         }
 163
 164         rockchip_rk3066_pll_get_params(pll, &cur);
 165
 166         rate64 *= cur.nf;
 167         do_div(rate64, cur.nr);
 168         do_div(rate64, cur.no);
 169
 170         return (unsigned long)rate64;
 171 }
 172
 173 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,
 174                                 const struct rockchip_pll_rate_table *rate)
 175 {
 176         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 177         struct clk_mux *pll_mux = &pll->pll_mux;
 178         struct rockchip_pll_rate_table cur;
 179         int rate_change_remuxed = 0;
 180         int cur_parent;
 181         int ret;
 182
 183         pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
 184                  __func__, rate->rate, rate->nr, rate->no, rate->nf);
 185
 186         rockchip_rk3066_pll_get_params(pll, &cur);
 187         cur.rate = 0;
 188
 189         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 190         if (cur_parent == PLL_MODE_NORM) {
 191                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 192                 rate_change_remuxed = 1;
 193         }
 194
 195         /* enter reset mode */
 196         writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
 197                pll->reg_base + RK3066_PLLCON(3));
 198
 199         /* update pll values */
 200         writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
 201                                            RK3066_PLLCON0_NR_SHIFT) |
 202                HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
 203                                            RK3066_PLLCON0_OD_SHIFT),
 204                pll->reg_base + RK3066_PLLCON(0));
 205
 206         writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
 207                                                    RK3066_PLLCON1_NF_SHIFT),
 208                        pll->reg_base + RK3066_PLLCON(1));
 209         writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
 210                                                    RK3066_PLLCON2_NB_SHIFT),
 211                        pll->reg_base + RK3066_PLLCON(2));
 212
 213         /* leave reset and wait the reset_delay */
 214         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
 215                pll->reg_base + RK3066_PLLCON(3));
 216         udelay(RK3066_PLL_RESET_DELAY(rate->nr));
 217
 218         /* wait for the pll to lock */
 219         ret = rockchip_pll_wait_lock(pll);
 220         if (ret) {
 221                 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
 222                         __func__);
 223                 rockchip_rk3066_pll_set_params(pll, &cur);
 224         }
 225
 226         if (rate_change_remuxed)
 227                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 228
 229         return ret;
 230 }
 231
 232 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 233                                         unsigned long prate)
 234 {
 235         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 236         const struct rockchip_pll_rate_table *rate;
 237         unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
 238         struct regmap *grf = rockchip_clk_get_grf();
 239
 240         if (IS_ERR(grf)) {
 241                 pr_debug("%s: grf regmap not available, aborting rate change\n",
 242                          __func__);
 243                 return PTR_ERR(grf);
 244         }
 245
 246         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 247                  __func__, clk_hw_get_name(hw), old_rate, drate, prate);
 248
 249         /* Get required rate settings from table */
 250         rate = rockchip_get_pll_settings(pll, drate);
 251         if (!rate) {
 252                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 253                         drate, clk_hw_get_name(hw));
 254                 return -EINVAL;
 255         }
 256
 257         return rockchip_rk3066_pll_set_params(pll, rate);
 258 }
 259
 260 static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
 261 {
 262         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 263
 264         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
 265                pll->reg_base + RK3066_PLLCON(3));
 266
 267         return 0;
 268 }
 269
 270 static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
 271 {
 272         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 273
 274         writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
 275                              RK3066_PLLCON3_PWRDOWN, 0),
 276                pll->reg_base + RK3066_PLLCON(3));
 277 }
 278
 279 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
 280 {
 281         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 282         u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
 283
 284         return !(pllcon & RK3066_PLLCON3_PWRDOWN);
 285 }
 286
 287 static void rockchip_rk3066_pll_init(struct clk_hw *hw)
 288 {
 289         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 290         const struct rockchip_pll_rate_table *rate;
 291         struct rockchip_pll_rate_table cur;
 292         unsigned long drate;
 293
 294         if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
 295                 return;
 296
 297         drate = clk_hw_get_rate(hw);
 298         rate = rockchip_get_pll_settings(pll, drate);
 299
 300         /* when no rate setting for the current rate, rely on clk_set_rate */
 301         if (!rate)
 302                 return;
 303
 304         rockchip_rk3066_pll_get_params(pll, &cur);
 305
 306         pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
 307                  __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,
 308                  rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
 309         if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
 310                                                      || rate->nb != cur.nb) {
 311                 struct regmap *grf = rockchip_clk_get_grf();
 312
 313                 if (IS_ERR(grf))
 314                         return;
 315
 316                 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
 317                          __func__, clk_hw_get_name(hw));
 318                 rockchip_rk3066_pll_set_params(pll, rate);
 319         }
 320 }
 321
 322 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
 323         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 324         .enable = rockchip_rk3066_pll_enable,
 325         .disable = rockchip_rk3066_pll_disable,
 326         .is_enabled = rockchip_rk3066_pll_is_enabled,
 327 };
 328
 329 static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
 330         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 331         .round_rate = rockchip_pll_round_rate,
 332         .set_rate = rockchip_rk3066_pll_set_rate,
 333         .enable = rockchip_rk3066_pll_enable,
 334         .disable = rockchip_rk3066_pll_disable,
 335         .is_enabled = rockchip_rk3066_pll_is_enabled,
 336         .init = rockchip_rk3066_pll_init,
 337 };
 338
 339 /*
 340  * Common registering of pll clocks
 341  */
 342
 343 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
 344                 const char *name, const char *const *parent_names,
 345                 u8 num_parents, void __iomem *base, int con_offset,
 346                 int grf_lock_offset, int lock_shift, int mode_offset,
 347                 int mode_shift, struct rockchip_pll_rate_table *rate_table,
 348                 u8 clk_pll_flags, spinlock_t *lock)
 349 {
 350         const char *pll_parents[3];
 351         struct clk_init_data init;
 352         struct rockchip_clk_pll *pll;
 353         struct clk_mux *pll_mux;
 354         struct clk *pll_clk, *mux_clk;
 355         char pll_name[20];
 356
 357         if (num_parents != 2) {
 358                 pr_err("%s: needs two parent clocks\n", __func__);
 359                 return ERR_PTR(-EINVAL);
 360         }
 361
 362         /* name the actual pll */
 363         snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
 364
 365         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 366         if (!pll)
 367                 return ERR_PTR(-ENOMEM);
 368
 369         /* create the mux on top of the real pll */
 370         pll->pll_mux_ops = &clk_mux_ops;
 371         pll_mux = &pll->pll_mux;
 372         pll_mux->reg = base + mode_offset;
 373         pll_mux->shift = mode_shift;
 374         pll_mux->mask = PLL_MODE_MASK;
 375         pll_mux->flags = 0;
 376         pll_mux->lock = lock;
 377         pll_mux->hw.init = &init;
 378
 379         if (pll_type == pll_rk3066)
 380                 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
 381
 382         /* the actual muxing is xin24m, pll-output, xin32k */
 383         pll_parents[0] = parent_names[0];
 384         pll_parents[1] = pll_name;
 385         pll_parents[2] = parent_names[1];
 386
 387         init.name = name;
 388         init.flags = CLK_SET_RATE_PARENT;
 389         init.ops = pll->pll_mux_ops;
 390         init.parent_names = pll_parents;
 391         init.num_parents = ARRAY_SIZE(pll_parents);
 392
 393         mux_clk = clk_register(NULL, &pll_mux->hw);
 394         if (IS_ERR(mux_clk))
 395                 goto err_mux;
 396
 397         /* now create the actual pll */
 398         init.name = pll_name;
 399
 400         /* keep all plls untouched for now */
 401         init.flags = CLK_IGNORE_UNUSED;
 402
 403         init.parent_names = &parent_names[0];
 404         init.num_parents = 1;
 405
 406         if (rate_table) {
 407                 int len;
 408
 409                 /* find count of rates in rate_table */
 410                 for (len = 0; rate_table[len].rate != 0; )
 411                         len++;
 412
 413                 pll->rate_count = len;
 414                 pll->rate_table = kmemdup(rate_table,
 415                                         pll->rate_count *
 416                                         sizeof(struct rockchip_pll_rate_table),
 417                                         GFP_KERNEL);
 418                 WARN(!pll->rate_table,
 419                         "%s: could not allocate rate table for %s\n",
 420                         __func__, name);
 421         }
 422
 423         switch (pll_type) {
 424         case pll_rk3066:
 425                 if (!pll->rate_table)
 426                         init.ops = &rockchip_rk3066_pll_clk_norate_ops;
 427                 else
 428                         init.ops = &rockchip_rk3066_pll_clk_ops;
 429                 break;
 430         default:
 431                 pr_warn("%s: Unknown pll type for pll clk %s\n",
 432                         __func__, name);
 433         }
 434
 435         pll->hw.init = &init;
 436         pll->type = pll_type;
 437         pll->reg_base = base + con_offset;
 438         pll->lock_offset = grf_lock_offset;
 439         pll->lock_shift = lock_shift;
 440         pll->flags = clk_pll_flags;
 441         pll->lock = lock;
 442
 443         pll_clk = clk_register(NULL, &pll->hw);
 444         if (IS_ERR(pll_clk)) {
 445                 pr_err("%s: failed to register pll clock %s : %ld\n",
 446                         __func__, name, PTR_ERR(pll_clk));
 447                 goto err_pll;
 448         }
 449
 450         return mux_clk;
 451
 452 err_pll:
 453         clk_unregister(mux_clk);
 454         mux_clk = pll_clk;
 455 err_mux:
 456         kfree(pll);
 457         return mux_clk;
 458 }