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of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / drivers / clk / samsung / clk-exynos5433.c
blobcee062c588dec2c2471b55c4c2b60a44d20ec42f
1 /*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5443 SoC.
10 */
11
12 #include <linux/clk-provider.h>
13 #include <linux/of.h>
14
15 #include <dt-bindings/clock/exynos5433.h>
16
17 #include "clk.h"
18 #include "clk-pll.h"
19
20 /*
21 * Register offset definitions for CMU_TOP
22 */
23 #define ISP_PLL_LOCK 0x0000
24 #define AUD_PLL_LOCK 0x0004
25 #define ISP_PLL_CON0 0x0100
26 #define ISP_PLL_CON1 0x0104
27 #define ISP_PLL_FREQ_DET 0x0108
28 #define AUD_PLL_CON0 0x0110
29 #define AUD_PLL_CON1 0x0114
30 #define AUD_PLL_CON2 0x0118
31 #define AUD_PLL_FREQ_DET 0x011c
32 #define MUX_SEL_TOP0 0x0200
33 #define MUX_SEL_TOP1 0x0204
34 #define MUX_SEL_TOP2 0x0208
35 #define MUX_SEL_TOP3 0x020c
36 #define MUX_SEL_TOP4 0x0210
37 #define MUX_SEL_TOP_MSCL 0x0220
38 #define MUX_SEL_TOP_CAM1 0x0224
39 #define MUX_SEL_TOP_DISP 0x0228
40 #define MUX_SEL_TOP_FSYS0 0x0230
41 #define MUX_SEL_TOP_FSYS1 0x0234
42 #define MUX_SEL_TOP_PERIC0 0x0238
43 #define MUX_SEL_TOP_PERIC1 0x023c
44 #define MUX_ENABLE_TOP0 0x0300
45 #define MUX_ENABLE_TOP1 0x0304
46 #define MUX_ENABLE_TOP2 0x0308
47 #define MUX_ENABLE_TOP3 0x030c
48 #define MUX_ENABLE_TOP4 0x0310
49 #define MUX_ENABLE_TOP_MSCL 0x0320
50 #define MUX_ENABLE_TOP_CAM1 0x0324
51 #define MUX_ENABLE_TOP_DISP 0x0328
52 #define MUX_ENABLE_TOP_FSYS0 0x0330
53 #define MUX_ENABLE_TOP_FSYS1 0x0334
54 #define MUX_ENABLE_TOP_PERIC0 0x0338
55 #define MUX_ENABLE_TOP_PERIC1 0x033c
56 #define MUX_STAT_TOP0 0x0400
57 #define MUX_STAT_TOP1 0x0404
58 #define MUX_STAT_TOP2 0x0408
59 #define MUX_STAT_TOP3 0x040c
60 #define MUX_STAT_TOP4 0x0410
61 #define MUX_STAT_TOP_MSCL 0x0420
62 #define MUX_STAT_TOP_CAM1 0x0424
63 #define MUX_STAT_TOP_FSYS0 0x0430
64 #define MUX_STAT_TOP_FSYS1 0x0434
65 #define MUX_STAT_TOP_PERIC0 0x0438
66 #define MUX_STAT_TOP_PERIC1 0x043c
67 #define DIV_TOP0 0x0600
68 #define DIV_TOP1 0x0604
69 #define DIV_TOP2 0x0608
70 #define DIV_TOP3 0x060c
71 #define DIV_TOP4 0x0610
72 #define DIV_TOP_MSCL 0x0618
73 #define DIV_TOP_CAM10 0x061c
74 #define DIV_TOP_CAM11 0x0620
75 #define DIV_TOP_FSYS0 0x062c
76 #define DIV_TOP_FSYS1 0x0630
77 #define DIV_TOP_FSYS2 0x0634
78 #define DIV_TOP_PERIC0 0x0638
79 #define DIV_TOP_PERIC1 0x063c
80 #define DIV_TOP_PERIC2 0x0640
81 #define DIV_TOP_PERIC3 0x0644
82 #define DIV_TOP_PERIC4 0x0648
83 #define DIV_TOP_PLL_FREQ_DET 0x064c
84 #define DIV_STAT_TOP0 0x0700
85 #define DIV_STAT_TOP1 0x0704
86 #define DIV_STAT_TOP2 0x0708
87 #define DIV_STAT_TOP3 0x070c
88 #define DIV_STAT_TOP4 0x0710
89 #define DIV_STAT_TOP_MSCL 0x0718
90 #define DIV_STAT_TOP_CAM10 0x071c
91 #define DIV_STAT_TOP_CAM11 0x0720
92 #define DIV_STAT_TOP_FSYS0 0x072c
93 #define DIV_STAT_TOP_FSYS1 0x0730
94 #define DIV_STAT_TOP_FSYS2 0x0734
95 #define DIV_STAT_TOP_PERIC0 0x0738
96 #define DIV_STAT_TOP_PERIC1 0x073c
97 #define DIV_STAT_TOP_PERIC2 0x0740
98 #define DIV_STAT_TOP_PERIC3 0x0744
99 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
100 #define ENABLE_ACLK_TOP 0x0800
101 #define ENABLE_SCLK_TOP 0x0a00
102 #define ENABLE_SCLK_TOP_MSCL 0x0a04
103 #define ENABLE_SCLK_TOP_CAM1 0x0a08
104 #define ENABLE_SCLK_TOP_DISP 0x0a0c
105 #define ENABLE_SCLK_TOP_FSYS 0x0a10
106 #define ENABLE_SCLK_TOP_PERIC 0x0a14
107 #define ENABLE_IP_TOP 0x0b00
108 #define ENABLE_CMU_TOP 0x0c00
109 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
110
111 static unsigned long top_clk_regs[] __initdata = {
112 ISP_PLL_LOCK,
113 AUD_PLL_LOCK,
114 ISP_PLL_CON0,
115 ISP_PLL_CON1,
116 ISP_PLL_FREQ_DET,
117 AUD_PLL_CON0,
118 AUD_PLL_CON1,
119 AUD_PLL_CON2,
120 AUD_PLL_FREQ_DET,
121 MUX_SEL_TOP0,
122 MUX_SEL_TOP1,
123 MUX_SEL_TOP2,
124 MUX_SEL_TOP3,
125 MUX_SEL_TOP4,
126 MUX_SEL_TOP_MSCL,
127 MUX_SEL_TOP_CAM1,
128 MUX_SEL_TOP_DISP,
129 MUX_SEL_TOP_FSYS0,
130 MUX_SEL_TOP_FSYS1,
131 MUX_SEL_TOP_PERIC0,
132 MUX_SEL_TOP_PERIC1,
133 MUX_ENABLE_TOP0,
134 MUX_ENABLE_TOP1,
135 MUX_ENABLE_TOP2,
136 MUX_ENABLE_TOP3,
137 MUX_ENABLE_TOP4,
138 MUX_ENABLE_TOP_MSCL,
139 MUX_ENABLE_TOP_CAM1,
140 MUX_ENABLE_TOP_DISP,
141 MUX_ENABLE_TOP_FSYS0,
142 MUX_ENABLE_TOP_FSYS1,
143 MUX_ENABLE_TOP_PERIC0,
144 MUX_ENABLE_TOP_PERIC1,
145 MUX_STAT_TOP0,
146 MUX_STAT_TOP1,
147 MUX_STAT_TOP2,
148 MUX_STAT_TOP3,
149 MUX_STAT_TOP4,
150 MUX_STAT_TOP_MSCL,
151 MUX_STAT_TOP_CAM1,
152 MUX_STAT_TOP_FSYS0,
153 MUX_STAT_TOP_FSYS1,
154 MUX_STAT_TOP_PERIC0,
155 MUX_STAT_TOP_PERIC1,
156 DIV_TOP0,
157 DIV_TOP1,
158 DIV_TOP2,
159 DIV_TOP3,
160 DIV_TOP4,
161 DIV_TOP_MSCL,
162 DIV_TOP_CAM10,
163 DIV_TOP_CAM11,
164 DIV_TOP_FSYS0,
165 DIV_TOP_FSYS1,
166 DIV_TOP_FSYS2,
167 DIV_TOP_PERIC0,
168 DIV_TOP_PERIC1,
169 DIV_TOP_PERIC2,
170 DIV_TOP_PERIC3,
171 DIV_TOP_PERIC4,
172 DIV_TOP_PLL_FREQ_DET,
173 DIV_STAT_TOP0,
174 DIV_STAT_TOP1,
175 DIV_STAT_TOP2,
176 DIV_STAT_TOP3,
177 DIV_STAT_TOP4,
178 DIV_STAT_TOP_MSCL,
179 DIV_STAT_TOP_CAM10,
180 DIV_STAT_TOP_CAM11,
181 DIV_STAT_TOP_FSYS0,
182 DIV_STAT_TOP_FSYS1,
183 DIV_STAT_TOP_FSYS2,
184 DIV_STAT_TOP_PERIC0,
185 DIV_STAT_TOP_PERIC1,
186 DIV_STAT_TOP_PERIC2,
187 DIV_STAT_TOP_PERIC3,
188 DIV_STAT_TOP_PLL_FREQ_DET,
189 ENABLE_ACLK_TOP,
190 ENABLE_SCLK_TOP,
191 ENABLE_SCLK_TOP_MSCL,
192 ENABLE_SCLK_TOP_CAM1,
193 ENABLE_SCLK_TOP_DISP,
194 ENABLE_SCLK_TOP_FSYS,
195 ENABLE_SCLK_TOP_PERIC,
196 ENABLE_IP_TOP,
197 ENABLE_CMU_TOP,
198 ENABLE_CMU_TOP_DIV_STAT,
199 };
200
201 /* list of all parent clock list */
202 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
203 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
204 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
205 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
206 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
207 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
208 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
209 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
210
211 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
212 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
213 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
214 "mout_mfc_pll_user", };
215 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
216
217 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
218 "mout_mphy_pll_user", };
219 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
220 "mout_bus_pll_user", };
221 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
222
223 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
224 "mout_mphy_pll_user", };
225 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
226 "mout_mphy_pll_user", };
227 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
228 "mout_mphy_pll_user", };
229
230 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
231 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
232
233 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
234 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
235 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
236 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
237 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
238
239 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
240 "oscclk", "ioclk_spdif_extclk", };
241 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
242 "mout_aud_pll_user_t",};
243 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
244 "mout_aud_pll_user_t",};
245
246 PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
247
248 static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
249 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
250 };
251
252 static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
253 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
254 FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
255 FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
256 /* Xi2s1SDI input clock for SPDIF */
257 FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
258 /* XspiCLK[4:0] input clock for SPI */
259 FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
260 FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
261 FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
262 FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
263 FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
264 /* Xi2s1SCLK input clock for I2S1_BCLK */
265 FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
266 };
267
268 static struct samsung_mux_clock top_mux_clks[] __initdata = {
269 /* MUX_SEL_TOP0 */
270 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
271 4, 1),
272 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
273 0, 1),
274
275 /* MUX_SEL_TOP1 */
276 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
277 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
278 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
279 MUX_SEL_TOP1, 8, 1),
280 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
281 MUX_SEL_TOP1, 4, 1),
282 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
283 MUX_SEL_TOP1, 0, 1),
284
285 /* MUX_SEL_TOP2 */
286 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
287 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
288 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
289 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
290 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
291 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
292 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
293 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
294 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
295 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
296 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
297 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
298
299 /* MUX_SEL_TOP3 */
300 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
301 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
302 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
303 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
304 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
305 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
306 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
307 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
308 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
309 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
310 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
311 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
312
313 /* MUX_SEL_TOP4 */
314 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
315 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
316 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
317 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
318 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
319 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
320
321 /* MUX_SEL_TOP_MSCL */
322 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
323 MUX_SEL_TOP_MSCL, 8, 1),
324 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
325 MUX_SEL_TOP_MSCL, 4, 1),
326 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
327 MUX_SEL_TOP_MSCL, 0, 1),
328
329 /* MUX_SEL_TOP_CAM1 */
330 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
331 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
332 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
333 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
334 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
335 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
336 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
337 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
338 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
339 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
340 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
341 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
342
343 /* MUX_SEL_TOP_FSYS0 */
344 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
345 MUX_SEL_TOP_FSYS0, 28, 1),
346 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
347 MUX_SEL_TOP_FSYS0, 24, 1),
348 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
349 MUX_SEL_TOP_FSYS0, 20, 1),
350 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
351 MUX_SEL_TOP_FSYS0, 16, 1),
352 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
353 MUX_SEL_TOP_FSYS0, 12, 1),
354 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
355 MUX_SEL_TOP_FSYS0, 8, 1),
356 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
357 MUX_SEL_TOP_FSYS0, 4, 1),
358 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
359 MUX_SEL_TOP_FSYS0, 0, 1),
360
361 /* MUX_SEL_TOP_FSYS1 */
362 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
363 MUX_SEL_TOP_FSYS1, 12, 1),
364 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
365 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
366 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
367 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
368 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
369 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
370
371 /* MUX_SEL_TOP_PERIC0 */
372 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
373 MUX_SEL_TOP_PERIC0, 28, 1),
374 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
375 MUX_SEL_TOP_PERIC0, 24, 1),
376 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
377 MUX_SEL_TOP_PERIC0, 20, 1),
378 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
379 MUX_SEL_TOP_PERIC0, 16, 1),
380 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
381 MUX_SEL_TOP_PERIC0, 12, 1),
382 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
383 MUX_SEL_TOP_PERIC0, 8, 1),
384 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
385 MUX_SEL_TOP_PERIC0, 4, 1),
386 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
387 MUX_SEL_TOP_PERIC0, 0, 1),
388
389 /* MUX_SEL_TOP_PERIC1 */
390 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
391 MUX_SEL_TOP_PERIC1, 16, 1),
392 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
393 MUX_SEL_TOP_PERIC1, 12, 2),
394 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
395 MUX_SEL_TOP_PERIC1, 4, 2),
396 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
397 MUX_SEL_TOP_PERIC1, 0, 2),
398
399 /* MUX_SEL_TOP_DISP */
400 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
401 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
402 };
403
404 static struct samsung_div_clock top_div_clks[] __initdata = {
405 /* DIV_TOP0 */
406 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
407 DIV_TOP0, 28, 3),
408 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
409 DIV_TOP0, 24, 3),
410 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
411 DIV_TOP0, 20, 3),
412 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
413 DIV_TOP0, 16, 3),
414 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
415 DIV_TOP0, 12, 3),
416 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
417 DIV_TOP0, 8, 3),
418 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
419 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
420 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
421 "mout_aclk_isp_400", DIV_TOP0, 0, 4),
422
423 /* DIV_TOP1 */
424 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
425 DIV_TOP1, 28, 3),
426 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
427 DIV_TOP1, 24, 3),
428 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
429 DIV_TOP1, 20, 3),
430 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
431 DIV_TOP1, 12, 3),
432 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
433 DIV_TOP1, 8, 3),
434 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
435 DIV_TOP1, 0, 3),
436
437 /* DIV_TOP2 */
438 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
439 DIV_TOP2, 4, 3),
440 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
441 DIV_TOP2, 0, 3),
442
443 /* DIV_TOP3 */
444 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
445 "mout_bus_pll_user", DIV_TOP3, 24, 3),
446 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
447 "mout_bus_pll_user", DIV_TOP3, 20, 3),
448 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
449 "mout_bus_pll_user", DIV_TOP3, 16, 3),
450 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
451 "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
452 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
453 "mout_bus_pll_user", DIV_TOP3, 8, 3),
454 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
455 "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
456 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
457 "mout_bus_pll_user", DIV_TOP3, 0, 3),
458
459 /* DIV_TOP4 */
460 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
461 DIV_TOP4, 8, 3),
462 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
463 DIV_TOP4, 4, 3),
464 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
465 DIV_TOP4, 0, 3),
466
467 /* DIV_TOP_MSCL */
468 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
469 DIV_TOP_MSCL, 0, 4),
470
471 /* DIV_TOP_CAM10 */
472 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
473 DIV_TOP_CAM10, 24, 5),
474 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
475 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
476 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
477 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
478 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
479 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
480 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
481 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
482
483 /* DIV_TOP_CAM11 */
484 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
485 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
486 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
487 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
488 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
489 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
490 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
491 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
492 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
493 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 12, 4),
494 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
495 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 8, 4),
496
497 /* DIV_TOP_FSYS0 */
498 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
499 DIV_TOP_FSYS0, 16, 8),
500 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
501 DIV_TOP_FSYS0, 12, 4),
502 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
503 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
504 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
505 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
506
507 /* DIV_TOP_FSYS1 */
508 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
509 DIV_TOP_FSYS1, 4, 8),
510 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
511 DIV_TOP_FSYS1, 0, 4),
512
513 /* DIV_TOP_FSYS2 */
514 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
515 DIV_TOP_FSYS2, 12, 3),
516 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
517 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
518 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
519 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
520 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
521 DIV_TOP_FSYS2, 0, 4),
522
523 /* DIV_TOP_PERIC0 */
524 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
525 DIV_TOP_PERIC0, 16, 8),
526 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
527 DIV_TOP_PERIC0, 12, 4),
528 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
529 DIV_TOP_PERIC0, 4, 8),
530 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
531 DIV_TOP_PERIC0, 0, 4),
532
533 /* DIV_TOP_PERIC1 */
534 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
535 DIV_TOP_PERIC1, 4, 8),
536 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
537 DIV_TOP_PERIC1, 0, 4),
538
539 /* DIV_TOP_PERIC2 */
540 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
541 DIV_TOP_PERIC2, 8, 4),
542 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
543 DIV_TOP_PERIC2, 4, 4),
544 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
545 DIV_TOP_PERIC2, 0, 4),
546
547 /* DIV_TOP_PERIC3 */
548 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
549 DIV_TOP_PERIC3, 16, 6),
550 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
551 DIV_TOP_PERIC3, 8, 8),
552 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
553 DIV_TOP_PERIC3, 4, 4),
554 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
555 DIV_TOP_PERIC3, 0, 4),
556
557 /* DIV_TOP_PERIC4 */
558 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
559 DIV_TOP_PERIC4, 16, 8),
560 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
561 DIV_TOP_PERIC4, 12, 4),
562 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
563 DIV_TOP_PERIC4, 4, 8),
564 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
565 DIV_TOP_PERIC4, 0, 4),
566 };
567
568 static struct samsung_gate_clock top_gate_clks[] __initdata = {
569 /* ENABLE_ACLK_TOP */
570 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
571 ENABLE_ACLK_TOP, 30, 0, 0),
572 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
573 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
574 29, CLK_IGNORE_UNUSED, 0),
575 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
576 ENABLE_ACLK_TOP, 26,
577 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
578 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
579 ENABLE_ACLK_TOP, 25,
580 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
581 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
582 ENABLE_ACLK_TOP, 24,
583 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
584 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
585 ENABLE_ACLK_TOP, 23,
586 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
587 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
588 ENABLE_ACLK_TOP, 22,
589 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
590 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
591 ENABLE_ACLK_TOP, 21,
592 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
593 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
594 ENABLE_ACLK_TOP, 19,
595 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
596 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
597 ENABLE_ACLK_TOP, 18,
598 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
599 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
600 ENABLE_ACLK_TOP, 15,
601 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
602 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
603 ENABLE_ACLK_TOP, 14,
604 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
605 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
606 ENABLE_ACLK_TOP, 13,
607 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
608 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
609 ENABLE_ACLK_TOP, 12,
610 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
611 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
612 ENABLE_ACLK_TOP, 11,
613 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
614 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
615 ENABLE_ACLK_TOP, 10,
616 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
617 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
618 ENABLE_ACLK_TOP, 9,
619 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
620 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
621 ENABLE_ACLK_TOP, 8,
622 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
623 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
624 ENABLE_ACLK_TOP, 7,
625 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
626 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
627 ENABLE_ACLK_TOP, 6,
628 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
629 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
630 ENABLE_ACLK_TOP, 5,
631 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
632 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
633 ENABLE_ACLK_TOP, 3,
634 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
635 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
636 ENABLE_ACLK_TOP, 2,
637 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
638 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
639 ENABLE_ACLK_TOP, 0,
640 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
641
642 /* ENABLE_SCLK_TOP_MSCL */
643 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
644 ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
645
646 /* ENABLE_SCLK_TOP_CAM1 */
647 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
648 ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
649 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
650 ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
651 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
652 ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
653 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
654 ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
655 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
656 ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
657 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
658 ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
659 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
660 ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
661
662 /* ENABLE_SCLK_TOP_DISP */
663 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
664 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
665 CLK_IGNORE_UNUSED, 0),
666
667 /* ENABLE_SCLK_TOP_FSYS */
668 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
669 ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
670 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
671 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
672 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
673 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
674 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
675 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
676 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
677 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
678 3, CLK_SET_RATE_PARENT, 0),
679 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
680 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
681 1, CLK_SET_RATE_PARENT, 0),
682 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
683 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
684 0, CLK_SET_RATE_PARENT, 0),
685
686 /* ENABLE_SCLK_TOP_PERIC */
687 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
688 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
689 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
690 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
691 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
692 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
693 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
694 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
695 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
696 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
697 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
698 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
699 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
700 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
701 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
702 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
703 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
704 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
705 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
706 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
707 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
708 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
709
710 /* MUX_ENABLE_TOP_PERIC1 */
711 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
712 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
713 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
714 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
715 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
716 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
717 };
718
719 /*
720 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
721 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
722 */
723 static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
724 PLL_35XX_RATE(2500000000U, 625, 6, 0),
725 PLL_35XX_RATE(2400000000U, 500, 5, 0),
726 PLL_35XX_RATE(2300000000U, 575, 6, 0),
727 PLL_35XX_RATE(2200000000U, 550, 6, 0),
728 PLL_35XX_RATE(2100000000U, 350, 4, 0),
729 PLL_35XX_RATE(2000000000U, 500, 6, 0),
730 PLL_35XX_RATE(1900000000U, 475, 6, 0),
731 PLL_35XX_RATE(1800000000U, 375, 5, 0),
732 PLL_35XX_RATE(1700000000U, 425, 6, 0),
733 PLL_35XX_RATE(1600000000U, 400, 6, 0),
734 PLL_35XX_RATE(1500000000U, 250, 4, 0),
735 PLL_35XX_RATE(1400000000U, 350, 6, 0),
736 PLL_35XX_RATE(1332000000U, 222, 4, 0),
737 PLL_35XX_RATE(1300000000U, 325, 6, 0),
738 PLL_35XX_RATE(1200000000U, 500, 5, 1),
739 PLL_35XX_RATE(1100000000U, 550, 6, 1),
740 PLL_35XX_RATE(1086000000U, 362, 4, 1),
741 PLL_35XX_RATE(1066000000U, 533, 6, 1),
742 PLL_35XX_RATE(1000000000U, 500, 6, 1),
743 PLL_35XX_RATE(933000000U, 311, 4, 1),
744 PLL_35XX_RATE(921000000U, 307, 4, 1),
745 PLL_35XX_RATE(900000000U, 375, 5, 1),
746 PLL_35XX_RATE(825000000U, 275, 4, 1),
747 PLL_35XX_RATE(800000000U, 400, 6, 1),
748 PLL_35XX_RATE(733000000U, 733, 12, 1),
749 PLL_35XX_RATE(700000000U, 175, 3, 1),
750 PLL_35XX_RATE(667000000U, 222, 4, 1),
751 PLL_35XX_RATE(633000000U, 211, 4, 1),
752 PLL_35XX_RATE(600000000U, 500, 5, 2),
753 PLL_35XX_RATE(552000000U, 460, 5, 2),
754 PLL_35XX_RATE(550000000U, 550, 6, 2),
755 PLL_35XX_RATE(543000000U, 362, 4, 2),
756 PLL_35XX_RATE(533000000U, 533, 6, 2),
757 PLL_35XX_RATE(500000000U, 500, 6, 2),
758 PLL_35XX_RATE(444000000U, 370, 5, 2),
759 PLL_35XX_RATE(420000000U, 350, 5, 2),
760 PLL_35XX_RATE(400000000U, 400, 6, 2),
761 PLL_35XX_RATE(350000000U, 350, 6, 2),
762 PLL_35XX_RATE(333000000U, 222, 4, 2),
763 PLL_35XX_RATE(300000000U, 500, 5, 3),
764 PLL_35XX_RATE(266000000U, 532, 6, 3),
765 PLL_35XX_RATE(200000000U, 400, 6, 3),
766 PLL_35XX_RATE(166000000U, 332, 6, 3),
767 PLL_35XX_RATE(160000000U, 320, 6, 3),
768 PLL_35XX_RATE(133000000U, 532, 6, 4),
769 PLL_35XX_RATE(100000000U, 400, 6, 4),
770 { /* sentinel */ }
771 };
772
773 /* AUD_PLL */
774 static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
775 PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
776 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
777 PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
778 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
779 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
780 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816),
781 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
782 PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
783 PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
784 { /* sentinel */ }
785 };
786
787 static struct samsung_pll_clock top_pll_clks[] __initdata = {
788 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
789 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
790 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
791 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
792 };
793
794 static struct samsung_cmu_info top_cmu_info __initdata = {
795 .pll_clks = top_pll_clks,
796 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
797 .mux_clks = top_mux_clks,
798 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
799 .div_clks = top_div_clks,
800 .nr_div_clks = ARRAY_SIZE(top_div_clks),
801 .gate_clks = top_gate_clks,
802 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
803 .fixed_clks = top_fixed_clks,
804 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
805 .fixed_factor_clks = top_fixed_factor_clks,
806 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
807 .nr_clk_ids = TOP_NR_CLK,
808 .clk_regs = top_clk_regs,
809 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
810 };
811
812 static void __init exynos5433_cmu_top_init(struct device_node *np)
813 {
814 samsung_cmu_register_one(np, &top_cmu_info);
815 }
816 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
817 exynos5433_cmu_top_init);
818
819 /*
820 * Register offset definitions for CMU_CPIF
821 */
822 #define MPHY_PLL_LOCK 0x0000
823 #define MPHY_PLL_CON0 0x0100
824 #define MPHY_PLL_CON1 0x0104
825 #define MPHY_PLL_FREQ_DET 0x010c
826 #define MUX_SEL_CPIF0 0x0200
827 #define DIV_CPIF 0x0600
828 #define ENABLE_SCLK_CPIF 0x0a00
829
830 static unsigned long cpif_clk_regs[] __initdata = {
831 MPHY_PLL_LOCK,
832 MPHY_PLL_CON0,
833 MPHY_PLL_CON1,
834 MPHY_PLL_FREQ_DET,
835 MUX_SEL_CPIF0,
836 DIV_CPIF,
837 ENABLE_SCLK_CPIF,
838 };
839
840 /* list of all parent clock list */
841 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
842
843 static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
844 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
845 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
846 };
847
848 static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
849 /* MUX_SEL_CPIF0 */
850 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
851 0, 1),
852 };
853
854 static struct samsung_div_clock cpif_div_clks[] __initdata = {
855 /* DIV_CPIF */
856 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
857 0, 6),
858 };
859
860 static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
861 /* ENABLE_SCLK_CPIF */
862 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
863 ENABLE_SCLK_CPIF, 9, 0, 0),
864 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
865 ENABLE_SCLK_CPIF, 4, 0, 0),
866 };
867
868 static struct samsung_cmu_info cpif_cmu_info __initdata = {
869 .pll_clks = cpif_pll_clks,
870 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
871 .mux_clks = cpif_mux_clks,
872 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
873 .div_clks = cpif_div_clks,
874 .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
875 .gate_clks = cpif_gate_clks,
876 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
877 .nr_clk_ids = CPIF_NR_CLK,
878 .clk_regs = cpif_clk_regs,
879 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
880 };
881
882 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
883 {
884 samsung_cmu_register_one(np, &cpif_cmu_info);
885 }
886 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
887 exynos5433_cmu_cpif_init);
888
889 /*
890 * Register offset definitions for CMU_MIF
891 */
892 #define MEM0_PLL_LOCK 0x0000
893 #define MEM1_PLL_LOCK 0x0004
894 #define BUS_PLL_LOCK 0x0008
895 #define MFC_PLL_LOCK 0x000c
896 #define MEM0_PLL_CON0 0x0100
897 #define MEM0_PLL_CON1 0x0104
898 #define MEM0_PLL_FREQ_DET 0x010c
899 #define MEM1_PLL_CON0 0x0110
900 #define MEM1_PLL_CON1 0x0114
901 #define MEM1_PLL_FREQ_DET 0x011c
902 #define BUS_PLL_CON0 0x0120
903 #define BUS_PLL_CON1 0x0124
904 #define BUS_PLL_FREQ_DET 0x012c
905 #define MFC_PLL_CON0 0x0130
906 #define MFC_PLL_CON1 0x0134
907 #define MFC_PLL_FREQ_DET 0x013c
908 #define MUX_SEL_MIF0 0x0200
909 #define MUX_SEL_MIF1 0x0204
910 #define MUX_SEL_MIF2 0x0208
911 #define MUX_SEL_MIF3 0x020c
912 #define MUX_SEL_MIF4 0x0210
913 #define MUX_SEL_MIF5 0x0214
914 #define MUX_SEL_MIF6 0x0218
915 #define MUX_SEL_MIF7 0x021c
916 #define MUX_ENABLE_MIF0 0x0300
917 #define MUX_ENABLE_MIF1 0x0304
918 #define MUX_ENABLE_MIF2 0x0308
919 #define MUX_ENABLE_MIF3 0x030c
920 #define MUX_ENABLE_MIF4 0x0310
921 #define MUX_ENABLE_MIF5 0x0314
922 #define MUX_ENABLE_MIF6 0x0318
923 #define MUX_ENABLE_MIF7 0x031c
924 #define MUX_STAT_MIF0 0x0400
925 #define MUX_STAT_MIF1 0x0404
926 #define MUX_STAT_MIF2 0x0408
927 #define MUX_STAT_MIF3 0x040c
928 #define MUX_STAT_MIF4 0x0410
929 #define MUX_STAT_MIF5 0x0414
930 #define MUX_STAT_MIF6 0x0418
931 #define MUX_STAT_MIF7 0x041c
932 #define DIV_MIF1 0x0604
933 #define DIV_MIF2 0x0608
934 #define DIV_MIF3 0x060c
935 #define DIV_MIF4 0x0610
936 #define DIV_MIF5 0x0614
937 #define DIV_MIF_PLL_FREQ_DET 0x0618
938 #define DIV_STAT_MIF1 0x0704
939 #define DIV_STAT_MIF2 0x0708
940 #define DIV_STAT_MIF3 0x070c
941 #define DIV_STAT_MIF4 0x0710
942 #define DIV_STAT_MIF5 0x0714
943 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
944 #define ENABLE_ACLK_MIF0 0x0800
945 #define ENABLE_ACLK_MIF1 0x0804
946 #define ENABLE_ACLK_MIF2 0x0808
947 #define ENABLE_ACLK_MIF3 0x080c
948 #define ENABLE_PCLK_MIF 0x0900
949 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
950 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
951 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
952 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
953 #define ENABLE_SCLK_MIF 0x0a00
954 #define ENABLE_IP_MIF0 0x0b00
955 #define ENABLE_IP_MIF1 0x0b04
956 #define ENABLE_IP_MIF2 0x0b08
957 #define ENABLE_IP_MIF3 0x0b0c
958 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
959 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
960 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
961 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
962 #define CLKOUT_CMU_MIF 0x0c00
963 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
964 #define DREX_FREQ_CTRL0 0x1000
965 #define DREX_FREQ_CTRL1 0x1004
966 #define PAUSE 0x1008
967 #define DDRPHY_LOCK_CTRL 0x100c
968
969 static unsigned long mif_clk_regs[] __initdata = {
970 MEM0_PLL_LOCK,
971 MEM1_PLL_LOCK,
972 BUS_PLL_LOCK,
973 MFC_PLL_LOCK,
974 MEM0_PLL_CON0,
975 MEM0_PLL_CON1,
976 MEM0_PLL_FREQ_DET,
977 MEM1_PLL_CON0,
978 MEM1_PLL_CON1,
979 MEM1_PLL_FREQ_DET,
980 BUS_PLL_CON0,
981 BUS_PLL_CON1,
982 BUS_PLL_FREQ_DET,
983 MFC_PLL_CON0,
984 MFC_PLL_CON1,
985 MFC_PLL_FREQ_DET,
986 MUX_SEL_MIF0,
987 MUX_SEL_MIF1,
988 MUX_SEL_MIF2,
989 MUX_SEL_MIF3,
990 MUX_SEL_MIF4,
991 MUX_SEL_MIF5,
992 MUX_SEL_MIF6,
993 MUX_SEL_MIF7,
994 MUX_ENABLE_MIF0,
995 MUX_ENABLE_MIF1,
996 MUX_ENABLE_MIF2,
997 MUX_ENABLE_MIF3,
998 MUX_ENABLE_MIF4,
999 MUX_ENABLE_MIF5,
1000 MUX_ENABLE_MIF6,
1001 MUX_ENABLE_MIF7,
1002 MUX_STAT_MIF0,
1003 MUX_STAT_MIF1,
1004 MUX_STAT_MIF2,
1005 MUX_STAT_MIF3,
1006 MUX_STAT_MIF4,
1007 MUX_STAT_MIF5,
1008 MUX_STAT_MIF6,
1009 MUX_STAT_MIF7,
1010 DIV_MIF1,
1011 DIV_MIF2,
1012 DIV_MIF3,
1013 DIV_MIF4,
1014 DIV_MIF5,
1015 DIV_MIF_PLL_FREQ_DET,
1016 DIV_STAT_MIF1,
1017 DIV_STAT_MIF2,
1018 DIV_STAT_MIF3,
1019 DIV_STAT_MIF4,
1020 DIV_STAT_MIF5,
1021 DIV_STAT_MIF_PLL_FREQ_DET,
1022 ENABLE_ACLK_MIF0,
1023 ENABLE_ACLK_MIF1,
1024 ENABLE_ACLK_MIF2,
1025 ENABLE_ACLK_MIF3,
1026 ENABLE_PCLK_MIF,
1027 ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
1028 ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
1029 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
1030 ENABLE_PCLK_MIF_SECURE_RTC,
1031 ENABLE_SCLK_MIF,
1032 ENABLE_IP_MIF0,
1033 ENABLE_IP_MIF1,
1034 ENABLE_IP_MIF2,
1035 ENABLE_IP_MIF3,
1036 ENABLE_IP_MIF_SECURE_DREX0_TZ,
1037 ENABLE_IP_MIF_SECURE_DREX1_TZ,
1038 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
1039 ENABLE_IP_MIF_SECURE_RTC,
1040 CLKOUT_CMU_MIF,
1041 CLKOUT_CMU_MIF_DIV_STAT,
1042 DREX_FREQ_CTRL0,
1043 DREX_FREQ_CTRL1,
1044 PAUSE,
1045 DDRPHY_LOCK_CTRL,
1046 };
1047
1048 static struct samsung_pll_clock mif_pll_clks[] __initdata = {
1049 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1050 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
1051 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1052 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
1053 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1054 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
1055 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1056 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
1057 };
1058
1059 /* list of all parent clock list */
1060 PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
1061 PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
1062 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
1063 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
1064 PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
1065 PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
1066 PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
1067 PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
1068
1069 PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1070 PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1071 PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1072 PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1073
1074 PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
1075 PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1076
1077 PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
1078 "mout_bus_pll_div2", };
1079 PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1080
1081 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1082 "sclk_mphy_pll", };
1083 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1084 "mout_mfc_pll_div2", };
1085 PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
1086 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1087 "sclk_mphy_pll", };
1088 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1089 "mout_mfc_pll_div2", };
1090
1091 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1092 "sclk_mphy_pll", };
1093 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1094 "mout_mfc_pll_div2", };
1095 PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1096 PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1097 PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
1098
1099 PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1100 PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1101
1102 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1103 "sclk_mphy_pll", };
1104 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1105 "mout_mfc_pll_div2", };
1106 PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1107 PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1108
1109 static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
1110 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1111 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1112 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1113 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1114 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1115 };
1116
1117 static struct samsung_mux_clock mif_mux_clks[] __initdata = {
1118 /* MUX_SEL_MIF0 */
1119 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1120 MUX_SEL_MIF0, 28, 1),
1121 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1122 MUX_SEL_MIF0, 24, 1),
1123 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1124 MUX_SEL_MIF0, 20, 1),
1125 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1126 MUX_SEL_MIF0, 16, 1),
1127 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1128 12, 1),
1129 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1130 8, 1),
1131 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1132 4, 1),
1133 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1134 0, 1),
1135
1136 /* MUX_SEL_MIF1 */
1137 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1138 MUX_SEL_MIF1, 24, 1),
1139 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1140 MUX_SEL_MIF1, 20, 1),
1141 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1142 MUX_SEL_MIF1, 16, 1),
1143 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1144 MUX_SEL_MIF1, 12, 1),
1145 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1146 MUX_SEL_MIF1, 8, 1),
1147 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1148 MUX_SEL_MIF1, 4, 1),
1149
1150 /* MUX_SEL_MIF2 */
1151 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1152 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1153 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1154 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1155
1156 /* MUX_SEL_MIF3 */
1157 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1158 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1159 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1160 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1161
1162 /* MUX_SEL_MIF4 */
1163 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1164 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1165 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1166 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1167 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1168 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1169 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1170 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1171 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1172 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1173 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1174 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1175
1176 /* MUX_SEL_MIF5 */
1177 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1178 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1179 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1180 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1181 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1182 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1183 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1184 MUX_SEL_MIF5, 8, 1),
1185 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1186 MUX_SEL_MIF5, 4, 1),
1187 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1188 MUX_SEL_MIF5, 0, 1),
1189
1190 /* MUX_SEL_MIF6 */
1191 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1192 MUX_SEL_MIF6, 8, 1),
1193 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1194 MUX_SEL_MIF6, 4, 1),
1195 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1196 MUX_SEL_MIF6, 0, 1),
1197
1198 /* MUX_SEL_MIF7 */
1199 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1200 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1201 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1202 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1203 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1204 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1205 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1206 MUX_SEL_MIF7, 8, 1),
1207 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1208 MUX_SEL_MIF7, 4, 1),
1209 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1210 MUX_SEL_MIF7, 0, 1),
1211 };
1212
1213 static struct samsung_div_clock mif_div_clks[] __initdata = {
1214 /* DIV_MIF1 */
1215 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1216 DIV_MIF1, 16, 2),
1217 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1218 12, 2),
1219 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1220 8, 2),
1221 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1222 4, 4),
1223
1224 /* DIV_MIF2 */
1225 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1226 DIV_MIF2, 20, 3),
1227 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1228 DIV_MIF2, 16, 4),
1229 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1230 DIV_MIF2, 12, 4),
1231 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1232 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1233 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1234 DIV_MIF2, 4, 2),
1235 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1236 DIV_MIF2, 0, 3),
1237
1238 /* DIV_MIF3 */
1239 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1240 DIV_MIF3, 16, 4),
1241 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1242 DIV_MIF3, 4, 3),
1243 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1244 DIV_MIF3, 0, 3),
1245
1246 /* DIV_MIF4 */
1247 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1248 DIV_MIF4, 24, 4),
1249 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1250 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1251 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1252 DIV_MIF4, 16, 4),
1253 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1254 DIV_MIF4, 12, 4),
1255 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1256 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1257 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1258 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1259 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1260 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1261
1262 /* DIV_MIF5 */
1263 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1264 0, 3),
1265 };
1266
1267 static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1268 /* ENABLE_ACLK_MIF0 */
1269 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1270 19, CLK_IGNORE_UNUSED, 0),
1271 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1272 18, CLK_IGNORE_UNUSED, 0),
1273 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1274 17, CLK_IGNORE_UNUSED, 0),
1275 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1276 16, CLK_IGNORE_UNUSED, 0),
1277 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1278 15, CLK_IGNORE_UNUSED, 0),
1279 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1280 14, CLK_IGNORE_UNUSED, 0),
1281 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1282 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1283 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1284 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1285 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1286 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1287 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1288 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1289 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1290 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1291 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1292 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1293 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1294 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1295 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1296 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1297 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1298 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1299 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1300 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1301 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1302 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1303 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1304 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1305 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1306 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1307 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1308 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1309
1310 /* ENABLE_ACLK_MIF1 */
1311 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1312 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1313 CLK_IGNORE_UNUSED, 0),
1314 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1315 "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1316 27, CLK_IGNORE_UNUSED, 0),
1317 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1318 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1319 26, CLK_IGNORE_UNUSED, 0),
1320 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1321 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1322 25, CLK_IGNORE_UNUSED, 0),
1323 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1324 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1325 24, CLK_IGNORE_UNUSED, 0),
1326 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1327 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1328 23, CLK_IGNORE_UNUSED, 0),
1329 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1330 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1331 22, CLK_IGNORE_UNUSED, 0),
1332 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1333 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1334 21, CLK_IGNORE_UNUSED, 0),
1335 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1336 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1337 20, CLK_IGNORE_UNUSED, 0),
1338 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1339 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1340 19, CLK_IGNORE_UNUSED, 0),
1341 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1342 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1343 18, CLK_IGNORE_UNUSED, 0),
1344 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1345 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1346 17, CLK_IGNORE_UNUSED, 0),
1347 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1348 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1349 16, CLK_IGNORE_UNUSED, 0),
1350 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1351 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1352 15, CLK_IGNORE_UNUSED, 0),
1353 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1354 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1355 14, CLK_IGNORE_UNUSED, 0),
1356 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1357 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1358 13, CLK_IGNORE_UNUSED, 0),
1359 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1360 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1361 12, CLK_IGNORE_UNUSED, 0),
1362 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1363 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1364 11, CLK_IGNORE_UNUSED, 0),
1365 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1366 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1367 10, CLK_IGNORE_UNUSED, 0),
1368 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1369 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1370 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1371 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1372 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1373 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1374 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1375 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1376 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1377 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1378 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1379 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1380 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1381 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1382 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1383 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1384 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1385 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1386 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1387 0, CLK_IGNORE_UNUSED, 0),
1388
1389 /* ENABLE_ACLK_MIF2 */
1390 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1391 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1392 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1393 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1394 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1395 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1396 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1397 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1398 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1399 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1400 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1401 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1402 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1403 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1404 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1405 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1406 CLK_IGNORE_UNUSED, 0),
1407 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1408 "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1409 5, CLK_IGNORE_UNUSED, 0),
1410 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1411 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1412 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1413 "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1414 3, CLK_IGNORE_UNUSED, 0),
1415 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1416 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1417
1418 /* ENABLE_ACLK_MIF3 */
1419 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1420 ENABLE_ACLK_MIF3, 4,
1421 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1422 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1423 ENABLE_ACLK_MIF3, 1,
1424 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1425 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1426 ENABLE_ACLK_MIF3, 0,
1427 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1428
1429 /* ENABLE_PCLK_MIF */
1430 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1431 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1432 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1433 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1434 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1435 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1436 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1437 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1438 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1439 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1440 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1441 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1442 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1443 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1444 CLK_IGNORE_UNUSED, 0),
1445 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1446 ENABLE_PCLK_MIF, 19, 0, 0),
1447 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1448 ENABLE_PCLK_MIF, 18, 0, 0),
1449 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1450 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1451 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1452 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1453 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1454 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1455 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1456 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1457 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1458 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1459 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1460 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1461 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1462 ENABLE_PCLK_MIF, 11, 0, 0),
1463 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1464 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1465 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1466 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1467 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1468 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1469 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1470 ENABLE_PCLK_MIF, 7, 0, 0),
1471 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1472 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1473 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1474 ENABLE_PCLK_MIF, 5, 0, 0),
1475 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1476 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1477 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1478 ENABLE_PCLK_MIF, 2, 0, 0),
1479 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1480 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1481
1482 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1483 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1484 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
1485
1486 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1487 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1488 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
1489
1490 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1491 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1492 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1493
1494 /* ENABLE_PCLK_MIF_SECURE_RTC */
1495 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1496 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1497
1498 /* ENABLE_SCLK_MIF */
1499 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1500 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1501 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1502 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1503 14, CLK_IGNORE_UNUSED, 0),
1504 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1505 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1506 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1507 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1508 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1509 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1510 7, CLK_IGNORE_UNUSED, 0),
1511 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1512 "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1513 6, CLK_IGNORE_UNUSED, 0),
1514 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1515 "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1516 5, CLK_IGNORE_UNUSED, 0),
1517 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1518 ENABLE_SCLK_MIF, 4,
1519 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1520 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1521 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1522 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1523 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1524 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1525 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1526 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1527 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1528 };
1529
1530 static struct samsung_cmu_info mif_cmu_info __initdata = {
1531 .pll_clks = mif_pll_clks,
1532 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1533 .mux_clks = mif_mux_clks,
1534 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1535 .div_clks = mif_div_clks,
1536 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
1537 .gate_clks = mif_gate_clks,
1538 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1539 .fixed_factor_clks = mif_fixed_factor_clks,
1540 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
1541 .nr_clk_ids = MIF_NR_CLK,
1542 .clk_regs = mif_clk_regs,
1543 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
1544 };
1545
1546 static void __init exynos5433_cmu_mif_init(struct device_node *np)
1547 {
1548 samsung_cmu_register_one(np, &mif_cmu_info);
1549 }
1550 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1551 exynos5433_cmu_mif_init);
1552
1553 /*
1554 * Register offset definitions for CMU_PERIC
1555 */
1556 #define DIV_PERIC 0x0600
1557 #define DIV_STAT_PERIC 0x0700
1558 #define ENABLE_ACLK_PERIC 0x0800
1559 #define ENABLE_PCLK_PERIC0 0x0900
1560 #define ENABLE_PCLK_PERIC1 0x0904
1561 #define ENABLE_SCLK_PERIC 0x0A00
1562 #define ENABLE_IP_PERIC0 0x0B00
1563 #define ENABLE_IP_PERIC1 0x0B04
1564 #define ENABLE_IP_PERIC2 0x0B08
1565
1566 static unsigned long peric_clk_regs[] __initdata = {
1567 DIV_PERIC,
1568 DIV_STAT_PERIC,
1569 ENABLE_ACLK_PERIC,
1570 ENABLE_PCLK_PERIC0,
1571 ENABLE_PCLK_PERIC1,
1572 ENABLE_SCLK_PERIC,
1573 ENABLE_IP_PERIC0,
1574 ENABLE_IP_PERIC1,
1575 ENABLE_IP_PERIC2,
1576 };
1577
1578 static struct samsung_div_clock peric_div_clks[] __initdata = {
1579 /* DIV_PERIC */
1580 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1581 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1582 };
1583
1584 static struct samsung_gate_clock peric_gate_clks[] __initdata = {
1585 /* ENABLE_ACLK_PERIC */
1586 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1587 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1588 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1589 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1590 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1591 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1592 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1593 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1594
1595 /* ENABLE_PCLK_PERIC0 */
1596 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1597 31, CLK_SET_RATE_PARENT, 0),
1598 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1599 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1600 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1601 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1602 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1603 28, CLK_SET_RATE_PARENT, 0),
1604 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1605 26, CLK_SET_RATE_PARENT, 0),
1606 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1607 25, CLK_SET_RATE_PARENT, 0),
1608 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1609 24, CLK_SET_RATE_PARENT, 0),
1610 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1611 23, CLK_SET_RATE_PARENT, 0),
1612 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1613 22, CLK_SET_RATE_PARENT, 0),
1614 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1615 21, CLK_SET_RATE_PARENT, 0),
1616 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1617 20, CLK_SET_RATE_PARENT, 0),
1618 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1619 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1620 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1621 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1622 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1623 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1624 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1625 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1626 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1627 ENABLE_PCLK_PERIC0, 15,
1628 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1629 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1630 14, CLK_SET_RATE_PARENT, 0),
1631 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1632 13, CLK_SET_RATE_PARENT, 0),
1633 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1634 12, CLK_SET_RATE_PARENT, 0),
1635 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1636 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1637 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1638 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1639 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1640 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1641 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1642 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1643 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1644 7, CLK_SET_RATE_PARENT, 0),
1645 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1646 6, CLK_SET_RATE_PARENT, 0),
1647 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1648 5, CLK_SET_RATE_PARENT, 0),
1649 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1650 4, CLK_SET_RATE_PARENT, 0),
1651 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1652 3, CLK_SET_RATE_PARENT, 0),
1653 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1654 2, CLK_SET_RATE_PARENT, 0),
1655 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1656 1, CLK_SET_RATE_PARENT, 0),
1657 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1658 0, CLK_SET_RATE_PARENT, 0),
1659
1660 /* ENABLE_PCLK_PERIC1 */
1661 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1662 9, CLK_SET_RATE_PARENT, 0),
1663 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1664 8, CLK_SET_RATE_PARENT, 0),
1665 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1666 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1667 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1668 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1669 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1670 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1671 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1672 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1673 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1674 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1675 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1676 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1677 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1678 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1679 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1680 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1681
1682 /* ENABLE_SCLK_PERIC */
1683 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1684 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1685 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1686 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1687 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1688 19, CLK_SET_RATE_PARENT, 0),
1689 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1690 18, CLK_SET_RATE_PARENT, 0),
1691 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1692 17, 0, 0),
1693 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1694 16, 0, 0),
1695 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1696 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1697 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1698 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1699 ENABLE_SCLK_PERIC, 12,
1700 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1701 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1702 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1703 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1704 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1705 CLK_SET_RATE_PARENT, 0),
1706 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1707 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1708 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1709 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1710 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1711 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1712 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1713 5, CLK_SET_RATE_PARENT, 0),
1714 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1715 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1716 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1717 3, CLK_SET_RATE_PARENT, 0),
1718 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1719 ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
1720 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1721 ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
1722 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1723 ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
1724 };
1725
1726 static struct samsung_cmu_info peric_cmu_info __initdata = {
1727 .div_clks = peric_div_clks,
1728 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
1729 .gate_clks = peric_gate_clks,
1730 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
1731 .nr_clk_ids = PERIC_NR_CLK,
1732 .clk_regs = peric_clk_regs,
1733 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
1734 };
1735
1736 static void __init exynos5433_cmu_peric_init(struct device_node *np)
1737 {
1738 samsung_cmu_register_one(np, &peric_cmu_info);
1739 }
1740
1741 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1742 exynos5433_cmu_peric_init);
1743
1744 /*
1745 * Register offset definitions for CMU_PERIS
1746 */
1747 #define ENABLE_ACLK_PERIS 0x0800
1748 #define ENABLE_PCLK_PERIS 0x0900
1749 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1750 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1751 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1752 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1753 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1754 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1755 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1756 #define ENABLE_SCLK_PERIS 0x0a00
1757 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1758 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1759 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1760 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1761 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1762 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1763 #define ENABLE_IP_PERIS0 0x0b00
1764 #define ENABLE_IP_PERIS1 0x0b04
1765 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1766 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1767 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1768 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1769 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1770 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1771 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1772
1773 static unsigned long peris_clk_regs[] __initdata = {
1774 ENABLE_ACLK_PERIS,
1775 ENABLE_PCLK_PERIS,
1776 ENABLE_PCLK_PERIS_SECURE_TZPC,
1777 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1778 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1779 ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1780 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1781 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1782 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1783 ENABLE_SCLK_PERIS,
1784 ENABLE_SCLK_PERIS_SECURE_SECKEY,
1785 ENABLE_SCLK_PERIS_SECURE_CHIPID,
1786 ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1787 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1788 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1789 ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1790 ENABLE_IP_PERIS0,
1791 ENABLE_IP_PERIS1,
1792 ENABLE_IP_PERIS_SECURE_TZPC,
1793 ENABLE_IP_PERIS_SECURE_SECKEY,
1794 ENABLE_IP_PERIS_SECURE_CHIPID,
1795 ENABLE_IP_PERIS_SECURE_TOPRTC,
1796 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1797 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1798 ENABLE_IP_PERIS_SECURE_OTP_CON,
1799 };
1800
1801 static struct samsung_gate_clock peris_gate_clks[] __initdata = {
1802 /* ENABLE_ACLK_PERIS */
1803 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1804 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1805 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1806 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1807 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1808 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1809
1810 /* ENABLE_PCLK_PERIS */
1811 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1812 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1813 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1814 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1815 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1816 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1817 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1818 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1819 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1820 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1821 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1822 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1823 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1824 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1825 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1826 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1827 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1828 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1829 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1830 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1831
1832 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1833 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1834 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1835 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1836 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1837 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1838 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1839 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1840 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1841 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1842 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1843 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1844 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1845 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1846 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1847 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1848 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1849 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1850 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1851 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1852 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1853 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1854 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1855 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1856 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1857 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1858 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1859
1860 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1861 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1862 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1863
1864 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1865 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1866 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1867
1868 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1869 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1870 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1871
1872 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1873 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1874 "aclk_peris_66",
1875 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1876
1877 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1878 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1879 "aclk_peris_66",
1880 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1881
1882 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1883 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1884 "aclk_peris_66",
1885 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1886
1887 /* ENABLE_SCLK_PERIS */
1888 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1889 ENABLE_SCLK_PERIS, 10, 0, 0),
1890 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1891 ENABLE_SCLK_PERIS, 4, 0, 0),
1892 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1893 ENABLE_SCLK_PERIS, 3, 0, 0),
1894
1895 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1896 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1897 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1898
1899 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1900 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1901 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1902
1903 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1904 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1905 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1906
1907 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1908 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1909 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1910
1911 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1912 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1913 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1914
1915 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1916 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1917 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1918 };
1919
1920 static struct samsung_cmu_info peris_cmu_info __initdata = {
1921 .gate_clks = peris_gate_clks,
1922 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1923 .nr_clk_ids = PERIS_NR_CLK,
1924 .clk_regs = peris_clk_regs,
1925 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1926 };
1927
1928 static void __init exynos5433_cmu_peris_init(struct device_node *np)
1929 {
1930 samsung_cmu_register_one(np, &peris_cmu_info);
1931 }
1932
1933 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1934 exynos5433_cmu_peris_init);
1935
1936 /*
1937 * Register offset definitions for CMU_FSYS
1938 */
1939 #define MUX_SEL_FSYS0 0x0200
1940 #define MUX_SEL_FSYS1 0x0204
1941 #define MUX_SEL_FSYS2 0x0208
1942 #define MUX_SEL_FSYS3 0x020c
1943 #define MUX_SEL_FSYS4 0x0210
1944 #define MUX_ENABLE_FSYS0 0x0300
1945 #define MUX_ENABLE_FSYS1 0x0304
1946 #define MUX_ENABLE_FSYS2 0x0308
1947 #define MUX_ENABLE_FSYS3 0x030c
1948 #define MUX_ENABLE_FSYS4 0x0310
1949 #define MUX_STAT_FSYS0 0x0400
1950 #define MUX_STAT_FSYS1 0x0404
1951 #define MUX_STAT_FSYS2 0x0408
1952 #define MUX_STAT_FSYS3 0x040c
1953 #define MUX_STAT_FSYS4 0x0410
1954 #define MUX_IGNORE_FSYS2 0x0508
1955 #define MUX_IGNORE_FSYS3 0x050c
1956 #define ENABLE_ACLK_FSYS0 0x0800
1957 #define ENABLE_ACLK_FSYS1 0x0804
1958 #define ENABLE_PCLK_FSYS 0x0900
1959 #define ENABLE_SCLK_FSYS 0x0a00
1960 #define ENABLE_IP_FSYS0 0x0b00
1961 #define ENABLE_IP_FSYS1 0x0b04
1962
1963 /* list of all parent clock list */
1964 PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
1965 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", };
1966 PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
1967 PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
1968 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1969 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1970 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
1971 PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
1972 PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
1973
1974 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1975 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1976 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1977 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1978 PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1979 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1980 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1981 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1982 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1983 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1984 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1985 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1986 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1987 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1988 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1989 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1990 PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1991 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1992 PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1993 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1994 PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1995 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1996 PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
1997 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
1998 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
1999 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
2000 PNAME(mout_sclk_mphy_p)
2001 = { "mout_sclk_ufs_mphy_user",
2002 "mout_phyclk_lli_mphy_to_ufs_user", };
2003
2004 static unsigned long fsys_clk_regs[] __initdata = {
2005 MUX_SEL_FSYS0,
2006 MUX_SEL_FSYS1,
2007 MUX_SEL_FSYS2,
2008 MUX_SEL_FSYS3,
2009 MUX_SEL_FSYS4,
2010 MUX_ENABLE_FSYS0,
2011 MUX_ENABLE_FSYS1,
2012 MUX_ENABLE_FSYS2,
2013 MUX_ENABLE_FSYS3,
2014 MUX_ENABLE_FSYS4,
2015 MUX_STAT_FSYS0,
2016 MUX_STAT_FSYS1,
2017 MUX_STAT_FSYS2,
2018 MUX_STAT_FSYS3,
2019 MUX_STAT_FSYS4,
2020 MUX_IGNORE_FSYS2,
2021 MUX_IGNORE_FSYS3,
2022 ENABLE_ACLK_FSYS0,
2023 ENABLE_ACLK_FSYS1,
2024 ENABLE_PCLK_FSYS,
2025 ENABLE_SCLK_FSYS,
2026 ENABLE_IP_FSYS0,
2027 ENABLE_IP_FSYS1,
2028 };
2029
2030 static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
2031 /* PHY clocks from USBDRD30_PHY */
2032 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
2033 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
2034 CLK_IS_ROOT, 60000000),
2035 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
2036 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
2037 CLK_IS_ROOT, 125000000),
2038 /* PHY clocks from USBHOST30_PHY */
2039 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
2040 "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
2041 CLK_IS_ROOT, 60000000),
2042 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
2043 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
2044 CLK_IS_ROOT, 125000000),
2045 /* PHY clocks from USBHOST20_PHY */
2046 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2047 "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT,
2048 60000000),
2049 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2050 "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT,
2051 60000000),
2052 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2053 "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2054 CLK_IS_ROOT, 48000000),
2055 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2056 "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT,
2057 60000000),
2058 /* PHY clocks from UFS_PHY */
2059 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2060 NULL, CLK_IS_ROOT, 300000000),
2061 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2062 NULL, CLK_IS_ROOT, 300000000),
2063 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2064 NULL, CLK_IS_ROOT, 300000000),
2065 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2066 NULL, CLK_IS_ROOT, 300000000),
2067 /* PHY clocks from LLI_PHY */
2068 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2069 NULL, CLK_IS_ROOT, 26000000),
2070 };
2071
2072 static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
2073 /* MUX_SEL_FSYS0 */
2074 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2075 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2076 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2077 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2078
2079 /* MUX_SEL_FSYS1 */
2080 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2081 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2082 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2083 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2084 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2085 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2086 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2087 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2088 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2089 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2090 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2091 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2092 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2093 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2094
2095 /* MUX_SEL_FSYS2 */
2096 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2097 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2098 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2099 MUX_SEL_FSYS2, 28, 1),
2100 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2101 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2102 mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2103 MUX_SEL_FSYS2, 24, 1),
2104 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2105 "mout_phyclk_usbhost20_phy_hsic1",
2106 mout_phyclk_usbhost20_phy_hsic1_p,
2107 MUX_SEL_FSYS2, 20, 1),
2108 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2109 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2110 mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2111 MUX_SEL_FSYS2, 16, 1),
2112 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2113 "mout_phyclk_usbhost20_phy_phyclock_user",
2114 mout_phyclk_usbhost20_phy_phyclock_user_p,
2115 MUX_SEL_FSYS2, 12, 1),
2116 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2117 "mout_phyclk_usbhost20_phy_freeclk_user",
2118 mout_phyclk_usbhost20_phy_freeclk_user_p,
2119 MUX_SEL_FSYS2, 8, 1),
2120 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2121 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2122 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2123 MUX_SEL_FSYS2, 4, 1),
2124 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2125 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2126 mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2127 MUX_SEL_FSYS2, 0, 1),
2128
2129 /* MUX_SEL_FSYS3 */
2130 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2131 "mout_phyclk_ufs_rx1_symbol_user",
2132 mout_phyclk_ufs_rx1_symbol_user_p,
2133 MUX_SEL_FSYS3, 16, 1),
2134 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2135 "mout_phyclk_ufs_rx0_symbol_user",
2136 mout_phyclk_ufs_rx0_symbol_user_p,
2137 MUX_SEL_FSYS3, 12, 1),
2138 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2139 "mout_phyclk_ufs_tx1_symbol_user",
2140 mout_phyclk_ufs_tx1_symbol_user_p,
2141 MUX_SEL_FSYS3, 8, 1),
2142 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2143 "mout_phyclk_ufs_tx0_symbol_user",
2144 mout_phyclk_ufs_tx0_symbol_user_p,
2145 MUX_SEL_FSYS3, 4, 1),
2146 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2147 "mout_phyclk_lli_mphy_to_ufs_user",
2148 mout_phyclk_lli_mphy_to_ufs_user_p,
2149 MUX_SEL_FSYS3, 0, 1),
2150
2151 /* MUX_SEL_FSYS4 */
2152 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2153 MUX_SEL_FSYS4, 0, 1),
2154 };
2155
2156 static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2157 /* ENABLE_ACLK_FSYS0 */
2158 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2159 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2160 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2161 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2162 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2163 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2164 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2165 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2166 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2167 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2168 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2169 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2170 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2171 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2172 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2173 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2174 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2175 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2176 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2177 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2178 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2179 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2180
2181 /* ENABLE_ACLK_FSYS1 */
2182 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2183 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2184 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2185 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2186 26, CLK_IGNORE_UNUSED, 0),
2187 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2188 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2189 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2190 ENABLE_ACLK_FSYS1, 24, 0, 0),
2191 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2192 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2193 22, CLK_IGNORE_UNUSED, 0),
2194 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2195 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2196 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2197 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2198 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2199 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2200 13, 0, 0),
2201 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2202 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2203 12, 0, 0),
2204 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2205 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2206 11, CLK_IGNORE_UNUSED, 0),
2207 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2208 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2209 10, CLK_IGNORE_UNUSED, 0),
2210 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2211 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2212 9, CLK_IGNORE_UNUSED, 0),
2213 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2214 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2215 8, CLK_IGNORE_UNUSED, 0),
2216 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2217 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2218 7, CLK_IGNORE_UNUSED, 0),
2219 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2220 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2221 6, CLK_IGNORE_UNUSED, 0),
2222 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2223 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2224 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2225 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2226 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2227 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2228 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2229 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2230 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2231 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2232 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2233 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2234
2235 /* ENABLE_PCLK_FSYS */
2236 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2237 ENABLE_PCLK_FSYS, 17, 0, 0),
2238 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2239 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2240 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2241 ENABLE_PCLK_FSYS, 14, 0, 0),
2242 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2243 ENABLE_PCLK_FSYS, 13, 0, 0),
2244 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2245 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2246 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2247 ENABLE_PCLK_FSYS, 5, 0, 0),
2248 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2249 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2250 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2251 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2252 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2253 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2254 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2255 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2256 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2257 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2258 0, CLK_IGNORE_UNUSED, 0),
2259
2260 /* ENABLE_SCLK_FSYS */
2261 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2262 ENABLE_SCLK_FSYS, 21, 0, 0),
2263 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2264 "phyclk_usbhost30_uhost30_pipe_pclk",
2265 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2266 ENABLE_SCLK_FSYS, 18, 0, 0),
2267 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2268 "phyclk_usbhost30_uhost30_phyclock",
2269 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2270 ENABLE_SCLK_FSYS, 17, 0, 0),
2271 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2272 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2273 16, 0, 0),
2274 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2275 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2276 15, 0, 0),
2277 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2278 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2279 14, 0, 0),
2280 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2281 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2282 13, 0, 0),
2283 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2284 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2285 12, 0, 0),
2286 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2287 "phyclk_usbhost20_phy_clk48mohci",
2288 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2289 ENABLE_SCLK_FSYS, 11, 0, 0),
2290 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2291 "phyclk_usbhost20_phy_phyclock",
2292 "mout_phyclk_usbhost20_phy_phyclock_user",
2293 ENABLE_SCLK_FSYS, 10, 0, 0),
2294 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2295 "phyclk_usbhost20_phy_freeclk",
2296 "mout_phyclk_usbhost20_phy_freeclk_user",
2297 ENABLE_SCLK_FSYS, 9, 0, 0),
2298 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2299 "phyclk_usbdrd30_udrd30_pipe_pclk",
2300 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2301 ENABLE_SCLK_FSYS, 8, 0, 0),
2302 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2303 "phyclk_usbdrd30_udrd30_phyclock",
2304 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2305 ENABLE_SCLK_FSYS, 7, 0, 0),
2306 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2307 ENABLE_SCLK_FSYS, 6, 0, 0),
2308 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2309 ENABLE_SCLK_FSYS, 5, 0, 0),
2310 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2311 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2312 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2313 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2314 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2315 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2316 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2317 ENABLE_SCLK_FSYS, 1, 0, 0),
2318 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2319 ENABLE_SCLK_FSYS, 0, 0, 0),
2320
2321 /* ENABLE_IP_FSYS0 */
2322 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2323 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2324 };
2325
2326 static struct samsung_cmu_info fsys_cmu_info __initdata = {
2327 .mux_clks = fsys_mux_clks,
2328 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2329 .gate_clks = fsys_gate_clks,
2330 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
2331 .fixed_clks = fsys_fixed_clks,
2332 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
2333 .nr_clk_ids = FSYS_NR_CLK,
2334 .clk_regs = fsys_clk_regs,
2335 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
2336 };
2337
2338 static void __init exynos5433_cmu_fsys_init(struct device_node *np)
2339 {
2340 samsung_cmu_register_one(np, &fsys_cmu_info);
2341 }
2342
2343 CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2344 exynos5433_cmu_fsys_init);
2345
2346 /*
2347 * Register offset definitions for CMU_G2D
2348 */
2349 #define MUX_SEL_G2D0 0x0200
2350 #define MUX_SEL_ENABLE_G2D0 0x0300
2351 #define MUX_SEL_STAT_G2D0 0x0400
2352 #define DIV_G2D 0x0600
2353 #define DIV_STAT_G2D 0x0700
2354 #define DIV_ENABLE_ACLK_G2D 0x0800
2355 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2356 #define DIV_ENABLE_PCLK_G2D 0x0900
2357 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2358 #define DIV_ENABLE_IP_G2D0 0x0b00
2359 #define DIV_ENABLE_IP_G2D1 0x0b04
2360 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2361
2362 static unsigned long g2d_clk_regs[] __initdata = {
2363 MUX_SEL_G2D0,
2364 MUX_SEL_ENABLE_G2D0,
2365 MUX_SEL_STAT_G2D0,
2366 DIV_G2D,
2367 DIV_STAT_G2D,
2368 DIV_ENABLE_ACLK_G2D,
2369 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2370 DIV_ENABLE_PCLK_G2D,
2371 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2372 DIV_ENABLE_IP_G2D0,
2373 DIV_ENABLE_IP_G2D1,
2374 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2375 };
2376
2377 /* list of all parent clock list */
2378 PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2379 PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2380
2381 static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
2382 /* MUX_SEL_G2D0 */
2383 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2384 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2385 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2386 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2387 };
2388
2389 static struct samsung_div_clock g2d_div_clks[] __initdata = {
2390 /* DIV_G2D */
2391 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2392 DIV_G2D, 0, 2),
2393 };
2394
2395 static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
2396 /* DIV_ENABLE_ACLK_G2D */
2397 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2398 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2399 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2400 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2401 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2402 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2403 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2404 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2405 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2406 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2407 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2408 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2409 7, 0, 0),
2410 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2411 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2412 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2413 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2414 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2415 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2416 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2417 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2418 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2419 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2420 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2421 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2422 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2423 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2424
2425 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2426 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2427 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2428
2429 /* DIV_ENABLE_PCLK_G2D */
2430 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2431 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2432 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2433 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2434 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2435 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2436 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2437 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2438 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2439 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2440 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2441 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2442 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2443 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2444 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2445 0, 0, 0),
2446
2447 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2448 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2449 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2450 };
2451
2452 static struct samsung_cmu_info g2d_cmu_info __initdata = {
2453 .mux_clks = g2d_mux_clks,
2454 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2455 .div_clks = g2d_div_clks,
2456 .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
2457 .gate_clks = g2d_gate_clks,
2458 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
2459 .nr_clk_ids = G2D_NR_CLK,
2460 .clk_regs = g2d_clk_regs,
2461 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
2462 };
2463
2464 static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2465 {
2466 samsung_cmu_register_one(np, &g2d_cmu_info);
2467 }
2468
2469 CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2470 exynos5433_cmu_g2d_init);
2471
2472 /*
2473 * Register offset definitions for CMU_DISP
2474 */
2475 #define DISP_PLL_LOCK 0x0000
2476 #define DISP_PLL_CON0 0x0100
2477 #define DISP_PLL_CON1 0x0104
2478 #define DISP_PLL_FREQ_DET 0x0108
2479 #define MUX_SEL_DISP0 0x0200
2480 #define MUX_SEL_DISP1 0x0204
2481 #define MUX_SEL_DISP2 0x0208
2482 #define MUX_SEL_DISP3 0x020c
2483 #define MUX_SEL_DISP4 0x0210
2484 #define MUX_ENABLE_DISP0 0x0300
2485 #define MUX_ENABLE_DISP1 0x0304
2486 #define MUX_ENABLE_DISP2 0x0308
2487 #define MUX_ENABLE_DISP3 0x030c
2488 #define MUX_ENABLE_DISP4 0x0310
2489 #define MUX_STAT_DISP0 0x0400
2490 #define MUX_STAT_DISP1 0x0404
2491 #define MUX_STAT_DISP2 0x0408
2492 #define MUX_STAT_DISP3 0x040c
2493 #define MUX_STAT_DISP4 0x0410
2494 #define MUX_IGNORE_DISP2 0x0508
2495 #define DIV_DISP 0x0600
2496 #define DIV_DISP_PLL_FREQ_DET 0x0604
2497 #define DIV_STAT_DISP 0x0700
2498 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2499 #define ENABLE_ACLK_DISP0 0x0800
2500 #define ENABLE_ACLK_DISP1 0x0804
2501 #define ENABLE_PCLK_DISP 0x0900
2502 #define ENABLE_SCLK_DISP 0x0a00
2503 #define ENABLE_IP_DISP0 0x0b00
2504 #define ENABLE_IP_DISP1 0x0b04
2505 #define CLKOUT_CMU_DISP 0x0c00
2506 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2507
2508 static unsigned long disp_clk_regs[] __initdata = {
2509 DISP_PLL_LOCK,
2510 DISP_PLL_CON0,
2511 DISP_PLL_CON1,
2512 DISP_PLL_FREQ_DET,
2513 MUX_SEL_DISP0,
2514 MUX_SEL_DISP1,
2515 MUX_SEL_DISP2,
2516 MUX_SEL_DISP3,
2517 MUX_SEL_DISP4,
2518 MUX_ENABLE_DISP0,
2519 MUX_ENABLE_DISP1,
2520 MUX_ENABLE_DISP2,
2521 MUX_ENABLE_DISP3,
2522 MUX_ENABLE_DISP4,
2523 MUX_STAT_DISP0,
2524 MUX_STAT_DISP1,
2525 MUX_STAT_DISP2,
2526 MUX_STAT_DISP3,
2527 MUX_STAT_DISP4,
2528 MUX_IGNORE_DISP2,
2529 DIV_DISP,
2530 DIV_DISP_PLL_FREQ_DET,
2531 DIV_STAT_DISP,
2532 DIV_STAT_DISP_PLL_FREQ_DET,
2533 ENABLE_ACLK_DISP0,
2534 ENABLE_ACLK_DISP1,
2535 ENABLE_PCLK_DISP,
2536 ENABLE_SCLK_DISP,
2537 ENABLE_IP_DISP0,
2538 ENABLE_IP_DISP1,
2539 CLKOUT_CMU_DISP,
2540 CLKOUT_CMU_DISP_DIV_STAT,
2541 };
2542
2543 /* list of all parent clock list */
2544 PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2545 PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
2546 PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
2547 PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
2548 PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
2549 "sclk_decon_tv_eclk_disp", };
2550 PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
2551 "sclk_decon_vclk_disp", };
2552 PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
2553 "sclk_decon_eclk_disp", };
2554 PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
2555 "sclk_decon_tv_vclk_disp", };
2556 PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
2557
2558 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
2559 "phyclk_mipidphy1_bitclkdiv8_phy", };
2560 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
2561 "phyclk_mipidphy1_rxclkesc0_phy", };
2562 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
2563 "phyclk_mipidphy0_bitclkdiv8_phy", };
2564 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
2565 "phyclk_mipidphy0_rxclkesc0_phy", };
2566 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2567 "phyclk_hdmiphy_tmds_clko_phy", };
2568 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
2569 "phyclk_hdmiphy_pixel_clko_phy", };
2570
2571 PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
2572 "mout_sclk_dsim0_user", };
2573 PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
2574 "mout_sclk_decon_tv_eclk_user", };
2575 PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
2576 "mout_sclk_decon_vclk_user", };
2577 PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
2578 "mout_sclk_decon_eclk_user", };
2579
2580 PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
2581 "mout_sclk_dsim1_user", };
2582 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2583 "mout_phyclk_hdmiphy_pixel_clko_user",
2584 "mout_sclk_decon_tv_vclk_b_disp", };
2585 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2586 "mout_sclk_decon_tv_vclk_user", };
2587
2588 static struct samsung_pll_clock disp_pll_clks[] __initdata = {
2589 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2590 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2591 };
2592
2593 static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
2594 /*
2595 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2596 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2597 * and sclk_decon_{vclk|tv_vclk}.
2598 */
2599 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2600 1, 2, 0),
2601 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2602 1, 2, 0),
2603 };
2604
2605 static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
2606 /* PHY clocks from MIPI_DPHY1 */
2607 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2608 188000000),
2609 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2610 100000000),
2611 /* PHY clocks from MIPI_DPHY0 */
2612 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2613 188000000),
2614 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2615 100000000),
2616 /* PHY clocks from HDMI_PHY */
2617 FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
2618 FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
2619 };
2620
2621 static struct samsung_mux_clock disp_mux_clks[] __initdata = {
2622 /* MUX_SEL_DISP0 */
2623 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2624 0, 1),
2625
2626 /* MUX_SEL_DISP1 */
2627 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2628 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2629 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2630 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2631 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2632 MUX_SEL_DISP1, 20, 1),
2633 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2634 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2635 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2636 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2637 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2638 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2639 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2640 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2641 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2642 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2643
2644 /* MUX_SEL_DISP2 */
2645 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2646 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2647 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2648 20, 1),
2649 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2650 "mout_phyclk_mipidphy1_rxclkesc0_user",
2651 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2652 16, 1),
2653 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2654 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2655 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2656 12, 1),
2657 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2658 "mout_phyclk_mipidphy0_rxclkesc0_user",
2659 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2660 8, 1),
2661 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2662 "mout_phyclk_hdmiphy_tmds_clko_user",
2663 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2664 4, 1),
2665 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2666 "mout_phyclk_hdmiphy_pixel_clko_user",
2667 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2668 0, 1),
2669
2670 /* MUX_SEL_DISP3 */
2671 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2672 MUX_SEL_DISP3, 12, 1),
2673 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2674 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2675 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2676 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2677 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2678 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2679
2680 /* MUX_SEL_DISP4 */
2681 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2682 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2683 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2684 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2685 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2686 "mout_sclk_decon_tv_vclk_c_disp",
2687 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2688 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2689 "mout_sclk_decon_tv_vclk_b_disp",
2690 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2691 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2692 "mout_sclk_decon_tv_vclk_a_disp",
2693 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2694 };
2695
2696 static struct samsung_div_clock disp_div_clks[] __initdata = {
2697 /* DIV_DISP */
2698 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2699 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2700 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2701 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2702 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2703 DIV_DISP, 16, 3),
2704 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2705 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2706 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2707 "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2708 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2709 "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2710 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2711 DIV_DISP, 0, 2),
2712 };
2713
2714 static struct samsung_gate_clock disp_gate_clks[] __initdata = {
2715 /* ENABLE_ACLK_DISP0 */
2716 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2717 ENABLE_ACLK_DISP0, 2, 0, 0),
2718 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2719 ENABLE_ACLK_DISP0, 0, 0, 0),
2720
2721 /* ENABLE_ACLK_DISP1 */
2722 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2723 ENABLE_ACLK_DISP1, 25, 0, 0),
2724 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2725 ENABLE_ACLK_DISP1, 24, 0, 0),
2726 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2727 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2728 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2729 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2730 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2731 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2732 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2733 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2734 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2735 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2736 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2737 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2738 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2739 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2740 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2741 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2742 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2743 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2744 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2745 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2746 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2747 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2748 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2749 "div_pclk_disp", ENABLE_ACLK_DISP1,
2750 12, CLK_IGNORE_UNUSED, 0),
2751 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2752 "div_pclk_disp", ENABLE_ACLK_DISP1,
2753 11, CLK_IGNORE_UNUSED, 0),
2754 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2755 "div_pclk_disp", ENABLE_ACLK_DISP1,
2756 10, CLK_IGNORE_UNUSED, 0),
2757 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2758 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2759 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2760 ENABLE_ACLK_DISP1, 7, 0, 0),
2761 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2762 ENABLE_ACLK_DISP1, 6, 0, 0),
2763 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2764 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2765 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2766 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2767 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2768 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2769 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2770 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2771 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2772 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2773 CLK_IGNORE_UNUSED, 0),
2774 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2775 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2776 0, CLK_IGNORE_UNUSED, 0),
2777
2778 /* ENABLE_PCLK_DISP */
2779 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2780 ENABLE_PCLK_DISP, 23, 0, 0),
2781 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2782 ENABLE_PCLK_DISP, 22, 0, 0),
2783 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2784 ENABLE_PCLK_DISP, 21, 0, 0),
2785 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2786 ENABLE_PCLK_DISP, 20, 0, 0),
2787 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2788 ENABLE_PCLK_DISP, 19, 0, 0),
2789 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2790 ENABLE_PCLK_DISP, 18, 0, 0),
2791 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2792 ENABLE_PCLK_DISP, 17, 0, 0),
2793 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2794 ENABLE_PCLK_DISP, 16, 0, 0),
2795 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2796 ENABLE_PCLK_DISP, 15, 0, 0),
2797 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2798 ENABLE_PCLK_DISP, 14, 0, 0),
2799 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2800 ENABLE_PCLK_DISP, 13, 0, 0),
2801 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2802 ENABLE_PCLK_DISP, 12, 0, 0),
2803 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2804 ENABLE_PCLK_DISP, 11, 0, 0),
2805 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2806 ENABLE_PCLK_DISP, 10, 0, 0),
2807 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2808 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2809 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2810 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2811 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2812 ENABLE_PCLK_DISP, 7, 0, 0),
2813 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2814 ENABLE_PCLK_DISP, 6, 0, 0),
2815 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2816 ENABLE_PCLK_DISP, 5, 0, 0),
2817 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2818 ENABLE_PCLK_DISP, 3, 0, 0),
2819 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2820 ENABLE_PCLK_DISP, 2, 0, 0),
2821 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2822 ENABLE_PCLK_DISP, 1, 0, 0),
2823
2824 /* ENABLE_SCLK_DISP */
2825 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2826 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2827 ENABLE_SCLK_DISP, 26, 0, 0),
2828 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2829 "mout_phyclk_mipidphy1_rxclkesc0_user",
2830 ENABLE_SCLK_DISP, 25, 0, 0),
2831 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2832 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2833 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2834 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2835 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2836 ENABLE_SCLK_DISP, 22, 0, 0),
2837 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2838 "div_sclk_decon_tv_vclk_disp",
2839 ENABLE_SCLK_DISP, 21, 0, 0),
2840 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2841 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2842 ENABLE_SCLK_DISP, 15, 0, 0),
2843 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2844 "mout_phyclk_mipidphy0_rxclkesc0_user",
2845 ENABLE_SCLK_DISP, 14, 0, 0),
2846 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2847 "mout_phyclk_hdmiphy_tmds_clko_user",
2848 ENABLE_SCLK_DISP, 13, 0, 0),
2849 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2850 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2851 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2852 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2853 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2854 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2855 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2856 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2857 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2858 ENABLE_SCLK_DISP, 7, 0, 0),
2859 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2860 ENABLE_SCLK_DISP, 6, 0, 0),
2861 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2862 ENABLE_SCLK_DISP, 5, 0, 0),
2863 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2864 "div_sclk_decon_tv_eclk_disp",
2865 ENABLE_SCLK_DISP, 4, 0, 0),
2866 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2867 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2868 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2869 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2870 };
2871
2872 static struct samsung_cmu_info disp_cmu_info __initdata = {
2873 .pll_clks = disp_pll_clks,
2874 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2875 .mux_clks = disp_mux_clks,
2876 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
2877 .div_clks = disp_div_clks,
2878 .nr_div_clks = ARRAY_SIZE(disp_div_clks),
2879 .gate_clks = disp_gate_clks,
2880 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
2881 .fixed_clks = disp_fixed_clks,
2882 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
2883 .fixed_factor_clks = disp_fixed_factor_clks,
2884 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
2885 .nr_clk_ids = DISP_NR_CLK,
2886 .clk_regs = disp_clk_regs,
2887 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2888 };
2889
2890 static void __init exynos5433_cmu_disp_init(struct device_node *np)
2891 {
2892 samsung_cmu_register_one(np, &disp_cmu_info);
2893 }
2894
2895 CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2896 exynos5433_cmu_disp_init);
2897
2898 /*
2899 * Register offset definitions for CMU_AUD
2900 */
2901 #define MUX_SEL_AUD0 0x0200
2902 #define MUX_SEL_AUD1 0x0204
2903 #define MUX_ENABLE_AUD0 0x0300
2904 #define MUX_ENABLE_AUD1 0x0304
2905 #define MUX_STAT_AUD0 0x0400
2906 #define DIV_AUD0 0x0600
2907 #define DIV_AUD1 0x0604
2908 #define DIV_STAT_AUD0 0x0700
2909 #define DIV_STAT_AUD1 0x0704
2910 #define ENABLE_ACLK_AUD 0x0800
2911 #define ENABLE_PCLK_AUD 0x0900
2912 #define ENABLE_SCLK_AUD0 0x0a00
2913 #define ENABLE_SCLK_AUD1 0x0a04
2914 #define ENABLE_IP_AUD0 0x0b00
2915 #define ENABLE_IP_AUD1 0x0b04
2916
2917 static unsigned long aud_clk_regs[] __initdata = {
2918 MUX_SEL_AUD0,
2919 MUX_SEL_AUD1,
2920 MUX_ENABLE_AUD0,
2921 MUX_ENABLE_AUD1,
2922 MUX_STAT_AUD0,
2923 DIV_AUD0,
2924 DIV_AUD1,
2925 DIV_STAT_AUD0,
2926 DIV_STAT_AUD1,
2927 ENABLE_ACLK_AUD,
2928 ENABLE_PCLK_AUD,
2929 ENABLE_SCLK_AUD0,
2930 ENABLE_SCLK_AUD1,
2931 ENABLE_IP_AUD0,
2932 ENABLE_IP_AUD1,
2933 };
2934
2935 /* list of all parent clock list */
2936 PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2937 PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2938
2939 static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
2940 FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000),
2941 FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000),
2942 FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000),
2943 };
2944
2945 static struct samsung_mux_clock aud_mux_clks[] __initdata = {
2946 /* MUX_SEL_AUD0 */
2947 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2948 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2949
2950 /* MUX_SEL_AUD1 */
2951 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2952 MUX_SEL_AUD1, 8, 1),
2953 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2954 MUX_SEL_AUD1, 0, 1),
2955 };
2956
2957 static struct samsung_div_clock aud_div_clks[] __initdata = {
2958 /* DIV_AUD0 */
2959 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2960 12, 4),
2961 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2962 8, 4),
2963 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2964 4, 4),
2965 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2966 0, 4),
2967
2968 /* DIV_AUD1 */
2969 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2970 "mout_aud_pll_user", DIV_AUD1, 16, 5),
2971 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2972 DIV_AUD1, 12, 4),
2973 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2974 DIV_AUD1, 4, 8),
2975 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2976 DIV_AUD1, 0, 4),
2977 };
2978
2979 static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2980 /* ENABLE_ACLK_AUD */
2981 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2982 ENABLE_ACLK_AUD, 12, 0, 0),
2983 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2984 ENABLE_ACLK_AUD, 7, 0, 0),
2985 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2986 ENABLE_ACLK_AUD, 0, 4, 0),
2987 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2988 ENABLE_ACLK_AUD, 0, 3, 0),
2989 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2990 ENABLE_ACLK_AUD, 0, 2, 0),
2991 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2992 0, 1, 0),
2993 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
2994 0, CLK_IGNORE_UNUSED, 0),
2995
2996 /* ENABLE_PCLK_AUD */
2997 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2998 13, 0, 0),
2999 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
3000 12, 0, 0),
3001 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
3002 11, 0, 0),
3003 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
3004 ENABLE_PCLK_AUD, 10, 0, 0),
3005 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
3006 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3007 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
3008 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3009 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
3010 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3011 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
3012 ENABLE_PCLK_AUD, 6, 0, 0),
3013 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
3014 ENABLE_PCLK_AUD, 5, 0, 0),
3015 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
3016 ENABLE_PCLK_AUD, 4, 0, 0),
3017 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
3018 ENABLE_PCLK_AUD, 3, 0, 0),
3019 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
3020 2, 0, 0),
3021 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
3022 ENABLE_PCLK_AUD, 0, 0, 0),
3023
3024 /* ENABLE_SCLK_AUD0 */
3025 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
3026 2, 0, 0),
3027 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
3028 ENABLE_SCLK_AUD0, 1, 0, 0),
3029 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
3030 0, 0, 0),
3031
3032 /* ENABLE_SCLK_AUD1 */
3033 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
3034 ENABLE_SCLK_AUD1, 6, 0, 0),
3035 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
3036 ENABLE_SCLK_AUD1, 5, 0, 0),
3037 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
3038 ENABLE_SCLK_AUD1, 4, 0, 0),
3039 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
3040 ENABLE_SCLK_AUD1, 3, 0, 0),
3041 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
3042 ENABLE_SCLK_AUD1, 2, 0, 0),
3043 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
3044 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3045 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
3046 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3047 };
3048
3049 static struct samsung_cmu_info aud_cmu_info __initdata = {
3050 .mux_clks = aud_mux_clks,
3051 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
3052 .div_clks = aud_div_clks,
3053 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
3054 .gate_clks = aud_gate_clks,
3055 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
3056 .fixed_clks = aud_fixed_clks,
3057 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
3058 .nr_clk_ids = AUD_NR_CLK,
3059 .clk_regs = aud_clk_regs,
3060 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
3061 };
3062
3063 static void __init exynos5433_cmu_aud_init(struct device_node *np)
3064 {
3065 samsung_cmu_register_one(np, &aud_cmu_info);
3066 }
3067 CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
3068 exynos5433_cmu_aud_init);
3069
3070
3071 /*
3072 * Register offset definitions for CMU_BUS{0|1|2}
3073 */
3074 #define DIV_BUS 0x0600
3075 #define DIV_STAT_BUS 0x0700
3076 #define ENABLE_ACLK_BUS 0x0800
3077 #define ENABLE_PCLK_BUS 0x0900
3078 #define ENABLE_IP_BUS0 0x0b00
3079 #define ENABLE_IP_BUS1 0x0b04
3080
3081 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3082 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3083 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3084
3085 /* list of all parent clock list */
3086 PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3087
3088 #define CMU_BUS_COMMON_CLK_REGS \
3089 DIV_BUS, \
3090 DIV_STAT_BUS, \
3091 ENABLE_ACLK_BUS, \
3092 ENABLE_PCLK_BUS, \
3093 ENABLE_IP_BUS0, \
3094 ENABLE_IP_BUS1
3095
3096 static unsigned long bus01_clk_regs[] __initdata = {
3097 CMU_BUS_COMMON_CLK_REGS,
3098 };
3099
3100 static unsigned long bus2_clk_regs[] __initdata = {
3101 MUX_SEL_BUS2,
3102 MUX_ENABLE_BUS2,
3103 MUX_STAT_BUS2,
3104 CMU_BUS_COMMON_CLK_REGS,
3105 };
3106
3107 static struct samsung_div_clock bus0_div_clks[] __initdata = {
3108 /* DIV_BUS0 */
3109 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3110 DIV_BUS, 0, 3),
3111 };
3112
3113 /* CMU_BUS0 clocks */
3114 static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
3115 /* ENABLE_ACLK_BUS0 */
3116 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3117 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3118 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3119 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3120 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3121 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3122
3123 /* ENABLE_PCLK_BUS0 */
3124 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3125 ENABLE_PCLK_BUS, 2, 0, 0),
3126 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3127 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3128 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3129 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3130 };
3131
3132 /* CMU_BUS1 clocks */
3133 static struct samsung_div_clock bus1_div_clks[] __initdata = {
3134 /* DIV_BUS1 */
3135 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3136 DIV_BUS, 0, 3),
3137 };
3138
3139 static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
3140 /* ENABLE_ACLK_BUS1 */
3141 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3142 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3143 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3144 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3145 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3146 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3147
3148 /* ENABLE_PCLK_BUS1 */
3149 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3150 ENABLE_PCLK_BUS, 2, 0, 0),
3151 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3152 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3153 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3154 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3155 };
3156
3157 /* CMU_BUS2 clocks */
3158 static struct samsung_mux_clock bus2_mux_clks[] __initdata = {
3159 /* MUX_SEL_BUS2 */
3160 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3161 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3162 };
3163
3164 static struct samsung_div_clock bus2_div_clks[] __initdata = {
3165 /* DIV_BUS2 */
3166 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3167 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3168 };
3169
3170 static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
3171 /* ENABLE_ACLK_BUS2 */
3172 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3173 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3174 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3175 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3176 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3177 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3178 1, CLK_IGNORE_UNUSED, 0),
3179 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3180 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3181 0, CLK_IGNORE_UNUSED, 0),
3182
3183 /* ENABLE_PCLK_BUS2 */
3184 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3185 ENABLE_PCLK_BUS, 2, 0, 0),
3186 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3187 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3188 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3189 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3190 };
3191
3192 #define CMU_BUS_INFO_CLKS(id) \
3193 .div_clks = bus##id##_div_clks, \
3194 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
3195 .gate_clks = bus##id##_gate_clks, \
3196 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3197 .nr_clk_ids = BUSx_NR_CLK
3198
3199 static struct samsung_cmu_info bus0_cmu_info __initdata = {
3200 CMU_BUS_INFO_CLKS(0),
3201 .clk_regs = bus01_clk_regs,
3202 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3203 };
3204
3205 static struct samsung_cmu_info bus1_cmu_info __initdata = {
3206 CMU_BUS_INFO_CLKS(1),
3207 .clk_regs = bus01_clk_regs,
3208 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3209 };
3210
3211 static struct samsung_cmu_info bus2_cmu_info __initdata = {
3212 CMU_BUS_INFO_CLKS(2),
3213 .mux_clks = bus2_mux_clks,
3214 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
3215 .clk_regs = bus2_clk_regs,
3216 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
3217 };
3218
3219 #define exynos5433_cmu_bus_init(id) \
3220 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3221 { \
3222 samsung_cmu_register_one(np, &bus##id##_cmu_info); \
3223 } \
3224 CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
3225 "samsung,exynos5433-cmu-bus"#id, \
3226 exynos5433_cmu_bus##id##_init)
3227
3228 exynos5433_cmu_bus_init(0);
3229 exynos5433_cmu_bus_init(1);
3230 exynos5433_cmu_bus_init(2);
3231
3232 /*
3233 * Register offset definitions for CMU_G3D
3234 */
3235 #define G3D_PLL_LOCK 0x0000
3236 #define G3D_PLL_CON0 0x0100
3237 #define G3D_PLL_CON1 0x0104
3238 #define G3D_PLL_FREQ_DET 0x010c
3239 #define MUX_SEL_G3D 0x0200
3240 #define MUX_ENABLE_G3D 0x0300
3241 #define MUX_STAT_G3D 0x0400
3242 #define DIV_G3D 0x0600
3243 #define DIV_G3D_PLL_FREQ_DET 0x0604
3244 #define DIV_STAT_G3D 0x0700
3245 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3246 #define ENABLE_ACLK_G3D 0x0800
3247 #define ENABLE_PCLK_G3D 0x0900
3248 #define ENABLE_SCLK_G3D 0x0a00
3249 #define ENABLE_IP_G3D0 0x0b00
3250 #define ENABLE_IP_G3D1 0x0b04
3251 #define CLKOUT_CMU_G3D 0x0c00
3252 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3253 #define CLK_STOPCTRL 0x1000
3254
3255 static unsigned long g3d_clk_regs[] __initdata = {
3256 G3D_PLL_LOCK,
3257 G3D_PLL_CON0,
3258 G3D_PLL_CON1,
3259 G3D_PLL_FREQ_DET,
3260 MUX_SEL_G3D,
3261 MUX_ENABLE_G3D,
3262 MUX_STAT_G3D,
3263 DIV_G3D,
3264 DIV_G3D_PLL_FREQ_DET,
3265 DIV_STAT_G3D,
3266 DIV_STAT_G3D_PLL_FREQ_DET,
3267 ENABLE_ACLK_G3D,
3268 ENABLE_PCLK_G3D,
3269 ENABLE_SCLK_G3D,
3270 ENABLE_IP_G3D0,
3271 ENABLE_IP_G3D1,
3272 CLKOUT_CMU_G3D,
3273 CLKOUT_CMU_G3D_DIV_STAT,
3274 CLK_STOPCTRL,
3275 };
3276
3277 /* list of all parent clock list */
3278 PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3279 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3280
3281 static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
3282 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3283 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
3284 };
3285
3286 static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
3287 /* MUX_SEL_G3D */
3288 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3289 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3290 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3291 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3292 };
3293
3294 static struct samsung_div_clock g3d_div_clks[] __initdata = {
3295 /* DIV_G3D */
3296 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3297 8, 2),
3298 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3299 4, 3),
3300 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3301 0, 3, CLK_SET_RATE_PARENT, 0),
3302 };
3303
3304 static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
3305 /* ENABLE_ACLK_G3D */
3306 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3307 ENABLE_ACLK_G3D, 7, 0, 0),
3308 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3309 ENABLE_ACLK_G3D, 6, 0, 0),
3310 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3311 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3312 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3313 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3314 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3315 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3316 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3317 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3318 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3319 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3320 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3321 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3322
3323 /* ENABLE_PCLK_G3D */
3324 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3325 ENABLE_PCLK_G3D, 3, 0, 0),
3326 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3327 ENABLE_PCLK_G3D, 2, 0, 0),
3328 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3329 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3330 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3331 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3332
3333 /* ENABLE_SCLK_G3D */
3334 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3335 ENABLE_SCLK_G3D, 0, 0, 0),
3336 };
3337
3338 static struct samsung_cmu_info g3d_cmu_info __initdata = {
3339 .pll_clks = g3d_pll_clks,
3340 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3341 .mux_clks = g3d_mux_clks,
3342 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
3343 .div_clks = g3d_div_clks,
3344 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
3345 .gate_clks = g3d_gate_clks,
3346 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
3347 .nr_clk_ids = G3D_NR_CLK,
3348 .clk_regs = g3d_clk_regs,
3349 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
3350 };
3351
3352 static void __init exynos5433_cmu_g3d_init(struct device_node *np)
3353 {
3354 samsung_cmu_register_one(np, &g3d_cmu_info);
3355 }
3356 CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3357 exynos5433_cmu_g3d_init);
3358
3359 /*
3360 * Register offset definitions for CMU_GSCL
3361 */
3362 #define MUX_SEL_GSCL 0x0200
3363 #define MUX_ENABLE_GSCL 0x0300
3364 #define MUX_STAT_GSCL 0x0400
3365 #define ENABLE_ACLK_GSCL 0x0800
3366 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3367 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3368 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3369 #define ENABLE_PCLK_GSCL 0x0900
3370 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3371 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3372 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3373 #define ENABLE_IP_GSCL0 0x0b00
3374 #define ENABLE_IP_GSCL1 0x0b04
3375 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3376 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3377 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3378
3379 static unsigned long gscl_clk_regs[] __initdata = {
3380 MUX_SEL_GSCL,
3381 MUX_ENABLE_GSCL,
3382 MUX_STAT_GSCL,
3383 ENABLE_ACLK_GSCL,
3384 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3385 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3386 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3387 ENABLE_PCLK_GSCL,
3388 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3389 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3390 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3391 ENABLE_IP_GSCL0,
3392 ENABLE_IP_GSCL1,
3393 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3394 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3395 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3396 };
3397
3398 /* list of all parent clock list */
3399 PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3400 PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3401
3402 static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
3403 /* MUX_SEL_GSCL */
3404 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3405 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3406 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3407 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3408 };
3409
3410 static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
3411 /* ENABLE_ACLK_GSCL */
3412 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3413 ENABLE_ACLK_GSCL, 11, 0, 0),
3414 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3415 ENABLE_ACLK_GSCL, 10, 0, 0),
3416 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3417 ENABLE_ACLK_GSCL, 9, 0, 0),
3418 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3419 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3420 8, CLK_IGNORE_UNUSED, 0),
3421 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3422 ENABLE_ACLK_GSCL, 7, 0, 0),
3423 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3424 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3425 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3426 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
3427 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3428 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
3429 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3430 ENABLE_ACLK_GSCL, 3, 0, 0),
3431 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3432 ENABLE_ACLK_GSCL, 2, 0, 0),
3433 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3434 ENABLE_ACLK_GSCL, 1, 0, 0),
3435 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3436 ENABLE_ACLK_GSCL, 0, 0, 0),
3437
3438 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3439 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3440 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3441
3442 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3443 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3444 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3445
3446 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3447 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3448 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3449
3450 /* ENABLE_PCLK_GSCL */
3451 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3452 ENABLE_PCLK_GSCL, 7, 0, 0),
3453 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3454 ENABLE_PCLK_GSCL, 6, 0, 0),
3455 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3456 ENABLE_PCLK_GSCL, 5, 0, 0),
3457 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3458 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3459 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3460 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3461 3, CLK_IGNORE_UNUSED, 0),
3462 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3463 ENABLE_PCLK_GSCL, 2, 0, 0),
3464 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3465 ENABLE_PCLK_GSCL, 1, 0, 0),
3466 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3467 ENABLE_PCLK_GSCL, 0, 0, 0),
3468
3469 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3470 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3471 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3472
3473 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3474 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3475 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3476
3477 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3478 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3479 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3480 };
3481
3482 static struct samsung_cmu_info gscl_cmu_info __initdata = {
3483 .mux_clks = gscl_mux_clks,
3484 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3485 .gate_clks = gscl_gate_clks,
3486 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
3487 .nr_clk_ids = GSCL_NR_CLK,
3488 .clk_regs = gscl_clk_regs,
3489 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
3490 };
3491
3492 static void __init exynos5433_cmu_gscl_init(struct device_node *np)
3493 {
3494 samsung_cmu_register_one(np, &gscl_cmu_info);
3495 }
3496 CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3497 exynos5433_cmu_gscl_init);
3498
3499 /*
3500 * Register offset definitions for CMU_APOLLO
3501 */
3502 #define APOLLO_PLL_LOCK 0x0000
3503 #define APOLLO_PLL_CON0 0x0100
3504 #define APOLLO_PLL_CON1 0x0104
3505 #define APOLLO_PLL_FREQ_DET 0x010c
3506 #define MUX_SEL_APOLLO0 0x0200
3507 #define MUX_SEL_APOLLO1 0x0204
3508 #define MUX_SEL_APOLLO2 0x0208
3509 #define MUX_ENABLE_APOLLO0 0x0300
3510 #define MUX_ENABLE_APOLLO1 0x0304
3511 #define MUX_ENABLE_APOLLO2 0x0308
3512 #define MUX_STAT_APOLLO0 0x0400
3513 #define MUX_STAT_APOLLO1 0x0404
3514 #define MUX_STAT_APOLLO2 0x0408
3515 #define DIV_APOLLO0 0x0600
3516 #define DIV_APOLLO1 0x0604
3517 #define DIV_APOLLO_PLL_FREQ_DET 0x0608
3518 #define DIV_STAT_APOLLO0 0x0700
3519 #define DIV_STAT_APOLLO1 0x0704
3520 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3521 #define ENABLE_ACLK_APOLLO 0x0800
3522 #define ENABLE_PCLK_APOLLO 0x0900
3523 #define ENABLE_SCLK_APOLLO 0x0a00
3524 #define ENABLE_IP_APOLLO0 0x0b00
3525 #define ENABLE_IP_APOLLO1 0x0b04
3526 #define CLKOUT_CMU_APOLLO 0x0c00
3527 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3528 #define ARMCLK_STOPCTRL 0x1000
3529 #define APOLLO_PWR_CTRL 0x1020
3530 #define APOLLO_PWR_CTRL2 0x1024
3531 #define APOLLO_INTR_SPREAD_ENABLE 0x1080
3532 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3533 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3534
3535 static unsigned long apollo_clk_regs[] __initdata = {
3536 APOLLO_PLL_LOCK,
3537 APOLLO_PLL_CON0,
3538 APOLLO_PLL_CON1,
3539 APOLLO_PLL_FREQ_DET,
3540 MUX_SEL_APOLLO0,
3541 MUX_SEL_APOLLO1,
3542 MUX_SEL_APOLLO2,
3543 MUX_ENABLE_APOLLO0,
3544 MUX_ENABLE_APOLLO1,
3545 MUX_ENABLE_APOLLO2,
3546 MUX_STAT_APOLLO0,
3547 MUX_STAT_APOLLO1,
3548 MUX_STAT_APOLLO2,
3549 DIV_APOLLO0,
3550 DIV_APOLLO1,
3551 DIV_APOLLO_PLL_FREQ_DET,
3552 DIV_STAT_APOLLO0,
3553 DIV_STAT_APOLLO1,
3554 DIV_STAT_APOLLO_PLL_FREQ_DET,
3555 ENABLE_ACLK_APOLLO,
3556 ENABLE_PCLK_APOLLO,
3557 ENABLE_SCLK_APOLLO,
3558 ENABLE_IP_APOLLO0,
3559 ENABLE_IP_APOLLO1,
3560 CLKOUT_CMU_APOLLO,
3561 CLKOUT_CMU_APOLLO_DIV_STAT,
3562 ARMCLK_STOPCTRL,
3563 APOLLO_PWR_CTRL,
3564 APOLLO_PWR_CTRL2,
3565 APOLLO_INTR_SPREAD_ENABLE,
3566 APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3567 APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3568 };
3569
3570 /* list of all parent clock list */
3571 PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
3572 PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3573 PNAME(mout_apollo_p) = { "mout_apollo_pll",
3574 "mout_bus_pll_apollo_user", };
3575
3576 static struct samsung_pll_clock apollo_pll_clks[] __initdata = {
3577 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3578 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
3579 };
3580
3581 static struct samsung_mux_clock apollo_mux_clks[] __initdata = {
3582 /* MUX_SEL_APOLLO0 */
3583 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3584 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT, 0),
3585
3586 /* MUX_SEL_APOLLO1 */
3587 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3588 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3589
3590 /* MUX_SEL_APOLLO2 */
3591 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3592 0, 1, CLK_SET_RATE_PARENT, 0),
3593 };
3594
3595 static struct samsung_div_clock apollo_div_clks[] __initdata = {
3596 /* DIV_APOLLO0 */
3597 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3598 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3599 CLK_DIVIDER_READ_ONLY),
3600 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3601 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3602 CLK_DIVIDER_READ_ONLY),
3603 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3604 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3605 CLK_DIVIDER_READ_ONLY),
3606 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3607 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3608 CLK_DIVIDER_READ_ONLY),
3609 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3610 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3611 CLK_DIVIDER_READ_ONLY),
3612 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3613 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3614 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3615 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3616
3617 /* DIV_APOLLO1 */
3618 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3619 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3620 CLK_DIVIDER_READ_ONLY),
3621 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3622 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3623 CLK_DIVIDER_READ_ONLY),
3624 };
3625
3626 static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
3627 /* ENABLE_ACLK_APOLLO */
3628 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3629 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3630 6, CLK_IGNORE_UNUSED, 0),
3631 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3632 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3633 5, CLK_IGNORE_UNUSED, 0),
3634 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3635 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3636 4, CLK_IGNORE_UNUSED, 0),
3637 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3638 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3639 3, CLK_IGNORE_UNUSED, 0),
3640 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3641 "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3642 2, CLK_IGNORE_UNUSED, 0),
3643 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3644 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3645 1, CLK_IGNORE_UNUSED, 0),
3646 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3647 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3648 0, CLK_IGNORE_UNUSED, 0),
3649
3650 /* ENABLE_PCLK_APOLLO */
3651 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3652 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3653 2, CLK_IGNORE_UNUSED, 0),
3654 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3655 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3656 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3657 "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3658 0, CLK_IGNORE_UNUSED, 0),
3659
3660 /* ENABLE_SCLK_APOLLO */
3661 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3662 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3663 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3664 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3665 GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo2",
3666 ENABLE_SCLK_APOLLO, 0,
3667 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3668 };
3669
3670 static struct samsung_cmu_info apollo_cmu_info __initdata = {
3671 .pll_clks = apollo_pll_clks,
3672 .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks),
3673 .mux_clks = apollo_mux_clks,
3674 .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks),
3675 .div_clks = apollo_div_clks,
3676 .nr_div_clks = ARRAY_SIZE(apollo_div_clks),
3677 .gate_clks = apollo_gate_clks,
3678 .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks),
3679 .nr_clk_ids = APOLLO_NR_CLK,
3680 .clk_regs = apollo_clk_regs,
3681 .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs),
3682 };
3683
3684 static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3685 {
3686 samsung_cmu_register_one(np, &apollo_cmu_info);
3687 }
3688 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3689 exynos5433_cmu_apollo_init);
3690
3691 /*
3692 * Register offset definitions for CMU_ATLAS
3693 */
3694 #define ATLAS_PLL_LOCK 0x0000
3695 #define ATLAS_PLL_CON0 0x0100
3696 #define ATLAS_PLL_CON1 0x0104
3697 #define ATLAS_PLL_FREQ_DET 0x010c
3698 #define MUX_SEL_ATLAS0 0x0200
3699 #define MUX_SEL_ATLAS1 0x0204
3700 #define MUX_SEL_ATLAS2 0x0208
3701 #define MUX_ENABLE_ATLAS0 0x0300
3702 #define MUX_ENABLE_ATLAS1 0x0304
3703 #define MUX_ENABLE_ATLAS2 0x0308
3704 #define MUX_STAT_ATLAS0 0x0400
3705 #define MUX_STAT_ATLAS1 0x0404
3706 #define MUX_STAT_ATLAS2 0x0408
3707 #define DIV_ATLAS0 0x0600
3708 #define DIV_ATLAS1 0x0604
3709 #define DIV_ATLAS_PLL_FREQ_DET 0x0608
3710 #define DIV_STAT_ATLAS0 0x0700
3711 #define DIV_STAT_ATLAS1 0x0704
3712 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3713 #define ENABLE_ACLK_ATLAS 0x0800
3714 #define ENABLE_PCLK_ATLAS 0x0900
3715 #define ENABLE_SCLK_ATLAS 0x0a00
3716 #define ENABLE_IP_ATLAS0 0x0b00
3717 #define ENABLE_IP_ATLAS1 0x0b04
3718 #define CLKOUT_CMU_ATLAS 0x0c00
3719 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3720 #define ARMCLK_STOPCTRL 0x1000
3721 #define ATLAS_PWR_CTRL 0x1020
3722 #define ATLAS_PWR_CTRL2 0x1024
3723 #define ATLAS_INTR_SPREAD_ENABLE 0x1080
3724 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3725 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3726
3727 static unsigned long atlas_clk_regs[] __initdata = {
3728 ATLAS_PLL_LOCK,
3729 ATLAS_PLL_CON0,
3730 ATLAS_PLL_CON1,
3731 ATLAS_PLL_FREQ_DET,
3732 MUX_SEL_ATLAS0,
3733 MUX_SEL_ATLAS1,
3734 MUX_SEL_ATLAS2,
3735 MUX_ENABLE_ATLAS0,
3736 MUX_ENABLE_ATLAS1,
3737 MUX_ENABLE_ATLAS2,
3738 MUX_STAT_ATLAS0,
3739 MUX_STAT_ATLAS1,
3740 MUX_STAT_ATLAS2,
3741 DIV_ATLAS0,
3742 DIV_ATLAS1,
3743 DIV_ATLAS_PLL_FREQ_DET,
3744 DIV_STAT_ATLAS0,
3745 DIV_STAT_ATLAS1,
3746 DIV_STAT_ATLAS_PLL_FREQ_DET,
3747 ENABLE_ACLK_ATLAS,
3748 ENABLE_PCLK_ATLAS,
3749 ENABLE_SCLK_ATLAS,
3750 ENABLE_IP_ATLAS0,
3751 ENABLE_IP_ATLAS1,
3752 CLKOUT_CMU_ATLAS,
3753 CLKOUT_CMU_ATLAS_DIV_STAT,
3754 ARMCLK_STOPCTRL,
3755 ATLAS_PWR_CTRL,
3756 ATLAS_PWR_CTRL2,
3757 ATLAS_INTR_SPREAD_ENABLE,
3758 ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3759 ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3760 };
3761
3762 /* list of all parent clock list */
3763 PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
3764 PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3765 PNAME(mout_atlas_p) = { "mout_atlas_pll",
3766 "mout_bus_pll_atlas_user", };
3767
3768 static struct samsung_pll_clock atlas_pll_clks[] __initdata = {
3769 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3770 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
3771 };
3772
3773 static struct samsung_mux_clock atlas_mux_clks[] __initdata = {
3774 /* MUX_SEL_ATLAS0 */
3775 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3776 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT, 0),
3777
3778 /* MUX_SEL_ATLAS1 */
3779 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3780 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3781
3782 /* MUX_SEL_ATLAS2 */
3783 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3784 0, 1, CLK_SET_RATE_PARENT, 0),
3785 };
3786
3787 static struct samsung_div_clock atlas_div_clks[] __initdata = {
3788 /* DIV_ATLAS0 */
3789 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3790 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3791 CLK_DIVIDER_READ_ONLY),
3792 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3793 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3794 CLK_DIVIDER_READ_ONLY),
3795 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3796 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3797 CLK_DIVIDER_READ_ONLY),
3798 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3799 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3800 CLK_DIVIDER_READ_ONLY),
3801 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3802 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3803 CLK_DIVIDER_READ_ONLY),
3804 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3805 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3806 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3807 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3808
3809 /* DIV_ATLAS1 */
3810 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3811 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3812 CLK_DIVIDER_READ_ONLY),
3813 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3814 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3815 CLK_DIVIDER_READ_ONLY),
3816 };
3817
3818 static struct samsung_gate_clock atlas_gate_clks[] __initdata = {
3819 /* ENABLE_ACLK_ATLAS */
3820 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3821 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3822 9, CLK_IGNORE_UNUSED, 0),
3823 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3824 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3825 8, CLK_IGNORE_UNUSED, 0),
3826 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3827 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3828 7, CLK_IGNORE_UNUSED, 0),
3829 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3830 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3831 6, CLK_IGNORE_UNUSED, 0),
3832 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3833 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3834 5, CLK_IGNORE_UNUSED, 0),
3835 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3836 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3837 4, CLK_IGNORE_UNUSED, 0),
3838 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3839 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3840 3, CLK_IGNORE_UNUSED, 0),
3841 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3842 "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3843 2, CLK_IGNORE_UNUSED, 0),
3844 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3845 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3846 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3847 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3848
3849 /* ENABLE_PCLK_ATLAS */
3850 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3851 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3852 5, CLK_IGNORE_UNUSED, 0),
3853 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3854 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3855 4, CLK_IGNORE_UNUSED, 0),
3856 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3857 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3858 3, CLK_IGNORE_UNUSED, 0),
3859 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3860 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3861 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3862 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3863 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3864 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3865
3866 /* ENABLE_SCLK_ATLAS */
3867 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3868 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3869 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3870 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3871 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3872 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3873 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3874 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3875 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3876 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3877 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3878 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3879 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3880 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3881 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3882 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3883 GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
3884 ENABLE_SCLK_ATLAS, 0,
3885 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3886 };
3887
3888 static struct samsung_cmu_info atlas_cmu_info __initdata = {
3889 .pll_clks = atlas_pll_clks,
3890 .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks),
3891 .mux_clks = atlas_mux_clks,
3892 .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks),
3893 .div_clks = atlas_div_clks,
3894 .nr_div_clks = ARRAY_SIZE(atlas_div_clks),
3895 .gate_clks = atlas_gate_clks,
3896 .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks),
3897 .nr_clk_ids = ATLAS_NR_CLK,
3898 .clk_regs = atlas_clk_regs,
3899 .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs),
3900 };
3901
3902 static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3903 {
3904 samsung_cmu_register_one(np, &atlas_cmu_info);
3905 }
3906 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3907 exynos5433_cmu_atlas_init);
3908
3909 /*
3910 * Register offset definitions for CMU_MSCL
3911 */
3912 #define MUX_SEL_MSCL0 0x0200
3913 #define MUX_SEL_MSCL1 0x0204
3914 #define MUX_ENABLE_MSCL0 0x0300
3915 #define MUX_ENABLE_MSCL1 0x0304
3916 #define MUX_STAT_MSCL0 0x0400
3917 #define MUX_STAT_MSCL1 0x0404
3918 #define DIV_MSCL 0x0600
3919 #define DIV_STAT_MSCL 0x0700
3920 #define ENABLE_ACLK_MSCL 0x0800
3921 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3922 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3923 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3924 #define ENABLE_PCLK_MSCL 0x0900
3925 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3926 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3927 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
3928 #define ENABLE_SCLK_MSCL 0x0a00
3929 #define ENABLE_IP_MSCL0 0x0b00
3930 #define ENABLE_IP_MSCL1 0x0b04
3931 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3932 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3933 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3934
3935 static unsigned long mscl_clk_regs[] __initdata = {
3936 MUX_SEL_MSCL0,
3937 MUX_SEL_MSCL1,
3938 MUX_ENABLE_MSCL0,
3939 MUX_ENABLE_MSCL1,
3940 MUX_STAT_MSCL0,
3941 MUX_STAT_MSCL1,
3942 DIV_MSCL,
3943 DIV_STAT_MSCL,
3944 ENABLE_ACLK_MSCL,
3945 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3946 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3947 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3948 ENABLE_PCLK_MSCL,
3949 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3950 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3951 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3952 ENABLE_SCLK_MSCL,
3953 ENABLE_IP_MSCL0,
3954 ENABLE_IP_MSCL1,
3955 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
3956 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
3957 ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3958 };
3959
3960 /* list of all parent clock list */
3961 PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
3962 PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
3963 PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
3964 "mout_aclk_mscl_400_user", };
3965
3966 static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
3967 /* MUX_SEL_MSCL0 */
3968 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
3969 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
3970 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
3971 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
3972
3973 /* MUX_SEL_MSCL1 */
3974 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
3975 MUX_SEL_MSCL1, 0, 1),
3976 };
3977
3978 static struct samsung_div_clock mscl_div_clks[] __initdata = {
3979 /* DIV_MSCL */
3980 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
3981 DIV_MSCL, 0, 3),
3982 };
3983
3984 static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
3985 /* ENABLE_ACLK_MSCL */
3986 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
3987 ENABLE_ACLK_MSCL, 9, 0, 0),
3988 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
3989 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
3990 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
3991 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
3992 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
3993 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
3994 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
3995 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
3996 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
3997 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
3998 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
3999 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4000 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
4001 ENABLE_ACLK_MSCL, 2, 0, 0),
4002 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4003 ENABLE_ACLK_MSCL, 1, 0, 0),
4004 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4005 ENABLE_ACLK_MSCL, 0, 0, 0),
4006
4007 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4008 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
4009 "mout_aclk_mscl_400_user",
4010 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4011 0, CLK_IGNORE_UNUSED, 0),
4012
4013 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4014 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
4015 "mout_aclk_mscl_400_user",
4016 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4017 0, CLK_IGNORE_UNUSED, 0),
4018
4019 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4020 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4021 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4022 0, CLK_IGNORE_UNUSED, 0),
4023
4024 /* ENABLE_PCLK_MSCL */
4025 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
4026 ENABLE_PCLK_MSCL, 7, 0, 0),
4027 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4028 ENABLE_PCLK_MSCL, 6, 0, 0),
4029 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4030 ENABLE_PCLK_MSCL, 5, 0, 0),
4031 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
4032 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4033 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
4034 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4035 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
4036 ENABLE_PCLK_MSCL, 2, 0, 0),
4037 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
4038 ENABLE_PCLK_MSCL, 1, 0, 0),
4039 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
4040 ENABLE_PCLK_MSCL, 0, 0, 0),
4041
4042 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4043 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4044 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4045 0, CLK_IGNORE_UNUSED, 0),
4046
4047 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4048 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4049 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4050 0, CLK_IGNORE_UNUSED, 0),
4051
4052 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4053 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
4054 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4055 0, CLK_IGNORE_UNUSED, 0),
4056
4057 /* ENABLE_SCLK_MSCL */
4058 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4059 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4060 };
4061
4062 static struct samsung_cmu_info mscl_cmu_info __initdata = {
4063 .mux_clks = mscl_mux_clks,
4064 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
4065 .div_clks = mscl_div_clks,
4066 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
4067 .gate_clks = mscl_gate_clks,
4068 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
4069 .nr_clk_ids = MSCL_NR_CLK,
4070 .clk_regs = mscl_clk_regs,
4071 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
4072 };
4073
4074 static void __init exynos5433_cmu_mscl_init(struct device_node *np)
4075 {
4076 samsung_cmu_register_one(np, &mscl_cmu_info);
4077 }
4078 CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
4079 exynos5433_cmu_mscl_init);
4080
4081 /*
4082 * Register offset definitions for CMU_MFC
4083 */
4084 #define MUX_SEL_MFC 0x0200
4085 #define MUX_ENABLE_MFC 0x0300
4086 #define MUX_STAT_MFC 0x0400
4087 #define DIV_MFC 0x0600
4088 #define DIV_STAT_MFC 0x0700
4089 #define ENABLE_ACLK_MFC 0x0800
4090 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4091 #define ENABLE_PCLK_MFC 0x0900
4092 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4093 #define ENABLE_IP_MFC0 0x0b00
4094 #define ENABLE_IP_MFC1 0x0b04
4095 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4096
4097 static unsigned long mfc_clk_regs[] __initdata = {
4098 MUX_SEL_MFC,
4099 MUX_ENABLE_MFC,
4100 MUX_STAT_MFC,
4101 DIV_MFC,
4102 DIV_STAT_MFC,
4103 ENABLE_ACLK_MFC,
4104 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4105 ENABLE_PCLK_MFC,
4106 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4107 ENABLE_IP_MFC0,
4108 ENABLE_IP_MFC1,
4109 ENABLE_IP_MFC_SECURE_SMMU_MFC,
4110 };
4111
4112 PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4113
4114 static struct samsung_mux_clock mfc_mux_clks[] __initdata = {
4115 /* MUX_SEL_MFC */
4116 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4117 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4118 };
4119
4120 static struct samsung_div_clock mfc_div_clks[] __initdata = {
4121 /* DIV_MFC */
4122 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4123 DIV_MFC, 0, 2),
4124 };
4125
4126 static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
4127 /* ENABLE_ACLK_MFC */
4128 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4129 ENABLE_ACLK_MFC, 6, 0, 0),
4130 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4131 ENABLE_ACLK_MFC, 5, 0, 0),
4132 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4133 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4134 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4135 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4136 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4137 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4138 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4139 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4140 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4141 ENABLE_ACLK_MFC, 0, 0, 0),
4142
4143 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4144 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4145 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4146 1, CLK_IGNORE_UNUSED, 0),
4147 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4148 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4149 0, CLK_IGNORE_UNUSED, 0),
4150
4151 /* ENABLE_PCLK_MFC */
4152 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4153 ENABLE_PCLK_MFC, 4, 0, 0),
4154 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4155 ENABLE_PCLK_MFC, 3, 0, 0),
4156 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4157 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4158 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4159 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4160 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4161 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4162
4163 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4164 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4165 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4166 1, CLK_IGNORE_UNUSED, 0),
4167 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4168 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4169 0, CLK_IGNORE_UNUSED, 0),
4170 };
4171
4172 static struct samsung_cmu_info mfc_cmu_info __initdata = {
4173 .mux_clks = mfc_mux_clks,
4174 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4175 .div_clks = mfc_div_clks,
4176 .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
4177 .gate_clks = mfc_gate_clks,
4178 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
4179 .nr_clk_ids = MFC_NR_CLK,
4180 .clk_regs = mfc_clk_regs,
4181 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
4182 };
4183
4184 static void __init exynos5433_cmu_mfc_init(struct device_node *np)
4185 {
4186 samsung_cmu_register_one(np, &mfc_cmu_info);
4187 }
4188 CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4189 exynos5433_cmu_mfc_init);
4190
4191 /*
4192 * Register offset definitions for CMU_HEVC
4193 */
4194 #define MUX_SEL_HEVC 0x0200
4195 #define MUX_ENABLE_HEVC 0x0300
4196 #define MUX_STAT_HEVC 0x0400
4197 #define DIV_HEVC 0x0600
4198 #define DIV_STAT_HEVC 0x0700
4199 #define ENABLE_ACLK_HEVC 0x0800
4200 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4201 #define ENABLE_PCLK_HEVC 0x0900
4202 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4203 #define ENABLE_IP_HEVC0 0x0b00
4204 #define ENABLE_IP_HEVC1 0x0b04
4205 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4206
4207 static unsigned long hevc_clk_regs[] __initdata = {
4208 MUX_SEL_HEVC,
4209 MUX_ENABLE_HEVC,
4210 MUX_STAT_HEVC,
4211 DIV_HEVC,
4212 DIV_STAT_HEVC,
4213 ENABLE_ACLK_HEVC,
4214 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4215 ENABLE_PCLK_HEVC,
4216 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4217 ENABLE_IP_HEVC0,
4218 ENABLE_IP_HEVC1,
4219 ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4220 };
4221
4222 PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4223
4224 static struct samsung_mux_clock hevc_mux_clks[] __initdata = {
4225 /* MUX_SEL_HEVC */
4226 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4227 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4228 };
4229
4230 static struct samsung_div_clock hevc_div_clks[] __initdata = {
4231 /* DIV_HEVC */
4232 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4233 DIV_HEVC, 0, 2),
4234 };
4235
4236 static struct samsung_gate_clock hevc_gate_clks[] __initdata = {
4237 /* ENABLE_ACLK_HEVC */
4238 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4239 ENABLE_ACLK_HEVC, 6, 0, 0),
4240 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4241 ENABLE_ACLK_HEVC, 5, 0, 0),
4242 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4243 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4244 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4245 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4246 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4247 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4248 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4249 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4250 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4251 ENABLE_ACLK_HEVC, 0, 0, 0),
4252
4253 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4254 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4255 "mout_aclk_hevc_400_user",
4256 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4257 1, CLK_IGNORE_UNUSED, 0),
4258 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4259 "mout_aclk_hevc_400_user",
4260 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4261 0, CLK_IGNORE_UNUSED, 0),
4262
4263 /* ENABLE_PCLK_HEVC */
4264 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4265 ENABLE_PCLK_HEVC, 4, 0, 0),
4266 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4267 ENABLE_PCLK_HEVC, 3, 0, 0),
4268 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4269 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4270 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4271 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4272 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4273 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4274
4275 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4276 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4277 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4278 1, CLK_IGNORE_UNUSED, 0),
4279 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4280 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4281 0, CLK_IGNORE_UNUSED, 0),
4282 };
4283
4284 static struct samsung_cmu_info hevc_cmu_info __initdata = {
4285 .mux_clks = hevc_mux_clks,
4286 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
4287 .div_clks = hevc_div_clks,
4288 .nr_div_clks = ARRAY_SIZE(hevc_div_clks),
4289 .gate_clks = hevc_gate_clks,
4290 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
4291 .nr_clk_ids = HEVC_NR_CLK,
4292 .clk_regs = hevc_clk_regs,
4293 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
4294 };
4295
4296 static void __init exynos5433_cmu_hevc_init(struct device_node *np)
4297 {
4298 samsung_cmu_register_one(np, &hevc_cmu_info);
4299 }
4300 CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4301 exynos5433_cmu_hevc_init);
4302
4303 /*
4304 * Register offset definitions for CMU_ISP
4305 */
4306 #define MUX_SEL_ISP 0x0200
4307 #define MUX_ENABLE_ISP 0x0300
4308 #define MUX_STAT_ISP 0x0400
4309 #define DIV_ISP 0x0600
4310 #define DIV_STAT_ISP 0x0700
4311 #define ENABLE_ACLK_ISP0 0x0800
4312 #define ENABLE_ACLK_ISP1 0x0804
4313 #define ENABLE_ACLK_ISP2 0x0808
4314 #define ENABLE_PCLK_ISP 0x0900
4315 #define ENABLE_SCLK_ISP 0x0a00
4316 #define ENABLE_IP_ISP0 0x0b00
4317 #define ENABLE_IP_ISP1 0x0b04
4318 #define ENABLE_IP_ISP2 0x0b08
4319 #define ENABLE_IP_ISP3 0x0b0c
4320
4321 static unsigned long isp_clk_regs[] __initdata = {
4322 MUX_SEL_ISP,
4323 MUX_ENABLE_ISP,
4324 MUX_STAT_ISP,
4325 DIV_ISP,
4326 DIV_STAT_ISP,
4327 ENABLE_ACLK_ISP0,
4328 ENABLE_ACLK_ISP1,
4329 ENABLE_ACLK_ISP2,
4330 ENABLE_PCLK_ISP,
4331 ENABLE_SCLK_ISP,
4332 ENABLE_IP_ISP0,
4333 ENABLE_IP_ISP1,
4334 ENABLE_IP_ISP2,
4335 ENABLE_IP_ISP3,
4336 };
4337
4338 PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4339 PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
4340
4341 static struct samsung_mux_clock isp_mux_clks[] __initdata = {
4342 /* MUX_SEL_ISP */
4343 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4344 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4345 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4346 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4347 };
4348
4349 static struct samsung_div_clock isp_div_clks[] __initdata = {
4350 /* DIV_ISP */
4351 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4352 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4353 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4354 DIV_ISP, 8, 3),
4355 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4356 "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4357 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4358 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4359 };
4360
4361 static struct samsung_gate_clock isp_gate_clks[] __initdata = {
4362 /* ENABLE_ACLK_ISP0 */
4363 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4364 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4365 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4366 ENABLE_ACLK_ISP0, 5, 0, 0),
4367 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4368 ENABLE_ACLK_ISP0, 4, 0, 0),
4369 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4370 ENABLE_ACLK_ISP0, 3, 0, 0),
4371 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4372 ENABLE_ACLK_ISP0, 2, 0, 0),
4373 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4374 ENABLE_ACLK_ISP0, 1, 0, 0),
4375 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4376 ENABLE_ACLK_ISP0, 0, 0, 0),
4377
4378 /* ENABLE_ACLK_ISP1 */
4379 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4380 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4381 17, CLK_IGNORE_UNUSED, 0),
4382 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4383 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4384 16, CLK_IGNORE_UNUSED, 0),
4385 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4386 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4387 15, CLK_IGNORE_UNUSED, 0),
4388 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4389 "div_pclk_isp", ENABLE_ACLK_ISP1,
4390 14, CLK_IGNORE_UNUSED, 0),
4391 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4392 "div_pclk_isp", ENABLE_ACLK_ISP1,
4393 13, CLK_IGNORE_UNUSED, 0),
4394 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4395 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4396 12, CLK_IGNORE_UNUSED, 0),
4397 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4398 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4399 11, CLK_IGNORE_UNUSED, 0),
4400 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4401 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4402 10, CLK_IGNORE_UNUSED, 0),
4403 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4404 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4405 9, CLK_IGNORE_UNUSED, 0),
4406 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4407 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4408 8, CLK_IGNORE_UNUSED, 0),
4409 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4410 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4411 7, CLK_IGNORE_UNUSED, 0),
4412 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4413 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4414 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4415 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4416 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4417 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4418 4, CLK_IGNORE_UNUSED, 0),
4419 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4420 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4421 3, CLK_IGNORE_UNUSED, 0),
4422 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4423 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4424 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4425 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4426 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4427 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4428
4429 /* ENABLE_ACLK_ISP2 */
4430 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4431 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4432 13, CLK_IGNORE_UNUSED, 0),
4433 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4434 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4435 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4436 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4437 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4438 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4439 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4440 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4441 9, CLK_IGNORE_UNUSED, 0),
4442 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4443 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4444 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4445 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4446 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4447 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4448 6, CLK_IGNORE_UNUSED, 0),
4449 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4450 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4451 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4452 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4453 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4454 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4455 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4456 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4457 2, CLK_IGNORE_UNUSED, 0),
4458 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4459 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4460 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4461 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4462
4463 /* ENABLE_PCLK_ISP */
4464 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4465 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4466 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4467 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4468 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4469 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4470 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4471 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4472 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4473 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4474 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4475 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4476 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4477 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4478 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4479 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4480 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4481 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4482 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4483 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4484 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4485 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4486 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4487 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4488 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4489 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4490 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4491 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4492 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4493 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4494 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4495 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4496 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4497 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4498 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4499 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4500 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4501 "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4502 7, CLK_IGNORE_UNUSED, 0),
4503 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4504 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4505 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4506 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4507 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4508 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4509 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4510 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4511 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4512 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4513 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4514 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4515 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4516 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4517
4518 /* ENABLE_SCLK_ISP */
4519 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4520 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4521 5, CLK_IGNORE_UNUSED, 0),
4522 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4523 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4524 4, CLK_IGNORE_UNUSED, 0),
4525 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4526 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4527 3, CLK_IGNORE_UNUSED, 0),
4528 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4529 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4530 2, CLK_IGNORE_UNUSED, 0),
4531 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4532 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4533 1, CLK_IGNORE_UNUSED, 0),
4534 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4535 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4536 0, CLK_IGNORE_UNUSED, 0),
4537 };
4538
4539 static struct samsung_cmu_info isp_cmu_info __initdata = {
4540 .mux_clks = isp_mux_clks,
4541 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
4542 .div_clks = isp_div_clks,
4543 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
4544 .gate_clks = isp_gate_clks,
4545 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
4546 .nr_clk_ids = ISP_NR_CLK,
4547 .clk_regs = isp_clk_regs,
4548 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
4549 };
4550
4551 static void __init exynos5433_cmu_isp_init(struct device_node *np)
4552 {
4553 samsung_cmu_register_one(np, &isp_cmu_info);
4554 }
4555 CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
4556 exynos5433_cmu_isp_init);
4557
4558 /*
4559 * Register offset definitions for CMU_CAM0
4560 */
4561 #define MUX_SEL_CAM00 0x0200
4562 #define MUX_SEL_CAM01 0x0204
4563 #define MUX_SEL_CAM02 0x0208
4564 #define MUX_SEL_CAM03 0x020c
4565 #define MUX_SEL_CAM04 0x0210
4566 #define MUX_ENABLE_CAM00 0x0300
4567 #define MUX_ENABLE_CAM01 0x0304
4568 #define MUX_ENABLE_CAM02 0x0308
4569 #define MUX_ENABLE_CAM03 0x030c
4570 #define MUX_ENABLE_CAM04 0x0310
4571 #define MUX_STAT_CAM00 0x0400
4572 #define MUX_STAT_CAM01 0x0404
4573 #define MUX_STAT_CAM02 0x0408
4574 #define MUX_STAT_CAM03 0x040c
4575 #define MUX_STAT_CAM04 0x0410
4576 #define MUX_IGNORE_CAM01 0x0504
4577 #define DIV_CAM00 0x0600
4578 #define DIV_CAM01 0x0604
4579 #define DIV_CAM02 0x0608
4580 #define DIV_CAM03 0x060c
4581 #define DIV_STAT_CAM00 0x0700
4582 #define DIV_STAT_CAM01 0x0704
4583 #define DIV_STAT_CAM02 0x0708
4584 #define DIV_STAT_CAM03 0x070c
4585 #define ENABLE_ACLK_CAM00 0X0800
4586 #define ENABLE_ACLK_CAM01 0X0804
4587 #define ENABLE_ACLK_CAM02 0X0808
4588 #define ENABLE_PCLK_CAM0 0X0900
4589 #define ENABLE_SCLK_CAM0 0X0a00
4590 #define ENABLE_IP_CAM00 0X0b00
4591 #define ENABLE_IP_CAM01 0X0b04
4592 #define ENABLE_IP_CAM02 0X0b08
4593 #define ENABLE_IP_CAM03 0X0b0C
4594
4595 static unsigned long cam0_clk_regs[] __initdata = {
4596 MUX_SEL_CAM00,
4597 MUX_SEL_CAM01,
4598 MUX_SEL_CAM02,
4599 MUX_SEL_CAM03,
4600 MUX_SEL_CAM04,
4601 MUX_ENABLE_CAM00,
4602 MUX_ENABLE_CAM01,
4603 MUX_ENABLE_CAM02,
4604 MUX_ENABLE_CAM03,
4605 MUX_ENABLE_CAM04,
4606 MUX_STAT_CAM00,
4607 MUX_STAT_CAM01,
4608 MUX_STAT_CAM02,
4609 MUX_STAT_CAM03,
4610 MUX_STAT_CAM04,
4611 MUX_IGNORE_CAM01,
4612 DIV_CAM00,
4613 DIV_CAM01,
4614 DIV_CAM02,
4615 DIV_CAM03,
4616 DIV_STAT_CAM00,
4617 DIV_STAT_CAM01,
4618 DIV_STAT_CAM02,
4619 DIV_STAT_CAM03,
4620 ENABLE_ACLK_CAM00,
4621 ENABLE_ACLK_CAM01,
4622 ENABLE_ACLK_CAM02,
4623 ENABLE_PCLK_CAM0,
4624 ENABLE_SCLK_CAM0,
4625 ENABLE_IP_CAM00,
4626 ENABLE_IP_CAM01,
4627 ENABLE_IP_CAM02,
4628 ENABLE_IP_CAM03,
4629 };
4630 PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
4631 PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
4632 PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
4633
4634 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4635 "phyclk_rxbyteclkhs0_s4_phy", };
4636 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4637 "phyclk_rxbyteclkhs0_s2a_phy", };
4638
4639 PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a",
4640 "mout_aclk_cam0_333_user", };
4641 PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user",
4642 "mout_aclk_cam0_400_user", };
4643 PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a",
4644 "mout_aclk_cam0_333_user", };
4645 PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user",
4646 "mout_aclk_cam0_400_user", };
4647 PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a",
4648 "mout_aclk_cam0_333_user", };
4649 PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user",
4650 "mout_aclk_cam0_400_user", };
4651 PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user",
4652 "mout_aclk_cam0_333_user", };
4653
4654 PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a",
4655 "mout_aclk_cam0_333_user" };
4656 PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user",
4657 "mout_aclk_cam0_400_user", };
4658 PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a",
4659 "mout_aclk_cam0_333_user", };
4660 PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user",
4661 "mout_aclk-cam0_400_user", };
4662 PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a",
4663 "mout_aclk_cam0_333_user", };
4664 PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user",
4665 "mout_aclk_cam0_400_user", };
4666 PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a",
4667 "mout_aclk_cam0_333_user", };
4668 PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user",
4669 "mout_aclk_cam0_400_user", };
4670
4671 PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b",
4672 "div_pclk_lite_d", };
4673 PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a",
4674 "div_pclk_pixelasync_lite_c", };
4675 PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a",
4676 "div_pclk_lite_b", };
4677 PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a",
4678 "mout_aclk_cam0_333_user", };
4679 PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user",
4680 "mout_aclk_cam0_400_user", };
4681 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4682 "mout_sclk_pixelasync_lite_c_init_a",
4683 "mout_aclk_cam0_400_user", };
4684 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4685 "mout_aclk_cam0_552_user",
4686 "mout_aclk_cam0_400_user", };
4687
4688 static struct samsung_fixed_rate_clock cam0_fixed_clks[] __initdata = {
4689 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4690 NULL, CLK_IS_ROOT, 100000000),
4691 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4692 NULL, CLK_IS_ROOT, 100000000),
4693 };
4694
4695 static struct samsung_mux_clock cam0_mux_clks[] __initdata = {
4696 /* MUX_SEL_CAM00 */
4697 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4698 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4699 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4700 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4701 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4702 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4703
4704 /* MUX_SEL_CAM01 */
4705 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4706 "mout_phyclk_rxbyteclkhs0_s4_user",
4707 mout_phyclk_rxbyteclkhs0_s4_user_p,
4708 MUX_SEL_CAM01, 4, 1),
4709 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4710 "mout_phyclk_rxbyteclkhs0_s2a_user",
4711 mout_phyclk_rxbyteclkhs0_s2a_user_p,
4712 MUX_SEL_CAM01, 0, 1),
4713
4714 /* MUX_SEL_CAM02 */
4715 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4716 MUX_SEL_CAM02, 24, 1),
4717 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4718 MUX_SEL_CAM02, 20, 1),
4719 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4720 MUX_SEL_CAM02, 16, 1),
4721 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4722 MUX_SEL_CAM02, 12, 1),
4723 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4724 MUX_SEL_CAM02, 8, 1),
4725 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4726 MUX_SEL_CAM02, 4, 1),
4727 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4728 MUX_SEL_CAM02, 0, 1),
4729
4730 /* MUX_SEL_CAM03 */
4731 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4732 MUX_SEL_CAM03, 28, 1),
4733 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4734 MUX_SEL_CAM03, 24, 1),
4735 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4736 MUX_SEL_CAM03, 20, 1),
4737 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4738 MUX_SEL_CAM03, 16, 1),
4739 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4740 MUX_SEL_CAM03, 12, 1),
4741 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4742 MUX_SEL_CAM03, 8, 1),
4743 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4744 MUX_SEL_CAM03, 4, 1),
4745 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4746 MUX_SEL_CAM03, 0, 1),
4747
4748 /* MUX_SEL_CAM04 */
4749 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4750 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4751 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4752 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 24, 1),
4753 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4754 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 24, 1),
4755 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4756 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 24, 1),
4757 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4758 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 24, 1),
4759 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4760 "mout_sclk_pixelasync_lite_c_init_b",
4761 mout_sclk_pixelasync_lite_c_init_b_p,
4762 MUX_SEL_CAM04, 24, 1),
4763 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4764 "mout_sclk_pixelasync_lite_c_init_a",
4765 mout_sclk_pixelasync_lite_c_init_a_p,
4766 MUX_SEL_CAM04, 24, 1),
4767 };
4768
4769 static struct samsung_div_clock cam0_div_clks[] __initdata = {
4770 /* DIV_CAM00 */
4771 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4772 DIV_CAM00, 8, 2),
4773 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4774 DIV_CAM00, 4, 3),
4775 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4776 "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4777
4778 /* DIV_CAM01 */
4779 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4780 DIV_CAM01, 20, 2),
4781 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4782 DIV_CAM01, 16, 3),
4783 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4784 DIV_CAM01, 12, 2),
4785 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4786 DIV_CAM01, 8, 3),
4787 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4788 DIV_CAM01, 4, 2),
4789 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4790 DIV_CAM01, 0, 3),
4791
4792 /* DIV_CAM02 */
4793 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4794 DIV_CAM02, 20, 3),
4795 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4796 DIV_CAM02, 16, 3),
4797 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4798 DIV_CAM02, 12, 2),
4799 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4800 DIV_CAM02, 8, 3),
4801 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4802 DIV_CAM02, 4, 2),
4803 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4804 DIV_CAM02, 0, 3),
4805
4806 /* DIV_CAM03 */
4807 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4808 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4809 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4810 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4811 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4812 "div_sclk_pixelasync_lite_c_init",
4813 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4814 };
4815
4816 static struct samsung_gate_clock cam0_gate_clks[] __initdata = {
4817 /* ENABLE_ACLK_CAM00 */
4818 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4819 6, 0, 0),
4820 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4821 5, 0, 0),
4822 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4823 4, 0, 0),
4824 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4825 3, 0, 0),
4826 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4827 ENABLE_ACLK_CAM00, 2, 0, 0),
4828 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4829 ENABLE_ACLK_CAM00, 1, 0, 0),
4830 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4831 ENABLE_ACLK_CAM00, 0, 0, 0),
4832
4833 /* ENABLE_ACLK_CAM01 */
4834 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4835 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4836 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4837 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4838 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4839 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4840 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4841 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4842 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4843 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4844 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4845 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4846 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4847 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4848 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4849 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4850 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4851 "div_pclk_lite_d", ENABLE_ACLK_CAM01,
4852 23, CLK_IGNORE_UNUSED, 0),
4853 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4854 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4855 22, CLK_IGNORE_UNUSED, 0),
4856 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4857 "div_pclk_lite_b", ENABLE_ACLK_CAM01,
4858 21, CLK_IGNORE_UNUSED, 0),
4859 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4860 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4861 20, CLK_IGNORE_UNUSED, 0),
4862 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4863 "div_pclk_lite_a", ENABLE_ACLK_CAM01,
4864 19, CLK_IGNORE_UNUSED, 0),
4865 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4866 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4867 18, CLK_IGNORE_UNUSED, 0),
4868 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4869 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4870 17, CLK_IGNORE_UNUSED, 0),
4871 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4872 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4873 16, CLK_IGNORE_UNUSED, 0),
4874 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4875 "div_aclk_3aa1", ENABLE_ACLK_CAM01,
4876 15, CLK_IGNORE_UNUSED, 0),
4877 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4878 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4879 14, CLK_IGNORE_UNUSED, 0),
4880 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4881 "div_aclk_3aa0", ENABLE_ACLK_CAM01,
4882 13, CLK_IGNORE_UNUSED, 0),
4883 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4884 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4885 12, CLK_IGNORE_UNUSED, 0),
4886 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4887 "div_aclk_lite_d", ENABLE_ACLK_CAM01,
4888 11, CLK_IGNORE_UNUSED, 0),
4889 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4890 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4891 10, CLK_IGNORE_UNUSED, 0),
4892 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4893 "div_aclk_lite_b", ENABLE_ACLK_CAM01,
4894 9, CLK_IGNORE_UNUSED, 0),
4895 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4896 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4897 8, CLK_IGNORE_UNUSED, 0),
4898 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4899 "div_aclk_lite_a", ENABLE_ACLK_CAM01,
4900 7, CLK_IGNORE_UNUSED, 0),
4901 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4902 "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4903 6, CLK_IGNORE_UNUSED, 0),
4904 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4905 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4906 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4907 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4908 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4909 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4910 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4911 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4912 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4913 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4914 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4915 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4916
4917 /* ENABLE_ACLK_CAM02 */
4918 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4919 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4920 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4921 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4922 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4923 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4924 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4925 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4926 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4927 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4928 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4929 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4930 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4931 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4932 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4933 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4934 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4935 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4936 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4937 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4938
4939 /* ENABLE_PCLK_CAM0 */
4940 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4941 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4942 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4943 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
4944 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
4945 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
4946 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
4947 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
4948 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
4949 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
4950 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
4951 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
4952 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
4953 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
4954 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
4955 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
4956 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
4957 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
4958 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
4959 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
4960 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
4961 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
4962 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
4963 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
4964 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
4965 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
4966 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
4967 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4968 12, CLK_IGNORE_UNUSED, 0),
4969 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
4970 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4971 11, CLK_IGNORE_UNUSED, 0),
4972 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
4973 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4974 10, CLK_IGNORE_UNUSED, 0),
4975 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
4976 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
4977 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
4978 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
4979 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
4980 "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
4981 7, CLK_IGNORE_UNUSED, 0),
4982 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
4983 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
4984 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
4985 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
4986 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
4987 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
4988 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
4989 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
4990 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
4991 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
4992 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
4993 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
4994 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
4995 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
4996
4997 /* ENABLE_SCLK_CAM0 */
4998 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
4999 "mout_phyclk_rxbyteclkhs0_s4_user",
5000 ENABLE_SCLK_CAM0, 8, 0, 0),
5001 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
5002 "mout_phyclk_rxbyteclkhs0_s2a_user",
5003 ENABLE_SCLK_CAM0, 7, 0, 0),
5004 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
5005 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5006 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
5007 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5008 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
5009 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5010 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
5011 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5012 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
5013 "div_sclk_pixelasync_lite_c",
5014 ENABLE_SCLK_CAM0, 2, 0, 0),
5015 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
5016 "div_sclk_pixelasync_lite_c_init",
5017 ENABLE_SCLK_CAM0, 1, 0, 0),
5018 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
5019 "div_sclk_pixelasync_lite_c",
5020 ENABLE_SCLK_CAM0, 0, 0, 0),
5021 };
5022
5023 static struct samsung_cmu_info cam0_cmu_info __initdata = {
5024 .mux_clks = cam0_mux_clks,
5025 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
5026 .div_clks = cam0_div_clks,
5027 .nr_div_clks = ARRAY_SIZE(cam0_div_clks),
5028 .gate_clks = cam0_gate_clks,
5029 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
5030 .fixed_clks = cam0_fixed_clks,
5031 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
5032 .nr_clk_ids = CAM0_NR_CLK,
5033 .clk_regs = cam0_clk_regs,
5034 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
5035 };
5036
5037 static void __init exynos5433_cmu_cam0_init(struct device_node *np)
5038 {
5039 samsung_cmu_register_one(np, &cam0_cmu_info);
5040 }
5041 CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0",
5042 exynos5433_cmu_cam0_init);
5043
5044 /*
5045 * Register offset definitions for CMU_CAM1
5046 */
5047 #define MUX_SEL_CAM10 0x0200
5048 #define MUX_SEL_CAM11 0x0204
5049 #define MUX_SEL_CAM12 0x0208
5050 #define MUX_ENABLE_CAM10 0x0300
5051 #define MUX_ENABLE_CAM11 0x0304
5052 #define MUX_ENABLE_CAM12 0x0308
5053 #define MUX_STAT_CAM10 0x0400
5054 #define MUX_STAT_CAM11 0x0404
5055 #define MUX_STAT_CAM12 0x0408
5056 #define MUX_IGNORE_CAM11 0x0504
5057 #define DIV_CAM10 0x0600
5058 #define DIV_CAM11 0x0604
5059 #define DIV_STAT_CAM10 0x0700
5060 #define DIV_STAT_CAM11 0x0704
5061 #define ENABLE_ACLK_CAM10 0X0800
5062 #define ENABLE_ACLK_CAM11 0X0804
5063 #define ENABLE_ACLK_CAM12 0X0808
5064 #define ENABLE_PCLK_CAM1 0X0900
5065 #define ENABLE_SCLK_CAM1 0X0a00
5066 #define ENABLE_IP_CAM10 0X0b00
5067 #define ENABLE_IP_CAM11 0X0b04
5068 #define ENABLE_IP_CAM12 0X0b08
5069
5070 static unsigned long cam1_clk_regs[] __initdata = {
5071 MUX_SEL_CAM10,
5072 MUX_SEL_CAM11,
5073 MUX_SEL_CAM12,
5074 MUX_ENABLE_CAM10,
5075 MUX_ENABLE_CAM11,
5076 MUX_ENABLE_CAM12,
5077 MUX_STAT_CAM10,
5078 MUX_STAT_CAM11,
5079 MUX_STAT_CAM12,
5080 MUX_IGNORE_CAM11,
5081 DIV_CAM10,
5082 DIV_CAM11,
5083 DIV_STAT_CAM10,
5084 DIV_STAT_CAM11,
5085 ENABLE_ACLK_CAM10,
5086 ENABLE_ACLK_CAM11,
5087 ENABLE_ACLK_CAM12,
5088 ENABLE_PCLK_CAM1,
5089 ENABLE_SCLK_CAM1,
5090 ENABLE_IP_CAM10,
5091 ENABLE_IP_CAM11,
5092 ENABLE_IP_CAM12,
5093 };
5094
5095 PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
5096 PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
5097 PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
5098
5099 PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", };
5100 PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", };
5101 PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", };
5102
5103 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5104 "phyclk_rxbyteclkhs0_s2b_phy", };
5105
5106 PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a",
5107 "mout_aclk_cam1_333_user", };
5108 PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user",
5109 "mout_aclk_cam1_400_user", };
5110
5111 PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a",
5112 "mout_aclk_cam1_333_user", };
5113 PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user",
5114 "mout_aclk_cam1_400_user", };
5115
5116 PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
5117 "mout_aclk_cam1_333_user", };
5118 PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
5119 "mout_aclk_cam1_400_user", };
5120
5121 static struct samsung_fixed_rate_clock cam1_fixed_clks[] __initdata = {
5122 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5123 CLK_IS_ROOT, 100000000),
5124 };
5125
5126 static struct samsung_mux_clock cam1_mux_clks[] __initdata = {
5127 /* MUX_SEL_CAM10 */
5128 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5129 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5130 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5131 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5132 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5133 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5134 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5135 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5136 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5137 mout_aclk_cam1_400_user_p, MUX_SEL_CAM01, 4, 1),
5138 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5139 mout_aclk_cam1_552_user_p, MUX_SEL_CAM01, 0, 1),
5140
5141 /* MUX_SEL_CAM11 */
5142 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5143 "mout_phyclk_rxbyteclkhs0_s2b_user",
5144 mout_phyclk_rxbyteclkhs0_s2b_user_p,
5145 MUX_SEL_CAM11, 0, 1),
5146
5147 /* MUX_SEL_CAM12 */
5148 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5149 MUX_SEL_CAM12, 20, 1),
5150 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5151 MUX_SEL_CAM12, 16, 1),
5152 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5153 MUX_SEL_CAM12, 12, 1),
5154 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5155 MUX_SEL_CAM12, 8, 1),
5156 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5157 MUX_SEL_CAM12, 4, 1),
5158 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5159 MUX_SEL_CAM12, 0, 1),
5160 };
5161
5162 static struct samsung_div_clock cam1_div_clks[] __initdata = {
5163 /* DIV_CAM10 */
5164 DIV(CLK_DIV_SCLK_ISP_WPWM, "div_sclk_isp_wpwm",
5165 "div_pclk_cam1_83", DIV_CAM10, 16, 2),
5166 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5167 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5168 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5169 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5170 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5171 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5172 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5173 DIV_CAM10, 0, 3),
5174
5175 /* DIV_CAM11 */
5176 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5177 DIV_CAM11, 16, 3),
5178 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5179 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5180 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5181 DIV_CAM11, 4, 2),
5182 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5183 DIV_CAM11, 0, 3),
5184 };
5185
5186 static struct samsung_gate_clock cam1_gate_clks[] __initdata = {
5187 /* ENABLE_ACLK_CAM10 */
5188 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5189 ENABLE_ACLK_CAM10, 4, 0, 0),
5190 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5191 ENABLE_ACLK_CAM10, 3, 0, 0),
5192 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5193 ENABLE_ACLK_CAM10, 1, 0, 0),
5194 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5195 ENABLE_ACLK_CAM10, 0, 0, 0),
5196
5197 /* ENABLE_ACLK_CAM11 */
5198 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5199 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5200 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5201 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5202 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5203 "div_pclk_lite_c", ENABLE_ACLK_CAM11,
5204 27, CLK_IGNORE_UNUSED, 0),
5205 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5206 "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5207 26, CLK_IGNORE_UNUSED, 0),
5208 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5209 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5210 25, CLK_IGNORE_UNUSED, 0),
5211 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5212 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5213 24, CLK_IGNORE_UNUSED, 0),
5214 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5215 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5216 23, CLK_IGNORE_UNUSED, 0),
5217 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5218 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5219 22, CLK_IGNORE_UNUSED, 0),
5220 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5221 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5222 21, CLK_IGNORE_UNUSED, 0),
5223 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5224 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5225 20, CLK_IGNORE_UNUSED, 0),
5226 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5227 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5228 19, CLK_IGNORE_UNUSED, 0),
5229 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5230 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5231 18, CLK_IGNORE_UNUSED, 0),
5232 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5233 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5234 17, CLK_IGNORE_UNUSED, 0),
5235 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5236 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5237 16, CLK_IGNORE_UNUSED, 0),
5238 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5239 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5240 15, CLK_IGNORE_UNUSED, 0),
5241 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5242 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5243 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5244 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5245 13, CLK_IGNORE_UNUSED, 0),
5246 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5247 "div_aclk_lite_c", ENABLE_ACLK_CAM11,
5248 12, CLK_IGNORE_UNUSED, 0),
5249 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5250 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5251 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5252 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5253 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5254 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5255 9, CLK_IGNORE_UNUSED, 0),
5256 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5257 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5258 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5259 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5260 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5261 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5262 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5263 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5264 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5265 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5266 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5267 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5268 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5269 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5270 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5271 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5272 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5273 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5274
5275 /* ENABLE_ACLK_CAM12 */
5276 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5277 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5278 10, CLK_IGNORE_UNUSED, 0),
5279 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5280 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5281 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5282 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5283 8, CLK_IGNORE_UNUSED, 0),
5284 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5285 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5286 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5287 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5288 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5289 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5290 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5291 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5292 4, CLK_IGNORE_UNUSED, 0),
5293 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5294 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5295 3, CLK_IGNORE_UNUSED, 0),
5296 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5297 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5298 2, CLK_IGNORE_UNUSED, 0),
5299 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5300 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5301 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5302 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5303 0, CLK_IGNORE_UNUSED, 0),
5304
5305 /* ENABLE_PCLK_CAM1 */
5306 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5307 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5308 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5309 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5310 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5311 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5312 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5313 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5314 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5315 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5316 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5317 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5318 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5319 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5320 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5321 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5322 20, CLK_IGNORE_UNUSED, 0),
5323 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5324 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5325 19, CLK_IGNORE_UNUSED, 0),
5326 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5327 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5328 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5329 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5330 17, CLK_IGNORE_UNUSED, 0),
5331 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5332 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5333 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5334 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5335 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5336 "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5337 14, CLK_IGNORE_UNUSED, 0),
5338 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5339 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5340 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5341 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5342 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5343 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5344 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5345 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5346 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5347 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5348 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5349 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5350 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5351 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5352 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5353 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5354 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5355 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5356 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5357 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5358 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_wpwm", "div_pclk_cam1_83",
5359 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5360 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5361 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5362 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5363 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5364 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5365 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5366
5367 /* ENABLE_SCLK_CAM1 */
5368 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5369 15, 0, 0),
5370 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5371 14, 0, 0),
5372 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5373 13, 0, 0),
5374 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5375 12, 0, 0),
5376 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5377 "mout_phyclk_rxbyteclkhs0_s2b_user",
5378 ENABLE_SCLK_CAM1, 11, 0, 0),
5379 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5380 ENABLE_SCLK_CAM1, 10, 0, 0),
5381 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5382 ENABLE_SCLK_CAM1, 9, 0, 0),
5383 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5384 ENABLE_SCLK_CAM1, 7, 0, 0),
5385 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5386 ENABLE_SCLK_CAM1, 6, 0, 0),
5387 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5388 ENABLE_SCLK_CAM1, 5, 0, 0),
5389 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5390 ENABLE_SCLK_CAM1, 4, 0, 0),
5391 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_wpwm", "div_sclk_isp_wpwm",
5392 ENABLE_SCLK_CAM1, 3, 0, 0),
5393 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5394 ENABLE_SCLK_CAM1, 2, 0, 0),
5395 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5396 ENABLE_SCLK_CAM1, 1, 0, 0),
5397 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5398 ENABLE_SCLK_CAM1, 0, 0, 0),
5399 };
5400
5401 static struct samsung_cmu_info cam1_cmu_info __initdata = {
5402 .mux_clks = cam1_mux_clks,
5403 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
5404 .div_clks = cam1_div_clks,
5405 .nr_div_clks = ARRAY_SIZE(cam1_div_clks),
5406 .gate_clks = cam1_gate_clks,
5407 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
5408 .fixed_clks = cam1_fixed_clks,
5409 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
5410 .nr_clk_ids = CAM1_NR_CLK,
5411 .clk_regs = cam1_clk_regs,
5412 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
5413 };
5414
5415 static void __init exynos5433_cmu_cam1_init(struct device_node *np)
5416 {
5417 samsung_cmu_register_one(np, &cam1_cmu_info);
5418 }
5419 CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1",
5420 exynos5433_cmu_cam1_init);
Linux with added FPC-III support