drivers/clk/samsung/clk-s3c2410-dclk.c

   1 /*
   2  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Common Clock Framework support for s3c24xx external clock output.
   9  */
  10
  11 #include <linux/clkdev.h>
  12 #include <linux/slab.h>
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/module.h>
  17 #include "clk.h"
  18
  19 /* legacy access to misccr, until dt conversion is finished */
  20 #include <mach/hardware.h>
  21 #include <mach/regs-gpio.h>
  22
  23 #define MUX_DCLK0       0
  24 #define MUX_DCLK1       1
  25 #define DIV_DCLK0       2
  26 #define DIV_DCLK1       3
  27 #define GATE_DCLK0      4
  28 #define GATE_DCLK1      5
  29 #define MUX_CLKOUT0     6
  30 #define MUX_CLKOUT1     7
  31 #define DCLK_MAX_CLKS   (MUX_CLKOUT1 + 1)
  32
  33 enum supported_socs {
  34         S3C2410,
  35         S3C2412,
  36         S3C2440,
  37         S3C2443,
  38 };
  39
  40 struct s3c24xx_dclk_drv_data {
  41         const char **clkout0_parent_names;
  42         int clkout0_num_parents;
  43         const char **clkout1_parent_names;
  44         int clkout1_num_parents;
  45         const char **mux_parent_names;
  46         int mux_num_parents;
  47 };
  48
  49 /*
  50  * Clock for output-parent selection in misccr
  51  */
  52
  53 struct s3c24xx_clkout {
  54         struct clk_hw           hw;
  55         u32                     mask;
  56         u8                      shift;
  57 };
  58
  59 #define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)
  60
  61 static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
  62 {
  63         struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
  64         int num_parents = clk_hw_get_num_parents(hw);
  65         u32 val;
  66
  67         val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift;
  68         val >>= clkout->shift;
  69         val &= clkout->mask;
  70
  71         if (val >= num_parents)
  72                 return -EINVAL;
  73
  74         return val;
  75 }
  76
  77 static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
  78 {
  79         struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
  80         int ret = 0;
  81
  82         s3c2410_modify_misccr((clkout->mask << clkout->shift),
  83                               (index << clkout->shift));
  84
  85         return ret;
  86 }
  87
  88 static const struct clk_ops s3c24xx_clkout_ops = {
  89         .get_parent = s3c24xx_clkout_get_parent,
  90         .set_parent = s3c24xx_clkout_set_parent,
  91         .determine_rate = __clk_mux_determine_rate,
  92 };
  93
  94 static struct clk *s3c24xx_register_clkout(struct device *dev, const char *name,
  95                 const char **parent_names, u8 num_parents,
  96                 u8 shift, u32 mask)
  97 {
  98         struct s3c24xx_clkout *clkout;
  99         struct clk *clk;
 100         struct clk_init_data init;
 101
 102         /* allocate the clkout */
 103         clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
 104         if (!clkout)
 105                 return ERR_PTR(-ENOMEM);
 106
 107         init.name = name;
 108         init.ops = &s3c24xx_clkout_ops;
 109         init.flags = CLK_IS_BASIC;
 110         init.parent_names = parent_names;
 111         init.num_parents = num_parents;
 112
 113         clkout->shift = shift;
 114         clkout->mask = mask;
 115         clkout->hw.init = &init;
 116
 117         clk = clk_register(dev, &clkout->hw);
 118
 119         return clk;
 120 }
 121
 122 /*
 123  * dclk and clkout init
 124  */
 125
 126 struct s3c24xx_dclk {
 127         struct device *dev;
 128         void __iomem *base;
 129         struct clk_onecell_data clk_data;
 130         struct notifier_block dclk0_div_change_nb;
 131         struct notifier_block dclk1_div_change_nb;
 132         spinlock_t dclk_lock;
 133         unsigned long reg_save;
 134 };
 135
 136 #define to_s3c24xx_dclk0(x) \
 137                 container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb)
 138
 139 #define to_s3c24xx_dclk1(x) \
 140                 container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb)
 141
 142 static const char *dclk_s3c2410_p[] = { "pclk", "uclk" };
 143 static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
 144                              "gate_dclk0" };
 145 static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
 146                              "gate_dclk1" };
 147
 148 static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
 149                              "hclk", "pclk", "gate_dclk0" };
 150 static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
 151                              "gate_dclk1" };
 152
 153 static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
 154                              "gate_dclk0" };
 155 static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
 156                              "hclk", "pclk", "gate_dclk1" };
 157
 158 static const char *dclk_s3c2443_p[] = { "pclk", "epll" };
 159 static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk",
 160                              "gate_dclk0" };
 161 static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout",
 162                              "hclk", "pclk", "gate_dclk1" };
 163
 164 #define DCLKCON_DCLK_DIV_MASK           0xf
 165 #define DCLKCON_DCLK0_DIV_SHIFT         4
 166 #define DCLKCON_DCLK0_CMP_SHIFT         8
 167 #define DCLKCON_DCLK1_DIV_SHIFT         20
 168 #define DCLKCON_DCLK1_CMP_SHIFT         24
 169
 170 static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk,
 171                                     int div_shift, int cmp_shift)
 172 {
 173         unsigned long flags = 0;
 174         u32 dclk_con, div, cmp;
 175
 176         spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags);
 177
 178         dclk_con = readl_relaxed(s3c24xx_dclk->base);
 179
 180         div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1;
 181         cmp = ((div + 1) / 2) - 1;
 182
 183         dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift);
 184         dclk_con |= (cmp << cmp_shift);
 185
 186         writel_relaxed(dclk_con, s3c24xx_dclk->base);
 187
 188         spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags);
 189 }
 190
 191 static int s3c24xx_dclk0_div_notify(struct notifier_block *nb,
 192                                unsigned long event, void *data)
 193 {
 194         struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb);
 195
 196         if (event == POST_RATE_CHANGE) {
 197                 s3c24xx_dclk_update_cmp(s3c24xx_dclk,
 198                         DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT);
 199         }
 200
 201         return NOTIFY_DONE;
 202 }
 203
 204 static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
 205                                unsigned long event, void *data)
 206 {
 207         struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb);
 208
 209         if (event == POST_RATE_CHANGE) {
 210                 s3c24xx_dclk_update_cmp(s3c24xx_dclk,
 211                         DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT);
 212         }
 213
 214         return NOTIFY_DONE;
 215 }
 216
 217 #ifdef CONFIG_PM_SLEEP
 218 static int s3c24xx_dclk_suspend(struct device *dev)
 219 {
 220         struct platform_device *pdev = to_platform_device(dev);
 221         struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
 222
 223         s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
 224         return 0;
 225 }
 226
 227 static int s3c24xx_dclk_resume(struct device *dev)
 228 {
 229         struct platform_device *pdev = to_platform_device(dev);
 230         struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
 231
 232         writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
 233         return 0;
 234 }
 235 #endif
 236
 237 static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops,
 238                          s3c24xx_dclk_suspend, s3c24xx_dclk_resume);
 239
 240 static int s3c24xx_dclk_probe(struct platform_device *pdev)
 241 {
 242         struct s3c24xx_dclk *s3c24xx_dclk;
 243         struct resource *mem;
 244         struct clk **clk_table;
 245         struct s3c24xx_dclk_drv_data *dclk_variant;
 246         int ret, i;
 247
 248         s3c24xx_dclk = devm_kzalloc(&pdev->dev, sizeof(*s3c24xx_dclk),
 249                                     GFP_KERNEL);
 250         if (!s3c24xx_dclk)
 251                 return -ENOMEM;
 252
 253         s3c24xx_dclk->dev = &pdev->dev;
 254         platform_set_drvdata(pdev, s3c24xx_dclk);
 255         spin_lock_init(&s3c24xx_dclk->dclk_lock);
 256
 257         clk_table = devm_kzalloc(&pdev->dev,
 258                                  sizeof(struct clk *) * DCLK_MAX_CLKS,
 259                                  GFP_KERNEL);
 260         if (!clk_table)
 261                 return -ENOMEM;
 262
 263         s3c24xx_dclk->clk_data.clks = clk_table;
 264         s3c24xx_dclk->clk_data.clk_num = DCLK_MAX_CLKS;
 265
 266         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 267         s3c24xx_dclk->base = devm_ioremap_resource(&pdev->dev, mem);
 268         if (IS_ERR(s3c24xx_dclk->base))
 269                 return PTR_ERR(s3c24xx_dclk->base);
 270
 271         dclk_variant = (struct s3c24xx_dclk_drv_data *)
 272                                 platform_get_device_id(pdev)->driver_data;
 273
 274
 275         clk_table[MUX_DCLK0] = clk_register_mux(&pdev->dev, "mux_dclk0",
 276                                 dclk_variant->mux_parent_names,
 277                                 dclk_variant->mux_num_parents, 0,
 278                                 s3c24xx_dclk->base, 1, 1, 0,
 279                                 &s3c24xx_dclk->dclk_lock);
 280         clk_table[MUX_DCLK1] = clk_register_mux(&pdev->dev, "mux_dclk1",
 281                                 dclk_variant->mux_parent_names,
 282                                 dclk_variant->mux_num_parents, 0,
 283                                 s3c24xx_dclk->base, 17, 1, 0,
 284                                 &s3c24xx_dclk->dclk_lock);
 285
 286         clk_table[DIV_DCLK0] = clk_register_divider(&pdev->dev, "div_dclk0",
 287                                 "mux_dclk0", 0, s3c24xx_dclk->base,
 288                                 4, 4, 0, &s3c24xx_dclk->dclk_lock);
 289         clk_table[DIV_DCLK1] = clk_register_divider(&pdev->dev, "div_dclk1",
 290                                 "mux_dclk1", 0, s3c24xx_dclk->base,
 291                                 20, 4, 0, &s3c24xx_dclk->dclk_lock);
 292
 293         clk_table[GATE_DCLK0] = clk_register_gate(&pdev->dev, "gate_dclk0",
 294                                 "div_dclk0", CLK_SET_RATE_PARENT,
 295                                 s3c24xx_dclk->base, 0, 0,
 296                                 &s3c24xx_dclk->dclk_lock);
 297         clk_table[GATE_DCLK1] = clk_register_gate(&pdev->dev, "gate_dclk1",
 298                                 "div_dclk1", CLK_SET_RATE_PARENT,
 299                                 s3c24xx_dclk->base, 16, 0,
 300                                 &s3c24xx_dclk->dclk_lock);
 301
 302         clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev,
 303                                 "clkout0", dclk_variant->clkout0_parent_names,
 304                                 dclk_variant->clkout0_num_parents, 4, 7);
 305         clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev,
 306                                 "clkout1", dclk_variant->clkout1_parent_names,
 307                                 dclk_variant->clkout1_num_parents, 8, 7);
 308
 309         for (i = 0; i < DCLK_MAX_CLKS; i++)
 310                 if (IS_ERR(clk_table[i])) {
 311                         dev_err(&pdev->dev, "clock %d failed to register\n", i);
 312                         ret = PTR_ERR(clk_table[i]);
 313                         goto err_clk_register;
 314                 }
 315
 316         ret = clk_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
 317         if (!ret)
 318                 ret = clk_register_clkdev(clk_table[MUX_DCLK1], "dclk1", NULL);
 319         if (!ret)
 320                 ret = clk_register_clkdev(clk_table[MUX_CLKOUT0],
 321                                           "clkout0", NULL);
 322         if (!ret)
 323                 ret = clk_register_clkdev(clk_table[MUX_CLKOUT1],
 324                                           "clkout1", NULL);
 325         if (ret) {
 326                 dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
 327                 goto err_clk_register;
 328         }
 329
 330         s3c24xx_dclk->dclk0_div_change_nb.notifier_call =
 331                                                 s3c24xx_dclk0_div_notify;
 332
 333         s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
 334                                                 s3c24xx_dclk1_div_notify;
 335
 336         ret = clk_notifier_register(clk_table[DIV_DCLK0],
 337                                     &s3c24xx_dclk->dclk0_div_change_nb);
 338         if (ret)
 339                 goto err_clk_register;
 340
 341         ret = clk_notifier_register(clk_table[DIV_DCLK1],
 342                                     &s3c24xx_dclk->dclk1_div_change_nb);
 343         if (ret)
 344                 goto err_dclk_notify;
 345
 346         return 0;
 347
 348 err_dclk_notify:
 349         clk_notifier_unregister(clk_table[DIV_DCLK0],
 350                                 &s3c24xx_dclk->dclk0_div_change_nb);
 351 err_clk_register:
 352         for (i = 0; i < DCLK_MAX_CLKS; i++)
 353                 if (clk_table[i] && !IS_ERR(clk_table[i]))
 354                         clk_unregister(clk_table[i]);
 355
 356         return ret;
 357 }
 358
 359 static int s3c24xx_dclk_remove(struct platform_device *pdev)
 360 {
 361         struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
 362         struct clk **clk_table = s3c24xx_dclk->clk_data.clks;
 363         int i;
 364
 365         clk_notifier_unregister(clk_table[DIV_DCLK1],
 366                                 &s3c24xx_dclk->dclk1_div_change_nb);
 367         clk_notifier_unregister(clk_table[DIV_DCLK0],
 368                                 &s3c24xx_dclk->dclk0_div_change_nb);
 369
 370         for (i = 0; i < DCLK_MAX_CLKS; i++)
 371                 clk_unregister(clk_table[i]);
 372
 373         return 0;
 374 }
 375
 376 static struct s3c24xx_dclk_drv_data dclk_variants[] = {
 377         [S3C2410] = {
 378                 .clkout0_parent_names = clkout0_s3c2410_p,
 379                 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p),
 380                 .clkout1_parent_names = clkout1_s3c2410_p,
 381                 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p),
 382                 .mux_parent_names = dclk_s3c2410_p,
 383                 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
 384         },
 385         [S3C2412] = {
 386                 .clkout0_parent_names = clkout0_s3c2412_p,
 387                 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p),
 388                 .clkout1_parent_names = clkout1_s3c2412_p,
 389                 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p),
 390                 .mux_parent_names = dclk_s3c2410_p,
 391                 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
 392         },
 393         [S3C2440] = {
 394                 .clkout0_parent_names = clkout0_s3c2440_p,
 395                 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p),
 396                 .clkout1_parent_names = clkout1_s3c2440_p,
 397                 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p),
 398                 .mux_parent_names = dclk_s3c2410_p,
 399                 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
 400         },
 401         [S3C2443] = {
 402                 .clkout0_parent_names = clkout0_s3c2443_p,
 403                 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p),
 404                 .clkout1_parent_names = clkout1_s3c2443_p,
 405                 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p),
 406                 .mux_parent_names = dclk_s3c2443_p,
 407                 .mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p),
 408         },
 409 };
 410
 411 static const struct platform_device_id s3c24xx_dclk_driver_ids[] = {
 412         {
 413                 .name           = "s3c2410-dclk",
 414                 .driver_data    = (kernel_ulong_t)&dclk_variants[S3C2410],
 415         }, {
 416                 .name           = "s3c2412-dclk",
 417                 .driver_data    = (kernel_ulong_t)&dclk_variants[S3C2412],
 418         }, {
 419                 .name           = "s3c2440-dclk",
 420                 .driver_data    = (kernel_ulong_t)&dclk_variants[S3C2440],
 421         }, {
 422                 .name           = "s3c2443-dclk",
 423                 .driver_data    = (kernel_ulong_t)&dclk_variants[S3C2443],
 424         },
 425         { }
 426 };
 427
 428 MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);
 429
 430 static struct platform_driver s3c24xx_dclk_driver = {
 431         .driver = {
 432                 .name           = "s3c24xx-dclk",
 433                 .pm             = &s3c24xx_dclk_pm_ops,
 434         },
 435         .probe = s3c24xx_dclk_probe,
 436         .remove = s3c24xx_dclk_remove,
 437         .id_table = s3c24xx_dclk_driver_ids,
 438 };
 439 module_platform_driver(s3c24xx_dclk_driver);
 440
 441 MODULE_LICENSE("GPL v2");
 442 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
 443 MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs");