drivers/clk/spear/spear6xx_clock.c

   1 /*
   2  * SPEAr6xx machines clock framework source file
   3  *
   4  * Copyright (C) 2012 ST Microelectronics
   5  * Viresh Kumar <vireshk@kernel.org>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/clkdev.h>
  13 #include <linux/io.h>
  14 #include <linux/spinlock_types.h>
  15 #include "clk.h"
  16
  17 static DEFINE_SPINLOCK(_lock);
  18
  19 #define PLL1_CTR                        (misc_base + 0x008)
  20 #define PLL1_FRQ                        (misc_base + 0x00C)
  21 #define PLL2_CTR                        (misc_base + 0x014)
  22 #define PLL2_FRQ                        (misc_base + 0x018)
  23 #define PLL_CLK_CFG                     (misc_base + 0x020)
  24         /* PLL_CLK_CFG register masks */
  25         #define MCTR_CLK_SHIFT          28
  26         #define MCTR_CLK_MASK           3
  27
  28 #define CORE_CLK_CFG                    (misc_base + 0x024)
  29         /* CORE CLK CFG register masks */
  30         #define HCLK_RATIO_SHIFT        10
  31         #define HCLK_RATIO_MASK         2
  32         #define PCLK_RATIO_SHIFT        8
  33         #define PCLK_RATIO_MASK         2
  34
  35 #define PERIP_CLK_CFG                   (misc_base + 0x028)
  36         /* PERIP_CLK_CFG register masks */
  37         #define CLCD_CLK_SHIFT          2
  38         #define CLCD_CLK_MASK           2
  39         #define UART_CLK_SHIFT          4
  40         #define UART_CLK_MASK           1
  41         #define FIRDA_CLK_SHIFT         5
  42         #define FIRDA_CLK_MASK          2
  43         #define GPT0_CLK_SHIFT          8
  44         #define GPT1_CLK_SHIFT          10
  45         #define GPT2_CLK_SHIFT          11
  46         #define GPT3_CLK_SHIFT          12
  47         #define GPT_CLK_MASK            1
  48
  49 #define PERIP1_CLK_ENB                  (misc_base + 0x02C)
  50         /* PERIP1_CLK_ENB register masks */
  51         #define UART0_CLK_ENB           3
  52         #define UART1_CLK_ENB           4
  53         #define SSP0_CLK_ENB            5
  54         #define SSP1_CLK_ENB            6
  55         #define I2C_CLK_ENB             7
  56         #define JPEG_CLK_ENB            8
  57         #define FSMC_CLK_ENB            9
  58         #define FIRDA_CLK_ENB           10
  59         #define GPT2_CLK_ENB            11
  60         #define GPT3_CLK_ENB            12
  61         #define GPIO2_CLK_ENB           13
  62         #define SSP2_CLK_ENB            14
  63         #define ADC_CLK_ENB             15
  64         #define GPT1_CLK_ENB            11
  65         #define RTC_CLK_ENB             17
  66         #define GPIO1_CLK_ENB           18
  67         #define DMA_CLK_ENB             19
  68         #define SMI_CLK_ENB             21
  69         #define CLCD_CLK_ENB            22
  70         #define GMAC_CLK_ENB            23
  71         #define USBD_CLK_ENB            24
  72         #define USBH0_CLK_ENB           25
  73         #define USBH1_CLK_ENB           26
  74
  75 #define PRSC0_CLK_CFG                   (misc_base + 0x044)
  76 #define PRSC1_CLK_CFG                   (misc_base + 0x048)
  77 #define PRSC2_CLK_CFG                   (misc_base + 0x04C)
  78
  79 #define CLCD_CLK_SYNT                   (misc_base + 0x05C)
  80 #define FIRDA_CLK_SYNT                  (misc_base + 0x060)
  81 #define UART_CLK_SYNT                   (misc_base + 0x064)
  82
  83 /* vco rate configuration table, in ascending order of rates */
  84 static struct pll_rate_tbl pll_rtbl[] = {
  85         {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
  86         {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
  87         {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
  88 };
  89
  90 /* aux rate configuration table, in ascending order of rates */
  91 static struct aux_rate_tbl aux_rtbl[] = {
  92         /* For PLL1 = 332 MHz */
  93         {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
  94         {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
  95         {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
  96         {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
  97 };
  98
  99 static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
 100 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
 101 static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
 102 static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
 103 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
 104 static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
 105 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
 106         "pll2_clk", };
 107
 108 /* gpt rate configuration table, in ascending order of rates */
 109 static struct gpt_rate_tbl gpt_rtbl[] = {
 110         /* For pll1 = 332 MHz */
 111         {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
 112         {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
 113         {.mscale = 1, .nscale = 0}, /* 83 MHz */
 114 };
 115
 116 void __init spear6xx_clk_init(void __iomem *misc_base)
 117 {
 118         struct clk *clk, *clk1;
 119
 120         clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
 121                         32000);
 122         clk_register_clkdev(clk, "osc_32k_clk", NULL);
 123
 124         clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT,
 125                         30000000);
 126         clk_register_clkdev(clk, "osc_30m_clk", NULL);
 127
 128         /* clock derived from 32 KHz osc clk */
 129         clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
 130                         PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
 131         clk_register_clkdev(clk, NULL, "rtc-spear");
 132
 133         /* clock derived from 30 MHz osc clk */
 134         clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
 135                         48000000);
 136         clk_register_clkdev(clk, "pll3_clk", NULL);
 137
 138         clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
 139                         0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
 140                         &_lock, &clk1, NULL);
 141         clk_register_clkdev(clk, "vco1_clk", NULL);
 142         clk_register_clkdev(clk1, "pll1_clk", NULL);
 143
 144         clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
 145                         0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
 146                         &_lock, &clk1, NULL);
 147         clk_register_clkdev(clk, "vco2_clk", NULL);
 148         clk_register_clkdev(clk1, "pll2_clk", NULL);
 149
 150         clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
 151                         1);
 152         clk_register_clkdev(clk, NULL, "wdt");
 153
 154         /* clock derived from pll1 clk */
 155         clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
 156                         CLK_SET_RATE_PARENT, 1, 1);
 157         clk_register_clkdev(clk, "cpu_clk", NULL);
 158
 159         clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
 160                         CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
 161                         HCLK_RATIO_MASK, 0, &_lock);
 162         clk_register_clkdev(clk, "ahb_clk", NULL);
 163
 164         clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
 165                         UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
 166                         &_lock, &clk1);
 167         clk_register_clkdev(clk, "uart_syn_clk", NULL);
 168         clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
 169
 170         clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
 171                         ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
 172                         PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
 173                         &_lock);
 174         clk_register_clkdev(clk, "uart_mclk", NULL);
 175
 176         clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
 177                         UART0_CLK_ENB, 0, &_lock);
 178         clk_register_clkdev(clk, NULL, "d0000000.serial");
 179
 180         clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
 181                         UART1_CLK_ENB, 0, &_lock);
 182         clk_register_clkdev(clk, NULL, "d0080000.serial");
 183
 184         clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
 185                         0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
 186                         &_lock, &clk1);
 187         clk_register_clkdev(clk, "firda_syn_clk", NULL);
 188         clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
 189
 190         clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
 191                         ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
 192                         PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
 193                         &_lock);
 194         clk_register_clkdev(clk, "firda_mclk", NULL);
 195
 196         clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
 197                         PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
 198         clk_register_clkdev(clk, NULL, "firda");
 199
 200         clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
 201                         0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
 202                         &_lock, &clk1);
 203         clk_register_clkdev(clk, "clcd_syn_clk", NULL);
 204         clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
 205
 206         clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
 207                         ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
 208                         PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
 209                         &_lock);
 210         clk_register_clkdev(clk, "clcd_mclk", NULL);
 211
 212         clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
 213                         PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
 214         clk_register_clkdev(clk, NULL, "clcd");
 215
 216         /* gpt clocks */
 217         clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
 218                         gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
 219         clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
 220
 221         clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
 222                         ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
 223                         PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 224         clk_register_clkdev(clk, NULL, "gpt0");
 225
 226         clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
 227                         ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
 228                         PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 229         clk_register_clkdev(clk, "gpt1_mclk", NULL);
 230
 231         clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
 232                         PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
 233         clk_register_clkdev(clk, NULL, "gpt1");
 234
 235         clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
 236                         gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
 237         clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
 238
 239         clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
 240                         ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
 241                         PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 242         clk_register_clkdev(clk, "gpt2_mclk", NULL);
 243
 244         clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
 245                         PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
 246         clk_register_clkdev(clk, NULL, "gpt2");
 247
 248         clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
 249                         gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
 250         clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
 251
 252         clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
 253                         ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
 254                         PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
 255         clk_register_clkdev(clk, "gpt3_mclk", NULL);
 256
 257         clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
 258                         PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
 259         clk_register_clkdev(clk, NULL, "gpt3");
 260
 261         /* clock derived from pll3 clk */
 262         clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
 263                         PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
 264         clk_register_clkdev(clk, NULL, "e1800000.ehci");
 265         clk_register_clkdev(clk, NULL, "e1900000.ohci");
 266
 267         clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
 268                         PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
 269         clk_register_clkdev(clk, NULL, "e2000000.ehci");
 270         clk_register_clkdev(clk, NULL, "e2100000.ohci");
 271
 272         clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
 273                         USBD_CLK_ENB, 0, &_lock);
 274         clk_register_clkdev(clk, NULL, "designware_udc");
 275
 276         /* clock derived from ahb clk */
 277         clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
 278                         1);
 279         clk_register_clkdev(clk, "ahbmult2_clk", NULL);
 280
 281         clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
 282                         ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
 283                         PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
 284         clk_register_clkdev(clk, "ddr_clk", NULL);
 285
 286         clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
 287                         CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
 288                         PCLK_RATIO_MASK, 0, &_lock);
 289         clk_register_clkdev(clk, "apb_clk", NULL);
 290
 291         clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 292                         DMA_CLK_ENB, 0, &_lock);
 293         clk_register_clkdev(clk, NULL, "fc400000.dma");
 294
 295         clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 296                         FSMC_CLK_ENB, 0, &_lock);
 297         clk_register_clkdev(clk, NULL, "d1800000.flash");
 298
 299         clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 300                         GMAC_CLK_ENB, 0, &_lock);
 301         clk_register_clkdev(clk, NULL, "e0800000.ethernet");
 302
 303         clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 304                         I2C_CLK_ENB, 0, &_lock);
 305         clk_register_clkdev(clk, NULL, "d0200000.i2c");
 306
 307         clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 308                         JPEG_CLK_ENB, 0, &_lock);
 309         clk_register_clkdev(clk, NULL, "jpeg");
 310
 311         clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
 312                         SMI_CLK_ENB, 0, &_lock);
 313         clk_register_clkdev(clk, NULL, "fc000000.flash");
 314
 315         /* clock derived from apb clk */
 316         clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 317                         ADC_CLK_ENB, 0, &_lock);
 318         clk_register_clkdev(clk, NULL, "adc");
 319
 320         clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
 321         clk_register_clkdev(clk, NULL, "f0100000.gpio");
 322
 323         clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 324                         GPIO1_CLK_ENB, 0, &_lock);
 325         clk_register_clkdev(clk, NULL, "fc980000.gpio");
 326
 327         clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 328                         GPIO2_CLK_ENB, 0, &_lock);
 329         clk_register_clkdev(clk, NULL, "d8100000.gpio");
 330
 331         clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 332                         SSP0_CLK_ENB, 0, &_lock);
 333         clk_register_clkdev(clk, NULL, "ssp-pl022.0");
 334
 335         clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 336                         SSP1_CLK_ENB, 0, &_lock);
 337         clk_register_clkdev(clk, NULL, "ssp-pl022.1");
 338
 339         clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 340                         SSP2_CLK_ENB, 0, &_lock);
 341         clk_register_clkdev(clk, NULL, "ssp-pl022.2");
 342 }