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of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / drivers / dma / at_xdmac.c
blob370c661c7d7b25c237a3376dd18da79fbd44eadd
1 /*
2 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
3 *
4 * Copyright (C) 2014 Atmel Corporation
5 *
6 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <asm/barrier.h>
22 #include <dt-bindings/dma/at91.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dmapool.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/kernel.h>
29 #include <linux/list.h>
30 #include <linux/module.h>
31 #include <linux/of_dma.h>
32 #include <linux/of_platform.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm.h>
35
36 #include "dmaengine.h"
37
38 /* Global registers */
39 #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
40 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
41 #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
42 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
43 #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
44 #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
45 #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
46 #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
47 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
48 #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
49 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
50 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
51 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
52 #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
53 #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
54 #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
55 #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
56 #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
57 #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
58 #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
59 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
60
61 /* Channel relative registers offsets */
62 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
63 #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
64 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
65 #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
66 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
67 #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
68 #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
69 #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
70 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
71 #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
72 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
73 #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
74 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
75 #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
76 #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
77 #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
78 #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
79 #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
80 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
81 #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
82 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
83 #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
84 #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
85 #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
86 #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
87 #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
88 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
89 #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
90 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
91 #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
92 #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
93 #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
94 #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
95 #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
96 #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
97 #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
98 #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
99 #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
100 #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
101 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
102 #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
103 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
104 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
106 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
107 #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
108 #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
109 #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
110 #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
111 #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
112 #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
113 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
114 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
115 #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
116 #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
117 #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
118 #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
119 #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
120 #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
121 #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
122 #define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
123 #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
124 #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
125 #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
126 #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
127 #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
128 #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
129 #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
130 #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
131 #define AT_XDMAC_CC_DWIDTH_OFFSET 11
132 #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
133 #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
134 #define AT_XDMAC_CC_DWIDTH_BYTE 0x0
135 #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
136 #define AT_XDMAC_CC_DWIDTH_WORD 0x2
137 #define AT_XDMAC_CC_DWIDTH_DWORD 0x3
138 #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
139 #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
140 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
141 #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
142 #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
143 #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
144 #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
145 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
146 #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
147 #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
148 #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
149 #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
150 #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
151 #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
152 #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
153 #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
154 #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
155 #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
156 #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
157 #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
158 #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
159 #define AT_XDMAC_CC_PERID(i) (0x7f & (i) << 24) /* Channel Peripheral Identifier */
160 #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
161 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
162 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
163
164 #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
165
166 /* Microblock control members */
167 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
168 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
169 #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
170 #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
171 #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
172 #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
173 #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
174 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
175
176 #define AT_XDMAC_MAX_CHAN 0x20
177 #define AT_XDMAC_MAX_CSIZE 16 /* 16 data */
178 #define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */
179
180 #define AT_XDMAC_DMA_BUSWIDTHS\
181 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
182 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
183 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
184 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
185 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
186
187 enum atc_status {
188 AT_XDMAC_CHAN_IS_CYCLIC = 0,
189 AT_XDMAC_CHAN_IS_PAUSED,
190 };
191
192 /* ----- Channels ----- */
193 struct at_xdmac_chan {
194 struct dma_chan chan;
195 void __iomem *ch_regs;
196 u32 mask; /* Channel Mask */
197 u32 cfg; /* Channel Configuration Register */
198 u8 perid; /* Peripheral ID */
199 u8 perif; /* Peripheral Interface */
200 u8 memif; /* Memory Interface */
201 u32 save_cc;
202 u32 save_cim;
203 u32 save_cnda;
204 u32 save_cndc;
205 unsigned long status;
206 struct tasklet_struct tasklet;
207 struct dma_slave_config sconfig;
208
209 spinlock_t lock;
210
211 struct list_head xfers_list;
212 struct list_head free_descs_list;
213 };
214
215
216 /* ----- Controller ----- */
217 struct at_xdmac {
218 struct dma_device dma;
219 void __iomem *regs;
220 int irq;
221 struct clk *clk;
222 u32 save_gim;
223 u32 save_gs;
224 struct dma_pool *at_xdmac_desc_pool;
225 struct at_xdmac_chan chan[0];
226 };
227
228
229 /* ----- Descriptors ----- */
230
231 /* Linked List Descriptor */
232 struct at_xdmac_lld {
233 dma_addr_t mbr_nda; /* Next Descriptor Member */
234 u32 mbr_ubc; /* Microblock Control Member */
235 dma_addr_t mbr_sa; /* Source Address Member */
236 dma_addr_t mbr_da; /* Destination Address Member */
237 u32 mbr_cfg; /* Configuration Register */
238 u32 mbr_bc; /* Block Control Register */
239 u32 mbr_ds; /* Data Stride Register */
240 u32 mbr_sus; /* Source Microblock Stride Register */
241 u32 mbr_dus; /* Destination Microblock Stride Register */
242 };
243
244
245 struct at_xdmac_desc {
246 struct at_xdmac_lld lld;
247 enum dma_transfer_direction direction;
248 struct dma_async_tx_descriptor tx_dma_desc;
249 struct list_head desc_node;
250 /* Following members are only used by the first descriptor */
251 bool active_xfer;
252 unsigned int xfer_size;
253 struct list_head descs_list;
254 struct list_head xfer_node;
255 };
256
257 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
258 {
259 return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
260 }
261
262 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
263 #define at_xdmac_write(atxdmac, reg, value) \
264 writel_relaxed((value), (atxdmac)->regs + (reg))
265
266 #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
267 #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
268
269 static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
270 {
271 return container_of(dchan, struct at_xdmac_chan, chan);
272 }
273
274 static struct device *chan2dev(struct dma_chan *chan)
275 {
276 return &chan->dev->device;
277 }
278
279 static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
280 {
281 return container_of(ddev, struct at_xdmac, dma);
282 }
283
284 static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
285 {
286 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
287 }
288
289 static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
290 {
291 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
292 }
293
294 static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
295 {
296 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
297 }
298
299 static inline int at_xdmac_csize(u32 maxburst)
300 {
301 int csize;
302
303 csize = ffs(maxburst) - 1;
304 if (csize > 4)
305 csize = -EINVAL;
306
307 return csize;
308 };
309
310 static inline u8 at_xdmac_get_dwidth(u32 cfg)
311 {
312 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
313 };
314
315 static unsigned int init_nr_desc_per_channel = 64;
316 module_param(init_nr_desc_per_channel, uint, 0644);
317 MODULE_PARM_DESC(init_nr_desc_per_channel,
318 "initial descriptors per channel (default: 64)");
319
320
321 static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
322 {
323 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
324 }
325
326 static void at_xdmac_off(struct at_xdmac *atxdmac)
327 {
328 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
329
330 /* Wait that all chans are disabled. */
331 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
332 cpu_relax();
333
334 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
335 }
336
337 /* Call with lock hold. */
338 static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
339 struct at_xdmac_desc *first)
340 {
341 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
342 u32 reg;
343
344 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
345
346 if (at_xdmac_chan_is_enabled(atchan))
347 return;
348
349 /* Set transfer as active to not try to start it again. */
350 first->active_xfer = true;
351
352 /* Tell xdmac where to get the first descriptor. */
353 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
354 | AT_XDMAC_CNDA_NDAIF(atchan->memif);
355 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
356
357 /*
358 * When doing non cyclic transfer we need to use the next
359 * descriptor view 2 since some fields of the configuration register
360 * depend on transfer size and src/dest addresses.
361 */
362 if (at_xdmac_chan_is_cyclic(atchan))
363 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
364 else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3)
365 reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
366 else
367 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
368 /*
369 * Even if the register will be updated from the configuration in the
370 * descriptor when using view 2 or higher, the PROT bit won't be set
371 * properly. This bit can be modified only by using the channel
372 * configuration register.
373 */
374 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
375
376 reg |= AT_XDMAC_CNDC_NDDUP
377 | AT_XDMAC_CNDC_NDSUP
378 | AT_XDMAC_CNDC_NDE;
379 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
380
381 dev_vdbg(chan2dev(&atchan->chan),
382 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
383 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
384 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
385 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
386 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
387 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
388 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
389
390 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
391 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE;
392 /*
393 * There is no end of list when doing cyclic dma, we need to get
394 * an interrupt after each periods.
395 */
396 if (at_xdmac_chan_is_cyclic(atchan))
397 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
398 reg | AT_XDMAC_CIE_BIE);
399 else
400 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
401 reg | AT_XDMAC_CIE_LIE);
402 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
403 dev_vdbg(chan2dev(&atchan->chan),
404 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
405 wmb();
406 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
407
408 dev_vdbg(chan2dev(&atchan->chan),
409 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
410 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
411 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
412 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
413 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
414 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
415 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
416
417 }
418
419 static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
420 {
421 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
422 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
423 dma_cookie_t cookie;
424 unsigned long irqflags;
425
426 spin_lock_irqsave(&atchan->lock, irqflags);
427 cookie = dma_cookie_assign(tx);
428
429 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
430 __func__, atchan, desc);
431 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
432 if (list_is_singular(&atchan->xfers_list))
433 at_xdmac_start_xfer(atchan, desc);
434
435 spin_unlock_irqrestore(&atchan->lock, irqflags);
436 return cookie;
437 }
438
439 static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
440 gfp_t gfp_flags)
441 {
442 struct at_xdmac_desc *desc;
443 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
444 dma_addr_t phys;
445
446 desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
447 if (desc) {
448 memset(desc, 0, sizeof(*desc));
449 INIT_LIST_HEAD(&desc->descs_list);
450 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
451 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
452 desc->tx_dma_desc.phys = phys;
453 }
454
455 return desc;
456 }
457
458 void at_xdmac_init_used_desc(struct at_xdmac_desc *desc)
459 {
460 memset(&desc->lld, 0, sizeof(desc->lld));
461 INIT_LIST_HEAD(&desc->descs_list);
462 desc->direction = DMA_TRANS_NONE;
463 desc->xfer_size = 0;
464 desc->active_xfer = false;
465 }
466
467 /* Call must be protected by lock. */
468 static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
469 {
470 struct at_xdmac_desc *desc;
471
472 if (list_empty(&atchan->free_descs_list)) {
473 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
474 } else {
475 desc = list_first_entry(&atchan->free_descs_list,
476 struct at_xdmac_desc, desc_node);
477 list_del(&desc->desc_node);
478 at_xdmac_init_used_desc(desc);
479 }
480
481 return desc;
482 }
483
484 static void at_xdmac_queue_desc(struct dma_chan *chan,
485 struct at_xdmac_desc *prev,
486 struct at_xdmac_desc *desc)
487 {
488 if (!prev || !desc)
489 return;
490
491 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
492 prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE;
493
494 dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
495 __func__, prev, &prev->lld.mbr_nda);
496 }
497
498 static inline void at_xdmac_increment_block_count(struct dma_chan *chan,
499 struct at_xdmac_desc *desc)
500 {
501 if (!desc)
502 return;
503
504 desc->lld.mbr_bc++;
505
506 dev_dbg(chan2dev(chan),
507 "%s: incrementing the block count of the desc 0x%p\n",
508 __func__, desc);
509 }
510
511 static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
512 struct of_dma *of_dma)
513 {
514 struct at_xdmac *atxdmac = of_dma->of_dma_data;
515 struct at_xdmac_chan *atchan;
516 struct dma_chan *chan;
517 struct device *dev = atxdmac->dma.dev;
518
519 if (dma_spec->args_count != 1) {
520 dev_err(dev, "dma phandler args: bad number of args\n");
521 return NULL;
522 }
523
524 chan = dma_get_any_slave_channel(&atxdmac->dma);
525 if (!chan) {
526 dev_err(dev, "can't get a dma channel\n");
527 return NULL;
528 }
529
530 atchan = to_at_xdmac_chan(chan);
531 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
532 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
533 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
534 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
535 atchan->memif, atchan->perif, atchan->perid);
536
537 return chan;
538 }
539
540 static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
541 enum dma_transfer_direction direction)
542 {
543 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
544 int csize, dwidth;
545
546 if (direction == DMA_DEV_TO_MEM) {
547 atchan->cfg =
548 AT91_XDMAC_DT_PERID(atchan->perid)
549 | AT_XDMAC_CC_DAM_INCREMENTED_AM
550 | AT_XDMAC_CC_SAM_FIXED_AM
551 | AT_XDMAC_CC_DIF(atchan->memif)
552 | AT_XDMAC_CC_SIF(atchan->perif)
553 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
554 | AT_XDMAC_CC_DSYNC_PER2MEM
555 | AT_XDMAC_CC_MBSIZE_SIXTEEN
556 | AT_XDMAC_CC_TYPE_PER_TRAN;
557 csize = ffs(atchan->sconfig.src_maxburst) - 1;
558 if (csize < 0) {
559 dev_err(chan2dev(chan), "invalid src maxburst value\n");
560 return -EINVAL;
561 }
562 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
563 dwidth = ffs(atchan->sconfig.src_addr_width) - 1;
564 if (dwidth < 0) {
565 dev_err(chan2dev(chan), "invalid src addr width value\n");
566 return -EINVAL;
567 }
568 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
569 } else if (direction == DMA_MEM_TO_DEV) {
570 atchan->cfg =
571 AT91_XDMAC_DT_PERID(atchan->perid)
572 | AT_XDMAC_CC_DAM_FIXED_AM
573 | AT_XDMAC_CC_SAM_INCREMENTED_AM
574 | AT_XDMAC_CC_DIF(atchan->perif)
575 | AT_XDMAC_CC_SIF(atchan->memif)
576 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
577 | AT_XDMAC_CC_DSYNC_MEM2PER
578 | AT_XDMAC_CC_MBSIZE_SIXTEEN
579 | AT_XDMAC_CC_TYPE_PER_TRAN;
580 csize = ffs(atchan->sconfig.dst_maxburst) - 1;
581 if (csize < 0) {
582 dev_err(chan2dev(chan), "invalid src maxburst value\n");
583 return -EINVAL;
584 }
585 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
586 dwidth = ffs(atchan->sconfig.dst_addr_width) - 1;
587 if (dwidth < 0) {
588 dev_err(chan2dev(chan), "invalid dst addr width value\n");
589 return -EINVAL;
590 }
591 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
592 }
593
594 dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg);
595
596 return 0;
597 }
598
599 /*
600 * Only check that maxburst and addr width values are supported by the
601 * the controller but not that the configuration is good to perform the
602 * transfer since we don't know the direction at this stage.
603 */
604 static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig)
605 {
606 if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE)
607 || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE))
608 return -EINVAL;
609
610 if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH)
611 || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH))
612 return -EINVAL;
613
614 return 0;
615 }
616
617 static int at_xdmac_set_slave_config(struct dma_chan *chan,
618 struct dma_slave_config *sconfig)
619 {
620 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
621
622 if (at_xdmac_check_slave_config(sconfig)) {
623 dev_err(chan2dev(chan), "invalid slave configuration\n");
624 return -EINVAL;
625 }
626
627 memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig));
628
629 return 0;
630 }
631
632 static struct dma_async_tx_descriptor *
633 at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
634 unsigned int sg_len, enum dma_transfer_direction direction,
635 unsigned long flags, void *context)
636 {
637 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
638 struct at_xdmac_desc *first = NULL, *prev = NULL;
639 struct scatterlist *sg;
640 int i;
641 unsigned int xfer_size = 0;
642 unsigned long irqflags;
643 struct dma_async_tx_descriptor *ret = NULL;
644
645 if (!sgl)
646 return NULL;
647
648 if (!is_slave_direction(direction)) {
649 dev_err(chan2dev(chan), "invalid DMA direction\n");
650 return NULL;
651 }
652
653 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
654 __func__, sg_len,
655 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
656 flags);
657
658 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
659 spin_lock_irqsave(&atchan->lock, irqflags);
660
661 if (at_xdmac_compute_chan_conf(chan, direction))
662 goto spin_unlock;
663
664 /* Prepare descriptors. */
665 for_each_sg(sgl, sg, sg_len, i) {
666 struct at_xdmac_desc *desc = NULL;
667 u32 len, mem, dwidth, fixed_dwidth;
668
669 len = sg_dma_len(sg);
670 mem = sg_dma_address(sg);
671 if (unlikely(!len)) {
672 dev_err(chan2dev(chan), "sg data length is zero\n");
673 goto spin_unlock;
674 }
675 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
676 __func__, i, len, mem);
677
678 desc = at_xdmac_get_desc(atchan);
679 if (!desc) {
680 dev_err(chan2dev(chan), "can't get descriptor\n");
681 if (first)
682 list_splice_init(&first->descs_list, &atchan->free_descs_list);
683 goto spin_unlock;
684 }
685
686 /* Linked list descriptor setup. */
687 if (direction == DMA_DEV_TO_MEM) {
688 desc->lld.mbr_sa = atchan->sconfig.src_addr;
689 desc->lld.mbr_da = mem;
690 } else {
691 desc->lld.mbr_sa = mem;
692 desc->lld.mbr_da = atchan->sconfig.dst_addr;
693 }
694 dwidth = at_xdmac_get_dwidth(atchan->cfg);
695 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
696 ? dwidth
697 : AT_XDMAC_CC_DWIDTH_BYTE;
698 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
699 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
700 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
701 | (len >> fixed_dwidth); /* microblock length */
702 desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |
703 AT_XDMAC_CC_DWIDTH(fixed_dwidth);
704 dev_dbg(chan2dev(chan),
705 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
706 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
707
708 /* Chain lld. */
709 if (prev)
710 at_xdmac_queue_desc(chan, prev, desc);
711
712 prev = desc;
713 if (!first)
714 first = desc;
715
716 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
717 __func__, desc, first);
718 list_add_tail(&desc->desc_node, &first->descs_list);
719 xfer_size += len;
720 }
721
722
723 first->tx_dma_desc.flags = flags;
724 first->xfer_size = xfer_size;
725 first->direction = direction;
726 ret = &first->tx_dma_desc;
727
728 spin_unlock:
729 spin_unlock_irqrestore(&atchan->lock, irqflags);
730 return ret;
731 }
732
733 static struct dma_async_tx_descriptor *
734 at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
735 size_t buf_len, size_t period_len,
736 enum dma_transfer_direction direction,
737 unsigned long flags)
738 {
739 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
740 struct at_xdmac_desc *first = NULL, *prev = NULL;
741 unsigned int periods = buf_len / period_len;
742 int i;
743 unsigned long irqflags;
744
745 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
746 __func__, &buf_addr, buf_len, period_len,
747 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
748
749 if (!is_slave_direction(direction)) {
750 dev_err(chan2dev(chan), "invalid DMA direction\n");
751 return NULL;
752 }
753
754 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
755 dev_err(chan2dev(chan), "channel currently used\n");
756 return NULL;
757 }
758
759 if (at_xdmac_compute_chan_conf(chan, direction))
760 return NULL;
761
762 for (i = 0; i < periods; i++) {
763 struct at_xdmac_desc *desc = NULL;
764
765 spin_lock_irqsave(&atchan->lock, irqflags);
766 desc = at_xdmac_get_desc(atchan);
767 if (!desc) {
768 dev_err(chan2dev(chan), "can't get descriptor\n");
769 if (first)
770 list_splice_init(&first->descs_list, &atchan->free_descs_list);
771 spin_unlock_irqrestore(&atchan->lock, irqflags);
772 return NULL;
773 }
774 spin_unlock_irqrestore(&atchan->lock, irqflags);
775 dev_dbg(chan2dev(chan),
776 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
777 __func__, desc, &desc->tx_dma_desc.phys);
778
779 if (direction == DMA_DEV_TO_MEM) {
780 desc->lld.mbr_sa = atchan->sconfig.src_addr;
781 desc->lld.mbr_da = buf_addr + i * period_len;
782 } else {
783 desc->lld.mbr_sa = buf_addr + i * period_len;
784 desc->lld.mbr_da = atchan->sconfig.dst_addr;
785 }
786 desc->lld.mbr_cfg = atchan->cfg;
787 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
788 | AT_XDMAC_MBR_UBC_NDEN
789 | AT_XDMAC_MBR_UBC_NSEN
790 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
791
792 dev_dbg(chan2dev(chan),
793 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
794 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
795
796 /* Chain lld. */
797 if (prev)
798 at_xdmac_queue_desc(chan, prev, desc);
799
800 prev = desc;
801 if (!first)
802 first = desc;
803
804 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
805 __func__, desc, first);
806 list_add_tail(&desc->desc_node, &first->descs_list);
807 }
808
809 at_xdmac_queue_desc(chan, prev, first);
810 first->tx_dma_desc.flags = flags;
811 first->xfer_size = buf_len;
812 first->direction = direction;
813
814 return &first->tx_dma_desc;
815 }
816
817 static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr)
818 {
819 u32 width;
820
821 /*
822 * Check address alignment to select the greater data width we
823 * can use.
824 *
825 * Some XDMAC implementations don't provide dword transfer, in
826 * this case selecting dword has the same behavior as
827 * selecting word transfers.
828 */
829 if (!(addr & 7)) {
830 width = AT_XDMAC_CC_DWIDTH_DWORD;
831 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
832 } else if (!(addr & 3)) {
833 width = AT_XDMAC_CC_DWIDTH_WORD;
834 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
835 } else if (!(addr & 1)) {
836 width = AT_XDMAC_CC_DWIDTH_HALFWORD;
837 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
838 } else {
839 width = AT_XDMAC_CC_DWIDTH_BYTE;
840 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
841 }
842
843 return width;
844 }
845
846 static struct at_xdmac_desc *
847 at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
848 struct at_xdmac_chan *atchan,
849 struct at_xdmac_desc *prev,
850 dma_addr_t src, dma_addr_t dst,
851 struct dma_interleaved_template *xt,
852 struct data_chunk *chunk)
853 {
854 struct at_xdmac_desc *desc;
855 u32 dwidth;
856 unsigned long flags;
857 size_t ublen;
858 /*
859 * WARNING: The channel configuration is set here since there is no
860 * dmaengine_slave_config call in this case. Moreover we don't know the
861 * direction, it involves we can't dynamically set the source and dest
862 * interface so we have to use the same one. Only interface 0 allows EBI
863 * access. Hopefully we can access DDR through both ports (at least on
864 * SAMA5D4x), so we can use the same interface for source and dest,
865 * that solves the fact we don't know the direction.
866 */
867 u32 chan_cc = AT_XDMAC_CC_DIF(0)
868 | AT_XDMAC_CC_SIF(0)
869 | AT_XDMAC_CC_MBSIZE_SIXTEEN
870 | AT_XDMAC_CC_TYPE_MEM_TRAN;
871
872 dwidth = at_xdmac_align_width(chan, src | dst | chunk->size);
873 if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
874 dev_dbg(chan2dev(chan),
875 "%s: chunk too big (%d, max size %lu)...\n",
876 __func__, chunk->size,
877 AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth);
878 return NULL;
879 }
880
881 if (prev)
882 dev_dbg(chan2dev(chan),
883 "Adding items at the end of desc 0x%p\n", prev);
884
885 if (xt->src_inc) {
886 if (xt->src_sgl)
887 chan_cc |= AT_XDMAC_CC_SAM_UBS_AM;
888 else
889 chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM;
890 }
891
892 if (xt->dst_inc) {
893 if (xt->dst_sgl)
894 chan_cc |= AT_XDMAC_CC_DAM_UBS_AM;
895 else
896 chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM;
897 }
898
899 spin_lock_irqsave(&atchan->lock, flags);
900 desc = at_xdmac_get_desc(atchan);
901 spin_unlock_irqrestore(&atchan->lock, flags);
902 if (!desc) {
903 dev_err(chan2dev(chan), "can't get descriptor\n");
904 return NULL;
905 }
906
907 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
908
909 ublen = chunk->size >> dwidth;
910
911 desc->lld.mbr_sa = src;
912 desc->lld.mbr_da = dst;
913 desc->lld.mbr_sus = dmaengine_get_src_icg(xt, chunk);
914 desc->lld.mbr_dus = dmaengine_get_dst_icg(xt, chunk);
915
916 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
917 | AT_XDMAC_MBR_UBC_NDEN
918 | AT_XDMAC_MBR_UBC_NSEN
919 | ublen;
920 desc->lld.mbr_cfg = chan_cc;
921
922 dev_dbg(chan2dev(chan),
923 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
924 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da,
925 desc->lld.mbr_ubc, desc->lld.mbr_cfg);
926
927 /* Chain lld. */
928 if (prev)
929 at_xdmac_queue_desc(chan, prev, desc);
930
931 return desc;
932 }
933
934 static struct dma_async_tx_descriptor *
935 at_xdmac_prep_interleaved(struct dma_chan *chan,
936 struct dma_interleaved_template *xt,
937 unsigned long flags)
938 {
939 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
940 struct at_xdmac_desc *prev = NULL, *first = NULL;
941 dma_addr_t dst_addr, src_addr;
942 size_t src_skip = 0, dst_skip = 0, len = 0;
943 struct data_chunk *chunk;
944 int i;
945
946 if (!xt || !xt->numf || (xt->dir != DMA_MEM_TO_MEM))
947 return NULL;
948
949 /*
950 * TODO: Handle the case where we have to repeat a chain of
951 * descriptors...
952 */
953 if ((xt->numf > 1) && (xt->frame_size > 1))
954 return NULL;
955
956 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, numf=%d, frame_size=%d, flags=0x%lx\n",
957 __func__, &xt->src_start, &xt->dst_start, xt->numf,
958 xt->frame_size, flags);
959
960 src_addr = xt->src_start;
961 dst_addr = xt->dst_start;
962
963 if (xt->numf > 1) {
964 first = at_xdmac_interleaved_queue_desc(chan, atchan,
965 NULL,
966 src_addr, dst_addr,
967 xt, xt->sgl);
968
969 /* Length of the block is (BLEN+1) microblocks. */
970 for (i = 0; i < xt->numf - 1; i++)
971 at_xdmac_increment_block_count(chan, first);
972
973 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
974 __func__, first, first);
975 list_add_tail(&first->desc_node, &first->descs_list);
976 } else {
977 for (i = 0; i < xt->frame_size; i++) {
978 size_t src_icg = 0, dst_icg = 0;
979 struct at_xdmac_desc *desc;
980
981 chunk = xt->sgl + i;
982
983 dst_icg = dmaengine_get_dst_icg(xt, chunk);
984 src_icg = dmaengine_get_src_icg(xt, chunk);
985
986 src_skip = chunk->size + src_icg;
987 dst_skip = chunk->size + dst_icg;
988
989 dev_dbg(chan2dev(chan),
990 "%s: chunk size=%d, src icg=%d, dst icg=%d\n",
991 __func__, chunk->size, src_icg, dst_icg);
992
993 desc = at_xdmac_interleaved_queue_desc(chan, atchan,
994 prev,
995 src_addr, dst_addr,
996 xt, chunk);
997 if (!desc) {
998 list_splice_init(&first->descs_list,
999 &atchan->free_descs_list);
1000 return NULL;
1001 }
1002
1003 if (!first)
1004 first = desc;
1005
1006 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1007 __func__, desc, first);
1008 list_add_tail(&desc->desc_node, &first->descs_list);
1009
1010 if (xt->src_sgl)
1011 src_addr += src_skip;
1012
1013 if (xt->dst_sgl)
1014 dst_addr += dst_skip;
1015
1016 len += chunk->size;
1017 prev = desc;
1018 }
1019 }
1020
1021 first->tx_dma_desc.cookie = -EBUSY;
1022 first->tx_dma_desc.flags = flags;
1023 first->xfer_size = len;
1024
1025 return &first->tx_dma_desc;
1026 }
1027
1028 static struct dma_async_tx_descriptor *
1029 at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1030 size_t len, unsigned long flags)
1031 {
1032 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1033 struct at_xdmac_desc *first = NULL, *prev = NULL;
1034 size_t remaining_size = len, xfer_size = 0, ublen;
1035 dma_addr_t src_addr = src, dst_addr = dest;
1036 u32 dwidth;
1037 /*
1038 * WARNING: We don't know the direction, it involves we can't
1039 * dynamically set the source and dest interface so we have to use the
1040 * same one. Only interface 0 allows EBI access. Hopefully we can
1041 * access DDR through both ports (at least on SAMA5D4x), so we can use
1042 * the same interface for source and dest, that solves the fact we
1043 * don't know the direction.
1044 */
1045 u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
1046 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1047 | AT_XDMAC_CC_DIF(0)
1048 | AT_XDMAC_CC_SIF(0)
1049 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1050 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1051 unsigned long irqflags;
1052
1053 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
1054 __func__, &src, &dest, len, flags);
1055
1056 if (unlikely(!len))
1057 return NULL;
1058
1059 dwidth = at_xdmac_align_width(chan, src_addr | dst_addr);
1060
1061 /* Prepare descriptors. */
1062 while (remaining_size) {
1063 struct at_xdmac_desc *desc = NULL;
1064
1065 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
1066
1067 spin_lock_irqsave(&atchan->lock, irqflags);
1068 desc = at_xdmac_get_desc(atchan);
1069 spin_unlock_irqrestore(&atchan->lock, irqflags);
1070 if (!desc) {
1071 dev_err(chan2dev(chan), "can't get descriptor\n");
1072 if (first)
1073 list_splice_init(&first->descs_list, &atchan->free_descs_list);
1074 return NULL;
1075 }
1076
1077 /* Update src and dest addresses. */
1078 src_addr += xfer_size;
1079 dst_addr += xfer_size;
1080
1081 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
1082 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
1083 else
1084 xfer_size = remaining_size;
1085
1086 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
1087
1088 /* Check remaining length and change data width if needed. */
1089 dwidth = at_xdmac_align_width(chan,
1090 src_addr | dst_addr | xfer_size);
1091 chan_cc &= ~AT_XDMAC_CC_DWIDTH_MASK;
1092 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1093
1094 ublen = xfer_size >> dwidth;
1095 remaining_size -= xfer_size;
1096
1097 desc->lld.mbr_sa = src_addr;
1098 desc->lld.mbr_da = dst_addr;
1099 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
1100 | AT_XDMAC_MBR_UBC_NDEN
1101 | AT_XDMAC_MBR_UBC_NSEN
1102 | ublen;
1103 desc->lld.mbr_cfg = chan_cc;
1104
1105 dev_dbg(chan2dev(chan),
1106 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1107 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
1108
1109 /* Chain lld. */
1110 if (prev)
1111 at_xdmac_queue_desc(chan, prev, desc);
1112
1113 prev = desc;
1114 if (!first)
1115 first = desc;
1116
1117 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1118 __func__, desc, first);
1119 list_add_tail(&desc->desc_node, &first->descs_list);
1120 }
1121
1122 first->tx_dma_desc.flags = flags;
1123 first->xfer_size = len;
1124
1125 return &first->tx_dma_desc;
1126 }
1127
1128 static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
1129 struct at_xdmac_chan *atchan,
1130 dma_addr_t dst_addr,
1131 size_t len,
1132 int value)
1133 {
1134 struct at_xdmac_desc *desc;
1135 unsigned long flags;
1136 size_t ublen;
1137 u32 dwidth;
1138 /*
1139 * WARNING: The channel configuration is set here since there is no
1140 * dmaengine_slave_config call in this case. Moreover we don't know the
1141 * direction, it involves we can't dynamically set the source and dest
1142 * interface so we have to use the same one. Only interface 0 allows EBI
1143 * access. Hopefully we can access DDR through both ports (at least on
1144 * SAMA5D4x), so we can use the same interface for source and dest,
1145 * that solves the fact we don't know the direction.
1146 */
1147 u32 chan_cc = AT_XDMAC_CC_DAM_UBS_AM
1148 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1149 | AT_XDMAC_CC_DIF(0)
1150 | AT_XDMAC_CC_SIF(0)
1151 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1152 | AT_XDMAC_CC_MEMSET_HW_MODE
1153 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1154
1155 dwidth = at_xdmac_align_width(chan, dst_addr);
1156
1157 if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
1158 dev_err(chan2dev(chan),
1159 "%s: Transfer too large, aborting...\n",
1160 __func__);
1161 return NULL;
1162 }
1163
1164 spin_lock_irqsave(&atchan->lock, flags);
1165 desc = at_xdmac_get_desc(atchan);
1166 spin_unlock_irqrestore(&atchan->lock, flags);
1167 if (!desc) {
1168 dev_err(chan2dev(chan), "can't get descriptor\n");
1169 return NULL;
1170 }
1171
1172 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1173
1174 ublen = len >> dwidth;
1175
1176 desc->lld.mbr_da = dst_addr;
1177 desc->lld.mbr_ds = value;
1178 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
1179 | AT_XDMAC_MBR_UBC_NDEN
1180 | AT_XDMAC_MBR_UBC_NSEN
1181 | ublen;
1182 desc->lld.mbr_cfg = chan_cc;
1183
1184 dev_dbg(chan2dev(chan),
1185 "%s: lld: mbr_da=%pad, mbr_ds=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1186 __func__, &desc->lld.mbr_da, &desc->lld.mbr_ds, desc->lld.mbr_ubc,
1187 desc->lld.mbr_cfg);
1188
1189 return desc;
1190 }
1191
1192 struct dma_async_tx_descriptor *
1193 at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
1194 size_t len, unsigned long flags)
1195 {
1196 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1197 struct at_xdmac_desc *desc;
1198
1199 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n",
1200 __func__, &dest, len, value, flags);
1201
1202 if (unlikely(!len))
1203 return NULL;
1204
1205 desc = at_xdmac_memset_create_desc(chan, atchan, dest, len, value);
1206 list_add_tail(&desc->desc_node, &desc->descs_list);
1207
1208 desc->tx_dma_desc.cookie = -EBUSY;
1209 desc->tx_dma_desc.flags = flags;
1210 desc->xfer_size = len;
1211
1212 return &desc->tx_dma_desc;
1213 }
1214
1215 static struct dma_async_tx_descriptor *
1216 at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl,
1217 unsigned int sg_len, int value,
1218 unsigned long flags)
1219 {
1220 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1221 struct at_xdmac_desc *desc, *pdesc = NULL,
1222 *ppdesc = NULL, *first = NULL;
1223 struct scatterlist *sg, *psg = NULL, *ppsg = NULL;
1224 size_t stride = 0, pstride = 0, len = 0;
1225 int i;
1226
1227 if (!sgl)
1228 return NULL;
1229
1230 dev_dbg(chan2dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n",
1231 __func__, sg_len, value, flags);
1232
1233 /* Prepare descriptors. */
1234 for_each_sg(sgl, sg, sg_len, i) {
1235 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n",
1236 __func__, &sg_dma_address(sg), sg_dma_len(sg),
1237 value, flags);
1238 desc = at_xdmac_memset_create_desc(chan, atchan,
1239 sg_dma_address(sg),
1240 sg_dma_len(sg),
1241 value);
1242 if (!desc && first)
1243 list_splice_init(&first->descs_list,
1244 &atchan->free_descs_list);
1245
1246 if (!first)
1247 first = desc;
1248
1249 /* Update our strides */
1250 pstride = stride;
1251 if (psg)
1252 stride = sg_dma_address(sg) -
1253 (sg_dma_address(psg) + sg_dma_len(psg));
1254
1255 /*
1256 * The scatterlist API gives us only the address and
1257 * length of each elements.
1258 *
1259 * Unfortunately, we don't have the stride, which we
1260 * will need to compute.
1261 *
1262 * That make us end up in a situation like this one:
1263 * len stride len stride len
1264 * +-------+ +-------+ +-------+
1265 * | N-2 | | N-1 | | N |
1266 * +-------+ +-------+ +-------+
1267 *
1268 * We need all these three elements (N-2, N-1 and N)
1269 * to actually take the decision on whether we need to
1270 * queue N-1 or reuse N-2.
1271 *
1272 * We will only consider N if it is the last element.
1273 */
1274 if (ppdesc && pdesc) {
1275 if ((stride == pstride) &&
1276 (sg_dma_len(ppsg) == sg_dma_len(psg))) {
1277 dev_dbg(chan2dev(chan),
1278 "%s: desc 0x%p can be merged with desc 0x%p\n",
1279 __func__, pdesc, ppdesc);
1280
1281 /*
1282 * Increment the block count of the
1283 * N-2 descriptor
1284 */
1285 at_xdmac_increment_block_count(chan, ppdesc);
1286 ppdesc->lld.mbr_dus = stride;
1287
1288 /*
1289 * Put back the N-1 descriptor in the
1290 * free descriptor list
1291 */
1292 list_add_tail(&pdesc->desc_node,
1293 &atchan->free_descs_list);
1294
1295 /*
1296 * Make our N-1 descriptor pointer
1297 * point to the N-2 since they were
1298 * actually merged.
1299 */
1300 pdesc = ppdesc;
1301
1302 /*
1303 * Rule out the case where we don't have
1304 * pstride computed yet (our second sg
1305 * element)
1306 *
1307 * We also want to catch the case where there
1308 * would be a negative stride,
1309 */
1310 } else if (pstride ||
1311 sg_dma_address(sg) < sg_dma_address(psg)) {
1312 /*
1313 * Queue the N-1 descriptor after the
1314 * N-2
1315 */
1316 at_xdmac_queue_desc(chan, ppdesc, pdesc);
1317
1318 /*
1319 * Add the N-1 descriptor to the list
1320 * of the descriptors used for this
1321 * transfer
1322 */
1323 list_add_tail(&desc->desc_node,
1324 &first->descs_list);
1325 dev_dbg(chan2dev(chan),
1326 "%s: add desc 0x%p to descs_list 0x%p\n",
1327 __func__, desc, first);
1328 }
1329 }
1330
1331 /*
1332 * If we are the last element, just see if we have the
1333 * same size than the previous element.
1334 *
1335 * If so, we can merge it with the previous descriptor
1336 * since we don't care about the stride anymore.
1337 */
1338 if ((i == (sg_len - 1)) &&
1339 sg_dma_len(psg) == sg_dma_len(sg)) {
1340 dev_dbg(chan2dev(chan),
1341 "%s: desc 0x%p can be merged with desc 0x%p\n",
1342 __func__, desc, pdesc);
1343
1344 /*
1345 * Increment the block count of the N-1
1346 * descriptor
1347 */
1348 at_xdmac_increment_block_count(chan, pdesc);
1349 pdesc->lld.mbr_dus = stride;
1350
1351 /*
1352 * Put back the N descriptor in the free
1353 * descriptor list
1354 */
1355 list_add_tail(&desc->desc_node,
1356 &atchan->free_descs_list);
1357 }
1358
1359 /* Update our descriptors */
1360 ppdesc = pdesc;
1361 pdesc = desc;
1362
1363 /* Update our scatter pointers */
1364 ppsg = psg;
1365 psg = sg;
1366
1367 len += sg_dma_len(sg);
1368 }
1369
1370 first->tx_dma_desc.cookie = -EBUSY;
1371 first->tx_dma_desc.flags = flags;
1372 first->xfer_size = len;
1373
1374 return &first->tx_dma_desc;
1375 }
1376
1377 static enum dma_status
1378 at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1379 struct dma_tx_state *txstate)
1380 {
1381 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1382 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1383 struct at_xdmac_desc *desc, *_desc;
1384 struct list_head *descs_list;
1385 enum dma_status ret;
1386 int residue;
1387 u32 cur_nda, mask, value;
1388 u8 dwidth = 0;
1389 unsigned long flags;
1390
1391 ret = dma_cookie_status(chan, cookie, txstate);
1392 if (ret == DMA_COMPLETE)
1393 return ret;
1394
1395 if (!txstate)
1396 return ret;
1397
1398 spin_lock_irqsave(&atchan->lock, flags);
1399
1400 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1401
1402 /*
1403 * If the transfer has not been started yet, don't need to compute the
1404 * residue, it's the transfer length.
1405 */
1406 if (!desc->active_xfer) {
1407 dma_set_residue(txstate, desc->xfer_size);
1408 goto spin_unlock;
1409 }
1410
1411 residue = desc->xfer_size;
1412 /*
1413 * Flush FIFO: only relevant when the transfer is source peripheral
1414 * synchronized.
1415 */
1416 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
1417 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
1418 if ((desc->lld.mbr_cfg & mask) == value) {
1419 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
1420 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1421 cpu_relax();
1422 }
1423
1424 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1425 /*
1426 * Remove size of all microblocks already transferred and the current
1427 * one. Then add the remaining size to transfer of the current
1428 * microblock.
1429 */
1430 descs_list = &desc->descs_list;
1431 list_for_each_entry_safe(desc, _desc, descs_list, desc_node) {
1432 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
1433 residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth;
1434 if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda)
1435 break;
1436 }
1437 residue += at_xdmac_chan_read(atchan, AT_XDMAC_CUBC) << dwidth;
1438
1439 dma_set_residue(txstate, residue);
1440
1441 dev_dbg(chan2dev(chan),
1442 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
1443 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
1444
1445 spin_unlock:
1446 spin_unlock_irqrestore(&atchan->lock, flags);
1447 return ret;
1448 }
1449
1450 /* Call must be protected by lock. */
1451 static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan,
1452 struct at_xdmac_desc *desc)
1453 {
1454 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1455
1456 /*
1457 * Remove the transfer from the transfer list then move the transfer
1458 * descriptors into the free descriptors list.
1459 */
1460 list_del(&desc->xfer_node);
1461 list_splice_init(&desc->descs_list, &atchan->free_descs_list);
1462 }
1463
1464 static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
1465 {
1466 struct at_xdmac_desc *desc;
1467 unsigned long flags;
1468
1469 spin_lock_irqsave(&atchan->lock, flags);
1470
1471 /*
1472 * If channel is enabled, do nothing, advance_work will be triggered
1473 * after the interruption.
1474 */
1475 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) {
1476 desc = list_first_entry(&atchan->xfers_list,
1477 struct at_xdmac_desc,
1478 xfer_node);
1479 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1480 if (!desc->active_xfer)
1481 at_xdmac_start_xfer(atchan, desc);
1482 }
1483
1484 spin_unlock_irqrestore(&atchan->lock, flags);
1485 }
1486
1487 static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
1488 {
1489 struct at_xdmac_desc *desc;
1490 struct dma_async_tx_descriptor *txd;
1491
1492 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1493 txd = &desc->tx_dma_desc;
1494
1495 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1496 txd->callback(txd->callback_param);
1497 }
1498
1499 static void at_xdmac_tasklet(unsigned long data)
1500 {
1501 struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data;
1502 struct at_xdmac_desc *desc;
1503 u32 error_mask;
1504
1505 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n",
1506 __func__, atchan->status);
1507
1508 error_mask = AT_XDMAC_CIS_RBEIS
1509 | AT_XDMAC_CIS_WBEIS
1510 | AT_XDMAC_CIS_ROIS;
1511
1512 if (at_xdmac_chan_is_cyclic(atchan)) {
1513 at_xdmac_handle_cyclic(atchan);
1514 } else if ((atchan->status & AT_XDMAC_CIS_LIS)
1515 || (atchan->status & error_mask)) {
1516 struct dma_async_tx_descriptor *txd;
1517
1518 if (atchan->status & AT_XDMAC_CIS_RBEIS)
1519 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1520 if (atchan->status & AT_XDMAC_CIS_WBEIS)
1521 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1522 if (atchan->status & AT_XDMAC_CIS_ROIS)
1523 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1524
1525 spin_lock_bh(&atchan->lock);
1526 desc = list_first_entry(&atchan->xfers_list,
1527 struct at_xdmac_desc,
1528 xfer_node);
1529 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1530 BUG_ON(!desc->active_xfer);
1531
1532 txd = &desc->tx_dma_desc;
1533
1534 at_xdmac_remove_xfer(atchan, desc);
1535 spin_unlock_bh(&atchan->lock);
1536
1537 if (!at_xdmac_chan_is_cyclic(atchan)) {
1538 dma_cookie_complete(txd);
1539 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1540 txd->callback(txd->callback_param);
1541 }
1542
1543 dma_run_dependencies(txd);
1544
1545 at_xdmac_advance_work(atchan);
1546 }
1547 }
1548
1549 static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1550 {
1551 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1552 struct at_xdmac_chan *atchan;
1553 u32 imr, status, pending;
1554 u32 chan_imr, chan_status;
1555 int i, ret = IRQ_NONE;
1556
1557 do {
1558 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1559 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1560 pending = status & imr;
1561
1562 dev_vdbg(atxdmac->dma.dev,
1563 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1564 __func__, status, imr, pending);
1565
1566 if (!pending)
1567 break;
1568
1569 /* We have to find which channel has generated the interrupt. */
1570 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1571 if (!((1 << i) & pending))
1572 continue;
1573
1574 atchan = &atxdmac->chan[i];
1575 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1576 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1577 atchan->status = chan_status & chan_imr;
1578 dev_vdbg(atxdmac->dma.dev,
1579 "%s: chan%d: imr=0x%x, status=0x%x\n",
1580 __func__, i, chan_imr, chan_status);
1581 dev_vdbg(chan2dev(&atchan->chan),
1582 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1583 __func__,
1584 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1585 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1586 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1587 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1588 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1589 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1590
1591 if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1592 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1593
1594 tasklet_schedule(&atchan->tasklet);
1595 ret = IRQ_HANDLED;
1596 }
1597
1598 } while (pending);
1599
1600 return ret;
1601 }
1602
1603 static void at_xdmac_issue_pending(struct dma_chan *chan)
1604 {
1605 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1606
1607 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1608
1609 if (!at_xdmac_chan_is_cyclic(atchan))
1610 at_xdmac_advance_work(atchan);
1611
1612 return;
1613 }
1614
1615 static int at_xdmac_device_config(struct dma_chan *chan,
1616 struct dma_slave_config *config)
1617 {
1618 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1619 int ret;
1620 unsigned long flags;
1621
1622 dev_dbg(chan2dev(chan), "%s\n", __func__);
1623
1624 spin_lock_irqsave(&atchan->lock, flags);
1625 ret = at_xdmac_set_slave_config(chan, config);
1626 spin_unlock_irqrestore(&atchan->lock, flags);
1627
1628 return ret;
1629 }
1630
1631 static int at_xdmac_device_pause(struct dma_chan *chan)
1632 {
1633 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1634 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1635 unsigned long flags;
1636
1637 dev_dbg(chan2dev(chan), "%s\n", __func__);
1638
1639 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1640 return 0;
1641
1642 spin_lock_irqsave(&atchan->lock, flags);
1643 at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
1644 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1645 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1646 cpu_relax();
1647 spin_unlock_irqrestore(&atchan->lock, flags);
1648
1649 return 0;
1650 }
1651
1652 static int at_xdmac_device_resume(struct dma_chan *chan)
1653 {
1654 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1655 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1656 unsigned long flags;
1657
1658 dev_dbg(chan2dev(chan), "%s\n", __func__);
1659
1660 spin_lock_irqsave(&atchan->lock, flags);
1661 if (!at_xdmac_chan_is_paused(atchan)) {
1662 spin_unlock_irqrestore(&atchan->lock, flags);
1663 return 0;
1664 }
1665
1666 at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
1667 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1668 spin_unlock_irqrestore(&atchan->lock, flags);
1669
1670 return 0;
1671 }
1672
1673 static int at_xdmac_device_terminate_all(struct dma_chan *chan)
1674 {
1675 struct at_xdmac_desc *desc, *_desc;
1676 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1677 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1678 unsigned long flags;
1679
1680 dev_dbg(chan2dev(chan), "%s\n", __func__);
1681
1682 spin_lock_irqsave(&atchan->lock, flags);
1683 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1684 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1685 cpu_relax();
1686
1687 /* Cancel all pending transfers. */
1688 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node)
1689 at_xdmac_remove_xfer(atchan, desc);
1690
1691 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
1692 spin_unlock_irqrestore(&atchan->lock, flags);
1693
1694 return 0;
1695 }
1696
1697 static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1698 {
1699 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1700 struct at_xdmac_desc *desc;
1701 int i;
1702 unsigned long flags;
1703
1704 spin_lock_irqsave(&atchan->lock, flags);
1705
1706 if (at_xdmac_chan_is_enabled(atchan)) {
1707 dev_err(chan2dev(chan),
1708 "can't allocate channel resources (channel enabled)\n");
1709 i = -EIO;
1710 goto spin_unlock;
1711 }
1712
1713 if (!list_empty(&atchan->free_descs_list)) {
1714 dev_err(chan2dev(chan),
1715 "can't allocate channel resources (channel not free from a previous use)\n");
1716 i = -EIO;
1717 goto spin_unlock;
1718 }
1719
1720 for (i = 0; i < init_nr_desc_per_channel; i++) {
1721 desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC);
1722 if (!desc) {
1723 dev_warn(chan2dev(chan),
1724 "only %d descriptors have been allocated\n", i);
1725 break;
1726 }
1727 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1728 }
1729
1730 dma_cookie_init(chan);
1731
1732 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1733
1734 spin_unlock:
1735 spin_unlock_irqrestore(&atchan->lock, flags);
1736 return i;
1737 }
1738
1739 static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1740 {
1741 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1742 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1743 struct at_xdmac_desc *desc, *_desc;
1744
1745 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1746 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1747 list_del(&desc->desc_node);
1748 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1749 }
1750
1751 return;
1752 }
1753
1754 #ifdef CONFIG_PM
1755 static int atmel_xdmac_prepare(struct device *dev)
1756 {
1757 struct platform_device *pdev = to_platform_device(dev);
1758 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1759 struct dma_chan *chan, *_chan;
1760
1761 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1762 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1763
1764 /* Wait for transfer completion, except in cyclic case. */
1765 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1766 return -EAGAIN;
1767 }
1768 return 0;
1769 }
1770 #else
1771 # define atmel_xdmac_prepare NULL
1772 #endif
1773
1774 #ifdef CONFIG_PM_SLEEP
1775 static int atmel_xdmac_suspend(struct device *dev)
1776 {
1777 struct platform_device *pdev = to_platform_device(dev);
1778 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1779 struct dma_chan *chan, *_chan;
1780
1781 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1782 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1783
1784 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
1785 if (at_xdmac_chan_is_cyclic(atchan)) {
1786 if (!at_xdmac_chan_is_paused(atchan))
1787 at_xdmac_device_pause(chan);
1788 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1789 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1790 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1791 }
1792 }
1793 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1794
1795 at_xdmac_off(atxdmac);
1796 clk_disable_unprepare(atxdmac->clk);
1797 return 0;
1798 }
1799
1800 static int atmel_xdmac_resume(struct device *dev)
1801 {
1802 struct platform_device *pdev = to_platform_device(dev);
1803 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1804 struct at_xdmac_chan *atchan;
1805 struct dma_chan *chan, *_chan;
1806 int i;
1807
1808 clk_prepare_enable(atxdmac->clk);
1809
1810 /* Clear pending interrupts. */
1811 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1812 atchan = &atxdmac->chan[i];
1813 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1814 cpu_relax();
1815 }
1816
1817 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
1818 at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs);
1819 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1820 atchan = to_at_xdmac_chan(chan);
1821 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
1822 if (at_xdmac_chan_is_cyclic(atchan)) {
1823 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
1824 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
1825 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
1826 wmb();
1827 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
1828 }
1829 }
1830 return 0;
1831 }
1832 #endif /* CONFIG_PM_SLEEP */
1833
1834 static int at_xdmac_probe(struct platform_device *pdev)
1835 {
1836 struct resource *res;
1837 struct at_xdmac *atxdmac;
1838 int irq, size, nr_channels, i, ret;
1839 void __iomem *base;
1840 u32 reg;
1841
1842 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1843 if (!res)
1844 return -EINVAL;
1845
1846 irq = platform_get_irq(pdev, 0);
1847 if (irq < 0)
1848 return irq;
1849
1850 base = devm_ioremap_resource(&pdev->dev, res);
1851 if (IS_ERR(base))
1852 return PTR_ERR(base);
1853
1854 /*
1855 * Read number of xdmac channels, read helper function can't be used
1856 * since atxdmac is not yet allocated and we need to know the number
1857 * of channels to do the allocation.
1858 */
1859 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
1860 nr_channels = AT_XDMAC_NB_CH(reg);
1861 if (nr_channels > AT_XDMAC_MAX_CHAN) {
1862 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
1863 nr_channels);
1864 return -EINVAL;
1865 }
1866
1867 size = sizeof(*atxdmac);
1868 size += nr_channels * sizeof(struct at_xdmac_chan);
1869 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1870 if (!atxdmac) {
1871 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
1872 return -ENOMEM;
1873 }
1874
1875 atxdmac->regs = base;
1876 atxdmac->irq = irq;
1877
1878 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
1879 if (IS_ERR(atxdmac->clk)) {
1880 dev_err(&pdev->dev, "can't get dma_clk\n");
1881 return PTR_ERR(atxdmac->clk);
1882 }
1883
1884 /* Do not use dev res to prevent races with tasklet */
1885 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
1886 if (ret) {
1887 dev_err(&pdev->dev, "can't request irq\n");
1888 return ret;
1889 }
1890
1891 ret = clk_prepare_enable(atxdmac->clk);
1892 if (ret) {
1893 dev_err(&pdev->dev, "can't prepare or enable clock\n");
1894 goto err_free_irq;
1895 }
1896
1897 atxdmac->at_xdmac_desc_pool =
1898 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1899 sizeof(struct at_xdmac_desc), 4, 0);
1900 if (!atxdmac->at_xdmac_desc_pool) {
1901 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
1902 ret = -ENOMEM;
1903 goto err_clk_disable;
1904 }
1905
1906 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
1907 dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask);
1908 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
1909 dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask);
1910 dma_cap_set(DMA_MEMSET_SG, atxdmac->dma.cap_mask);
1911 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
1912 /*
1913 * Without DMA_PRIVATE the driver is not able to allocate more than
1914 * one channel, second allocation fails in private_candidate.
1915 */
1916 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
1917 atxdmac->dma.dev = &pdev->dev;
1918 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
1919 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
1920 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
1921 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
1922 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
1923 atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved;
1924 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
1925 atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset;
1926 atxdmac->dma.device_prep_dma_memset_sg = at_xdmac_prep_dma_memset_sg;
1927 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
1928 atxdmac->dma.device_config = at_xdmac_device_config;
1929 atxdmac->dma.device_pause = at_xdmac_device_pause;
1930 atxdmac->dma.device_resume = at_xdmac_device_resume;
1931 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
1932 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1933 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
1934 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1935 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1936
1937 /* Disable all chans and interrupts. */
1938 at_xdmac_off(atxdmac);
1939
1940 /* Init channels. */
1941 INIT_LIST_HEAD(&atxdmac->dma.channels);
1942 for (i = 0; i < nr_channels; i++) {
1943 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
1944
1945 atchan->chan.device = &atxdmac->dma;
1946 list_add_tail(&atchan->chan.device_node,
1947 &atxdmac->dma.channels);
1948
1949 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
1950 atchan->mask = 1 << i;
1951
1952 spin_lock_init(&atchan->lock);
1953 INIT_LIST_HEAD(&atchan->xfers_list);
1954 INIT_LIST_HEAD(&atchan->free_descs_list);
1955 tasklet_init(&atchan->tasklet, at_xdmac_tasklet,
1956 (unsigned long)atchan);
1957
1958 /* Clear pending interrupts. */
1959 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1960 cpu_relax();
1961 }
1962 platform_set_drvdata(pdev, atxdmac);
1963
1964 ret = dma_async_device_register(&atxdmac->dma);
1965 if (ret) {
1966 dev_err(&pdev->dev, "fail to register DMA engine device\n");
1967 goto err_clk_disable;
1968 }
1969
1970 ret = of_dma_controller_register(pdev->dev.of_node,
1971 at_xdmac_xlate, atxdmac);
1972 if (ret) {
1973 dev_err(&pdev->dev, "could not register of dma controller\n");
1974 goto err_dma_unregister;
1975 }
1976
1977 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
1978 nr_channels, atxdmac->regs);
1979
1980 return 0;
1981
1982 err_dma_unregister:
1983 dma_async_device_unregister(&atxdmac->dma);
1984 err_clk_disable:
1985 clk_disable_unprepare(atxdmac->clk);
1986 err_free_irq:
1987 free_irq(atxdmac->irq, atxdmac->dma.dev);
1988 return ret;
1989 }
1990
1991 static int at_xdmac_remove(struct platform_device *pdev)
1992 {
1993 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
1994 int i;
1995
1996 at_xdmac_off(atxdmac);
1997 of_dma_controller_free(pdev->dev.of_node);
1998 dma_async_device_unregister(&atxdmac->dma);
1999 clk_disable_unprepare(atxdmac->clk);
2000
2001 synchronize_irq(atxdmac->irq);
2002
2003 free_irq(atxdmac->irq, atxdmac->dma.dev);
2004
2005 for (i = 0; i < atxdmac->dma.chancnt; i++) {
2006 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
2007
2008 tasklet_kill(&atchan->tasklet);
2009 at_xdmac_free_chan_resources(&atchan->chan);
2010 }
2011
2012 return 0;
2013 }
2014
2015 static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
2016 .prepare = atmel_xdmac_prepare,
2017 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
2018 };
2019
2020 static const struct of_device_id atmel_xdmac_dt_ids[] = {
2021 {
2022 .compatible = "atmel,sama5d4-dma",
2023 }, {
2024 /* sentinel */
2025 }
2026 };
2027 MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
2028
2029 static struct platform_driver at_xdmac_driver = {
2030 .probe = at_xdmac_probe,
2031 .remove = at_xdmac_remove,
2032 .driver = {
2033 .name = "at_xdmac",
2034 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
2035 .pm = &atmel_xdmac_dev_pm_ops,
2036 }
2037 };
2038
2039 static int __init at_xdmac_init(void)
2040 {
2041 return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe);
2042 }
2043 subsys_initcall(at_xdmac_init);
2044
2045 MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
2046 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
2047 MODULE_LICENSE("GPL");
Linux with added FPC-III support