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of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / drivers / dma / xgene-dma.c
blob9cb93c5b655d80f411079aff95e02f612b7f3ec0
1 /*
2 * Applied Micro X-Gene SoC DMA engine Driver
3 *
4 * Copyright (c) 2015, Applied Micro Circuits Corporation
5 * Authors: Rameshwar Prasad Sahu <rsahu@apm.com>
6 * Loc Ho <lho@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 * NOTE: PM support is currently not available.
22 */
23
24 #include <linux/acpi.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dmapool.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/irq.h>
33 #include <linux/module.h>
34 #include <linux/of_device.h>
35
36 #include "dmaengine.h"
37
38 /* X-Gene DMA ring csr registers and bit definations */
39 #define XGENE_DMA_RING_CONFIG 0x04
40 #define XGENE_DMA_RING_ENABLE BIT(31)
41 #define XGENE_DMA_RING_ID 0x08
42 #define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
43 #define XGENE_DMA_RING_ID_BUF 0x0C
44 #define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
45 #define XGENE_DMA_RING_THRESLD0_SET1 0x30
46 #define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64
47 #define XGENE_DMA_RING_THRESLD1_SET1 0x34
48 #define XGENE_DMA_RING_THRESLD1_SET1_VAL 0xC8
49 #define XGENE_DMA_RING_HYSTERESIS 0x68
50 #define XGENE_DMA_RING_HYSTERESIS_VAL 0xFFFFFFFF
51 #define XGENE_DMA_RING_STATE 0x6C
52 #define XGENE_DMA_RING_STATE_WR_BASE 0x70
53 #define XGENE_DMA_RING_NE_INT_MODE 0x017C
54 #define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \
55 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
56 #define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \
57 ((m) &= (~BIT(31 - (v))))
58 #define XGENE_DMA_RING_CLKEN 0xC208
59 #define XGENE_DMA_RING_SRST 0xC200
60 #define XGENE_DMA_RING_MEM_RAM_SHUTDOWN 0xD070
61 #define XGENE_DMA_RING_BLK_MEM_RDY 0xD074
62 #define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0xFFFFFFFF
63 #define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num))
64 #define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v))
65 #define XGENE_DMA_RING_CMD_OFFSET 0x2C
66 #define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6)
67 #define XGENE_DMA_RING_COHERENT_SET(m) \
68 (((u32 *)(m))[2] |= BIT(4))
69 #define XGENE_DMA_RING_ADDRL_SET(m, v) \
70 (((u32 *)(m))[2] |= (((v) >> 8) << 5))
71 #define XGENE_DMA_RING_ADDRH_SET(m, v) \
72 (((u32 *)(m))[3] |= ((v) >> 35))
73 #define XGENE_DMA_RING_ACCEPTLERR_SET(m) \
74 (((u32 *)(m))[3] |= BIT(19))
75 #define XGENE_DMA_RING_SIZE_SET(m, v) \
76 (((u32 *)(m))[3] |= ((v) << 23))
77 #define XGENE_DMA_RING_RECOMBBUF_SET(m) \
78 (((u32 *)(m))[3] |= BIT(27))
79 #define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m) \
80 (((u32 *)(m))[3] |= (0x7 << 28))
81 #define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m) \
82 (((u32 *)(m))[4] |= 0x3)
83 #define XGENE_DMA_RING_SELTHRSH_SET(m) \
84 (((u32 *)(m))[4] |= BIT(3))
85 #define XGENE_DMA_RING_TYPE_SET(m, v) \
86 (((u32 *)(m))[4] |= ((v) << 19))
87
88 /* X-Gene DMA device csr registers and bit definitions */
89 #define XGENE_DMA_IPBRR 0x0
90 #define XGENE_DMA_DEV_ID_RD(v) ((v) & 0x00000FFF)
91 #define XGENE_DMA_BUS_ID_RD(v) (((v) >> 12) & 3)
92 #define XGENE_DMA_REV_NO_RD(v) (((v) >> 14) & 3)
93 #define XGENE_DMA_GCR 0x10
94 #define XGENE_DMA_CH_SETUP(v) \
95 ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF)
96 #define XGENE_DMA_ENABLE(v) ((v) |= BIT(31))
97 #define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31))
98 #define XGENE_DMA_RAID6_CONT 0x14
99 #define XGENE_DMA_RAID6_MULTI_CTRL(v) ((v) << 24)
100 #define XGENE_DMA_INT 0x70
101 #define XGENE_DMA_INT_MASK 0x74
102 #define XGENE_DMA_INT_ALL_MASK 0xFFFFFFFF
103 #define XGENE_DMA_INT_ALL_UNMASK 0x0
104 #define XGENE_DMA_INT_MASK_SHIFT 0x14
105 #define XGENE_DMA_RING_INT0_MASK 0x90A0
106 #define XGENE_DMA_RING_INT1_MASK 0x90A8
107 #define XGENE_DMA_RING_INT2_MASK 0x90B0
108 #define XGENE_DMA_RING_INT3_MASK 0x90B8
109 #define XGENE_DMA_RING_INT4_MASK 0x90C0
110 #define XGENE_DMA_CFG_RING_WQ_ASSOC 0x90E0
111 #define XGENE_DMA_ASSOC_RING_MNGR1 0xFFFFFFFF
112 #define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
113 #define XGENE_DMA_BLK_MEM_RDY 0xD074
114 #define XGENE_DMA_BLK_MEM_RDY_VAL 0xFFFFFFFF
115 #define XGENE_DMA_RING_CMD_SM_OFFSET 0x8000
116
117 /* X-Gene SoC EFUSE csr register and bit defination */
118 #define XGENE_SOC_JTAG1_SHADOW 0x18
119 #define XGENE_DMA_PQ_DISABLE_MASK BIT(13)
120
121 /* X-Gene DMA Descriptor format */
122 #define XGENE_DMA_DESC_NV_BIT BIT_ULL(50)
123 #define XGENE_DMA_DESC_IN_BIT BIT_ULL(55)
124 #define XGENE_DMA_DESC_C_BIT BIT_ULL(63)
125 #define XGENE_DMA_DESC_DR_BIT BIT_ULL(61)
126 #define XGENE_DMA_DESC_ELERR_POS 46
127 #define XGENE_DMA_DESC_RTYPE_POS 56
128 #define XGENE_DMA_DESC_LERR_POS 60
129 #define XGENE_DMA_DESC_BUFLEN_POS 48
130 #define XGENE_DMA_DESC_HOENQ_NUM_POS 48
131 #define XGENE_DMA_DESC_ELERR_RD(m) \
132 (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
133 #define XGENE_DMA_DESC_LERR_RD(m) \
134 (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7)
135 #define XGENE_DMA_DESC_STATUS(elerr, lerr) \
136 (((elerr) << 4) | (lerr))
137
138 /* X-Gene DMA descriptor empty s/w signature */
139 #define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
140
141 /* X-Gene DMA configurable parameters defines */
142 #define XGENE_DMA_RING_NUM 512
143 #define XGENE_DMA_BUFNUM 0x0
144 #define XGENE_DMA_CPU_BUFNUM 0x18
145 #define XGENE_DMA_RING_OWNER_DMA 0x03
146 #define XGENE_DMA_RING_OWNER_CPU 0x0F
147 #define XGENE_DMA_RING_TYPE_REGULAR 0x01
148 #define XGENE_DMA_RING_WQ_DESC_SIZE 32 /* 32 Bytes */
149 #define XGENE_DMA_RING_NUM_CONFIG 5
150 #define XGENE_DMA_MAX_CHANNEL 4
151 #define XGENE_DMA_XOR_CHANNEL 0
152 #define XGENE_DMA_PQ_CHANNEL 1
153 #define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */
154 #define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */
155 #define XGENE_DMA_MAX_XOR_SRC 5
156 #define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
157 #define XGENE_DMA_INVALID_LEN_CODE 0x7800000000000000ULL
158
159 /* X-Gene DMA descriptor error codes */
160 #define ERR_DESC_AXI 0x01
161 #define ERR_BAD_DESC 0x02
162 #define ERR_READ_DATA_AXI 0x03
163 #define ERR_WRITE_DATA_AXI 0x04
164 #define ERR_FBP_TIMEOUT 0x05
165 #define ERR_ECC 0x06
166 #define ERR_DIFF_SIZE 0x08
167 #define ERR_SCT_GAT_LEN 0x09
168 #define ERR_CRC_ERR 0x11
169 #define ERR_CHKSUM 0x12
170 #define ERR_DIF 0x13
171
172 /* X-Gene DMA error interrupt codes */
173 #define ERR_DIF_SIZE_INT 0x0
174 #define ERR_GS_ERR_INT 0x1
175 #define ERR_FPB_TIMEO_INT 0x2
176 #define ERR_WFIFO_OVF_INT 0x3
177 #define ERR_RFIFO_OVF_INT 0x4
178 #define ERR_WR_TIMEO_INT 0x5
179 #define ERR_RD_TIMEO_INT 0x6
180 #define ERR_WR_ERR_INT 0x7
181 #define ERR_RD_ERR_INT 0x8
182 #define ERR_BAD_DESC_INT 0x9
183 #define ERR_DESC_DST_INT 0xA
184 #define ERR_DESC_SRC_INT 0xB
185
186 /* X-Gene DMA flyby operation code */
187 #define FLYBY_2SRC_XOR 0x80
188 #define FLYBY_3SRC_XOR 0x90
189 #define FLYBY_4SRC_XOR 0xA0
190 #define FLYBY_5SRC_XOR 0xB0
191
192 /* X-Gene DMA SW descriptor flags */
193 #define XGENE_DMA_FLAG_64B_DESC BIT(0)
194
195 /* Define to dump X-Gene DMA descriptor */
196 #define XGENE_DMA_DESC_DUMP(desc, m) \
197 print_hex_dump(KERN_ERR, (m), \
198 DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0)
199
200 #define to_dma_desc_sw(tx) \
201 container_of(tx, struct xgene_dma_desc_sw, tx)
202 #define to_dma_chan(dchan) \
203 container_of(dchan, struct xgene_dma_chan, dma_chan)
204
205 #define chan_dbg(chan, fmt, arg...) \
206 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
207 #define chan_err(chan, fmt, arg...) \
208 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
209
210 struct xgene_dma_desc_hw {
211 __le64 m0;
212 __le64 m1;
213 __le64 m2;
214 __le64 m3;
215 };
216
217 enum xgene_dma_ring_cfgsize {
218 XGENE_DMA_RING_CFG_SIZE_512B,
219 XGENE_DMA_RING_CFG_SIZE_2KB,
220 XGENE_DMA_RING_CFG_SIZE_16KB,
221 XGENE_DMA_RING_CFG_SIZE_64KB,
222 XGENE_DMA_RING_CFG_SIZE_512KB,
223 XGENE_DMA_RING_CFG_SIZE_INVALID
224 };
225
226 struct xgene_dma_ring {
227 struct xgene_dma *pdma;
228 u8 buf_num;
229 u16 id;
230 u16 num;
231 u16 head;
232 u16 owner;
233 u16 slots;
234 u16 dst_ring_num;
235 u32 size;
236 void __iomem *cmd;
237 void __iomem *cmd_base;
238 dma_addr_t desc_paddr;
239 u32 state[XGENE_DMA_RING_NUM_CONFIG];
240 enum xgene_dma_ring_cfgsize cfgsize;
241 union {
242 void *desc_vaddr;
243 struct xgene_dma_desc_hw *desc_hw;
244 };
245 };
246
247 struct xgene_dma_desc_sw {
248 struct xgene_dma_desc_hw desc1;
249 struct xgene_dma_desc_hw desc2;
250 u32 flags;
251 struct list_head node;
252 struct list_head tx_list;
253 struct dma_async_tx_descriptor tx;
254 };
255
256 /**
257 * struct xgene_dma_chan - internal representation of an X-Gene DMA channel
258 * @dma_chan: dmaengine channel object member
259 * @pdma: X-Gene DMA device structure reference
260 * @dev: struct device reference for dma mapping api
261 * @id: raw id of this channel
262 * @rx_irq: channel IRQ
263 * @name: name of X-Gene DMA channel
264 * @lock: serializes enqueue/dequeue operations to the descriptor pool
265 * @pending: number of transaction request pushed to DMA controller for
266 * execution, but still waiting for completion,
267 * @max_outstanding: max number of outstanding request we can push to channel
268 * @ld_pending: descriptors which are queued to run, but have not yet been
269 * submitted to the hardware for execution
270 * @ld_running: descriptors which are currently being executing by the hardware
271 * @ld_completed: descriptors which have finished execution by the hardware.
272 * These descriptors have already had their cleanup actions run. They
273 * are waiting for the ACK bit to be set by the async tx API.
274 * @desc_pool: descriptor pool for DMA operations
275 * @tasklet: bottom half where all completed descriptors cleans
276 * @tx_ring: transmit ring descriptor that we use to prepare actual
277 * descriptors for further executions
278 * @rx_ring: receive ring descriptor that we use to get completed DMA
279 * descriptors during cleanup time
280 */
281 struct xgene_dma_chan {
282 struct dma_chan dma_chan;
283 struct xgene_dma *pdma;
284 struct device *dev;
285 int id;
286 int rx_irq;
287 char name[10];
288 spinlock_t lock;
289 int pending;
290 int max_outstanding;
291 struct list_head ld_pending;
292 struct list_head ld_running;
293 struct list_head ld_completed;
294 struct dma_pool *desc_pool;
295 struct tasklet_struct tasklet;
296 struct xgene_dma_ring tx_ring;
297 struct xgene_dma_ring rx_ring;
298 };
299
300 /**
301 * struct xgene_dma - internal representation of an X-Gene DMA device
302 * @err_irq: DMA error irq number
303 * @ring_num: start id number for DMA ring
304 * @csr_dma: base for DMA register access
305 * @csr_ring: base for DMA ring register access
306 * @csr_ring_cmd: base for DMA ring command register access
307 * @csr_efuse: base for efuse register access
308 * @dma_dev: embedded struct dma_device
309 * @chan: reference to X-Gene DMA channels
310 */
311 struct xgene_dma {
312 struct device *dev;
313 struct clk *clk;
314 int err_irq;
315 int ring_num;
316 void __iomem *csr_dma;
317 void __iomem *csr_ring;
318 void __iomem *csr_ring_cmd;
319 void __iomem *csr_efuse;
320 struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL];
321 struct xgene_dma_chan chan[XGENE_DMA_MAX_CHANNEL];
322 };
323
324 static const char * const xgene_dma_desc_err[] = {
325 [ERR_DESC_AXI] = "AXI error when reading src/dst link list",
326 [ERR_BAD_DESC] = "ERR or El_ERR fields not set to zero in desc",
327 [ERR_READ_DATA_AXI] = "AXI error when reading data",
328 [ERR_WRITE_DATA_AXI] = "AXI error when writing data",
329 [ERR_FBP_TIMEOUT] = "Timeout on bufpool fetch",
330 [ERR_ECC] = "ECC double bit error",
331 [ERR_DIFF_SIZE] = "Bufpool too small to hold all the DIF result",
332 [ERR_SCT_GAT_LEN] = "Gather and scatter data length not same",
333 [ERR_CRC_ERR] = "CRC error",
334 [ERR_CHKSUM] = "Checksum error",
335 [ERR_DIF] = "DIF error",
336 };
337
338 static const char * const xgene_dma_err[] = {
339 [ERR_DIF_SIZE_INT] = "DIF size error",
340 [ERR_GS_ERR_INT] = "Gather scatter not same size error",
341 [ERR_FPB_TIMEO_INT] = "Free pool time out error",
342 [ERR_WFIFO_OVF_INT] = "Write FIFO over flow error",
343 [ERR_RFIFO_OVF_INT] = "Read FIFO over flow error",
344 [ERR_WR_TIMEO_INT] = "Write time out error",
345 [ERR_RD_TIMEO_INT] = "Read time out error",
346 [ERR_WR_ERR_INT] = "HBF bus write error",
347 [ERR_RD_ERR_INT] = "HBF bus read error",
348 [ERR_BAD_DESC_INT] = "Ring descriptor HE0 not set error",
349 [ERR_DESC_DST_INT] = "HFB reading dst link address error",
350 [ERR_DESC_SRC_INT] = "HFB reading src link address error",
351 };
352
353 static bool is_pq_enabled(struct xgene_dma *pdma)
354 {
355 u32 val;
356
357 val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW);
358 return !(val & XGENE_DMA_PQ_DISABLE_MASK);
359 }
360
361 static u64 xgene_dma_encode_len(size_t len)
362 {
363 return (len < XGENE_DMA_MAX_BYTE_CNT) ?
364 ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) :
365 XGENE_DMA_16K_BUFFER_LEN_CODE;
366 }
367
368 static u8 xgene_dma_encode_xor_flyby(u32 src_cnt)
369 {
370 static u8 flyby_type[] = {
371 FLYBY_2SRC_XOR, /* Dummy */
372 FLYBY_2SRC_XOR, /* Dummy */
373 FLYBY_2SRC_XOR,
374 FLYBY_3SRC_XOR,
375 FLYBY_4SRC_XOR,
376 FLYBY_5SRC_XOR
377 };
378
379 return flyby_type[src_cnt];
380 }
381
382 static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
383 dma_addr_t *paddr)
384 {
385 size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ?
386 *len : XGENE_DMA_MAX_BYTE_CNT;
387
388 *ext8 |= cpu_to_le64(*paddr);
389 *ext8 |= cpu_to_le64(xgene_dma_encode_len(nbytes));
390 *len -= nbytes;
391 *paddr += nbytes;
392 }
393
394 static void xgene_dma_invalidate_buffer(__le64 *ext8)
395 {
396 *ext8 |= cpu_to_le64(XGENE_DMA_INVALID_LEN_CODE);
397 }
398
399 static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc, int idx)
400 {
401 switch (idx) {
402 case 0:
403 return &desc->m1;
404 case 1:
405 return &desc->m0;
406 case 2:
407 return &desc->m3;
408 case 3:
409 return &desc->m2;
410 default:
411 pr_err("Invalid dma descriptor index\n");
412 }
413
414 return NULL;
415 }
416
417 static void xgene_dma_init_desc(struct xgene_dma_desc_hw *desc,
418 u16 dst_ring_num)
419 {
420 desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT);
421 desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA <<
422 XGENE_DMA_DESC_RTYPE_POS);
423 desc->m1 |= cpu_to_le64(XGENE_DMA_DESC_C_BIT);
424 desc->m3 |= cpu_to_le64((u64)dst_ring_num <<
425 XGENE_DMA_DESC_HOENQ_NUM_POS);
426 }
427
428 static void xgene_dma_prep_cpy_desc(struct xgene_dma_chan *chan,
429 struct xgene_dma_desc_sw *desc_sw,
430 dma_addr_t dst, dma_addr_t src,
431 size_t len)
432 {
433 struct xgene_dma_desc_hw *desc1, *desc2;
434 int i;
435
436 /* Get 1st descriptor */
437 desc1 = &desc_sw->desc1;
438 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
439
440 /* Set destination address */
441 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
442 desc1->m3 |= cpu_to_le64(dst);
443
444 /* Set 1st source address */
445 xgene_dma_set_src_buffer(&desc1->m1, &len, &src);
446
447 if (!len)
448 return;
449
450 /*
451 * We need to split this source buffer,
452 * and need to use 2nd descriptor
453 */
454 desc2 = &desc_sw->desc2;
455 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
456
457 /* Set 2nd to 5th source address */
458 for (i = 0; i < 4 && len; i++)
459 xgene_dma_set_src_buffer(xgene_dma_lookup_ext8(desc2, i),
460 &len, &src);
461
462 /* Invalidate unused source address field */
463 for (; i < 4; i++)
464 xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i));
465
466 /* Updated flag that we have prepared 64B descriptor */
467 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
468 }
469
470 static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan,
471 struct xgene_dma_desc_sw *desc_sw,
472 dma_addr_t *dst, dma_addr_t *src,
473 u32 src_cnt, size_t *nbytes,
474 const u8 *scf)
475 {
476 struct xgene_dma_desc_hw *desc1, *desc2;
477 size_t len = *nbytes;
478 int i;
479
480 desc1 = &desc_sw->desc1;
481 desc2 = &desc_sw->desc2;
482
483 /* Initialize DMA descriptor */
484 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
485
486 /* Set destination address */
487 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
488 desc1->m3 |= cpu_to_le64(*dst);
489
490 /* We have multiple source addresses, so need to set NV bit*/
491 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
492
493 /* Set flyby opcode */
494 desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt));
495
496 /* Set 1st to 5th source addresses */
497 for (i = 0; i < src_cnt; i++) {
498 len = *nbytes;
499 xgene_dma_set_src_buffer((i == 0) ? &desc1->m1 :
500 xgene_dma_lookup_ext8(desc2, i - 1),
501 &len, &src[i]);
502 desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8)));
503 }
504
505 /* Update meta data */
506 *nbytes = len;
507 *dst += XGENE_DMA_MAX_BYTE_CNT;
508
509 /* We need always 64B descriptor to perform xor or pq operations */
510 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
511 }
512
513 static dma_cookie_t xgene_dma_tx_submit(struct dma_async_tx_descriptor *tx)
514 {
515 struct xgene_dma_desc_sw *desc;
516 struct xgene_dma_chan *chan;
517 dma_cookie_t cookie;
518
519 if (unlikely(!tx))
520 return -EINVAL;
521
522 chan = to_dma_chan(tx->chan);
523 desc = to_dma_desc_sw(tx);
524
525 spin_lock_bh(&chan->lock);
526
527 cookie = dma_cookie_assign(tx);
528
529 /* Add this transaction list onto the tail of the pending queue */
530 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
531
532 spin_unlock_bh(&chan->lock);
533
534 return cookie;
535 }
536
537 static void xgene_dma_clean_descriptor(struct xgene_dma_chan *chan,
538 struct xgene_dma_desc_sw *desc)
539 {
540 list_del(&desc->node);
541 chan_dbg(chan, "LD %p free\n", desc);
542 dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
543 }
544
545 static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor(
546 struct xgene_dma_chan *chan)
547 {
548 struct xgene_dma_desc_sw *desc;
549 dma_addr_t phys;
550
551 desc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
552 if (!desc) {
553 chan_err(chan, "Failed to allocate LDs\n");
554 return NULL;
555 }
556
557 INIT_LIST_HEAD(&desc->tx_list);
558 desc->tx.phys = phys;
559 desc->tx.tx_submit = xgene_dma_tx_submit;
560 dma_async_tx_descriptor_init(&desc->tx, &chan->dma_chan);
561
562 chan_dbg(chan, "LD %p allocated\n", desc);
563
564 return desc;
565 }
566
567 /**
568 * xgene_dma_clean_completed_descriptor - free all descriptors which
569 * has been completed and acked
570 * @chan: X-Gene DMA channel
571 *
572 * This function is used on all completed and acked descriptors.
573 */
574 static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan *chan)
575 {
576 struct xgene_dma_desc_sw *desc, *_desc;
577
578 /* Run the callback for each descriptor, in order */
579 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) {
580 if (async_tx_test_ack(&desc->tx))
581 xgene_dma_clean_descriptor(chan, desc);
582 }
583 }
584
585 /**
586 * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor
587 * @chan: X-Gene DMA channel
588 * @desc: descriptor to cleanup and free
589 *
590 * This function is used on a descriptor which has been executed by the DMA
591 * controller. It will run any callbacks, submit any dependencies.
592 */
593 static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan *chan,
594 struct xgene_dma_desc_sw *desc)
595 {
596 struct dma_async_tx_descriptor *tx = &desc->tx;
597
598 /*
599 * If this is not the last transaction in the group,
600 * then no need to complete cookie and run any callback as
601 * this is not the tx_descriptor which had been sent to caller
602 * of this DMA request
603 */
604
605 if (tx->cookie == 0)
606 return;
607
608 dma_cookie_complete(tx);
609
610 /* Run the link descriptor callback function */
611 if (tx->callback)
612 tx->callback(tx->callback_param);
613
614 dma_descriptor_unmap(tx);
615
616 /* Run any dependencies */
617 dma_run_dependencies(tx);
618 }
619
620 /**
621 * xgene_dma_clean_running_descriptor - move the completed descriptor from
622 * ld_running to ld_completed
623 * @chan: X-Gene DMA channel
624 * @desc: the descriptor which is completed
625 *
626 * Free the descriptor directly if acked by async_tx api,
627 * else move it to queue ld_completed.
628 */
629 static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan *chan,
630 struct xgene_dma_desc_sw *desc)
631 {
632 /* Remove from the list of running transactions */
633 list_del(&desc->node);
634
635 /*
636 * the client is allowed to attach dependent operations
637 * until 'ack' is set
638 */
639 if (!async_tx_test_ack(&desc->tx)) {
640 /*
641 * Move this descriptor to the list of descriptors which is
642 * completed, but still awaiting the 'ack' bit to be set.
643 */
644 list_add_tail(&desc->node, &chan->ld_completed);
645 return;
646 }
647
648 chan_dbg(chan, "LD %p free\n", desc);
649 dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
650 }
651
652 static void xgene_chan_xfer_request(struct xgene_dma_chan *chan,
653 struct xgene_dma_desc_sw *desc_sw)
654 {
655 struct xgene_dma_ring *ring = &chan->tx_ring;
656 struct xgene_dma_desc_hw *desc_hw;
657
658 /* Get hw descriptor from DMA tx ring */
659 desc_hw = &ring->desc_hw[ring->head];
660
661 /*
662 * Increment the head count to point next
663 * descriptor for next time
664 */
665 if (++ring->head == ring->slots)
666 ring->head = 0;
667
668 /* Copy prepared sw descriptor data to hw descriptor */
669 memcpy(desc_hw, &desc_sw->desc1, sizeof(*desc_hw));
670
671 /*
672 * Check if we have prepared 64B descriptor,
673 * in this case we need one more hw descriptor
674 */
675 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) {
676 desc_hw = &ring->desc_hw[ring->head];
677
678 if (++ring->head == ring->slots)
679 ring->head = 0;
680
681 memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw));
682 }
683
684 /* Increment the pending transaction count */
685 chan->pending += ((desc_sw->flags &
686 XGENE_DMA_FLAG_64B_DESC) ? 2 : 1);
687
688 /* Notify the hw that we have descriptor ready for execution */
689 iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ?
690 2 : 1, ring->cmd);
691 }
692
693 /**
694 * xgene_chan_xfer_ld_pending - push any pending transactions to hw
695 * @chan : X-Gene DMA channel
696 *
697 * LOCKING: must hold chan->lock
698 */
699 static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan)
700 {
701 struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
702
703 /*
704 * If the list of pending descriptors is empty, then we
705 * don't need to do any work at all
706 */
707 if (list_empty(&chan->ld_pending)) {
708 chan_dbg(chan, "No pending LDs\n");
709 return;
710 }
711
712 /*
713 * Move elements from the queue of pending transactions onto the list
714 * of running transactions and push it to hw for further executions
715 */
716 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_pending, node) {
717 /*
718 * Check if have pushed max number of transactions to hw
719 * as capable, so let's stop here and will push remaining
720 * elements from pening ld queue after completing some
721 * descriptors that we have already pushed
722 */
723 if (chan->pending >= chan->max_outstanding)
724 return;
725
726 xgene_chan_xfer_request(chan, desc_sw);
727
728 /*
729 * Delete this element from ld pending queue and append it to
730 * ld running queue
731 */
732 list_move_tail(&desc_sw->node, &chan->ld_running);
733 }
734 }
735
736 /**
737 * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed
738 * and move them to ld_completed to free until flag 'ack' is set
739 * @chan: X-Gene DMA channel
740 *
741 * This function is used on descriptors which have been executed by the DMA
742 * controller. It will run any callbacks, submit any dependencies, then
743 * free these descriptors if flag 'ack' is set.
744 */
745 static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan)
746 {
747 struct xgene_dma_ring *ring = &chan->rx_ring;
748 struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
749 struct xgene_dma_desc_hw *desc_hw;
750 struct list_head ld_completed;
751 u8 status;
752
753 INIT_LIST_HEAD(&ld_completed);
754
755 spin_lock_bh(&chan->lock);
756
757 /* Clean already completed and acked descriptors */
758 xgene_dma_clean_completed_descriptor(chan);
759
760 /* Move all completed descriptors to ld completed queue, in order */
761 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) {
762 /* Get subsequent hw descriptor from DMA rx ring */
763 desc_hw = &ring->desc_hw[ring->head];
764
765 /* Check if this descriptor has been completed */
766 if (unlikely(le64_to_cpu(desc_hw->m0) ==
767 XGENE_DMA_DESC_EMPTY_SIGNATURE))
768 break;
769
770 if (++ring->head == ring->slots)
771 ring->head = 0;
772
773 /* Check if we have any error with DMA transactions */
774 status = XGENE_DMA_DESC_STATUS(
775 XGENE_DMA_DESC_ELERR_RD(le64_to_cpu(
776 desc_hw->m0)),
777 XGENE_DMA_DESC_LERR_RD(le64_to_cpu(
778 desc_hw->m0)));
779 if (status) {
780 /* Print the DMA error type */
781 chan_err(chan, "%s\n", xgene_dma_desc_err[status]);
782
783 /*
784 * We have DMA transactions error here. Dump DMA Tx
785 * and Rx descriptors for this request */
786 XGENE_DMA_DESC_DUMP(&desc_sw->desc1,
787 "X-Gene DMA TX DESC1: ");
788
789 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC)
790 XGENE_DMA_DESC_DUMP(&desc_sw->desc2,
791 "X-Gene DMA TX DESC2: ");
792
793 XGENE_DMA_DESC_DUMP(desc_hw,
794 "X-Gene DMA RX ERR DESC: ");
795 }
796
797 /* Notify the hw about this completed descriptor */
798 iowrite32(-1, ring->cmd);
799
800 /* Mark this hw descriptor as processed */
801 desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
802
803 /*
804 * Decrement the pending transaction count
805 * as we have processed one
806 */
807 chan->pending -= ((desc_sw->flags &
808 XGENE_DMA_FLAG_64B_DESC) ? 2 : 1);
809
810 /*
811 * Delete this node from ld running queue and append it to
812 * ld completed queue for further processing
813 */
814 list_move_tail(&desc_sw->node, &ld_completed);
815 }
816
817 /*
818 * Start any pending transactions automatically
819 * In the ideal case, we keep the DMA controller busy while we go
820 * ahead and free the descriptors below.
821 */
822 xgene_chan_xfer_ld_pending(chan);
823
824 spin_unlock_bh(&chan->lock);
825
826 /* Run the callback for each descriptor, in order */
827 list_for_each_entry_safe(desc_sw, _desc_sw, &ld_completed, node) {
828 xgene_dma_run_tx_complete_actions(chan, desc_sw);
829 xgene_dma_clean_running_descriptor(chan, desc_sw);
830 }
831 }
832
833 static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan)
834 {
835 struct xgene_dma_chan *chan = to_dma_chan(dchan);
836
837 /* Has this channel already been allocated? */
838 if (chan->desc_pool)
839 return 1;
840
841 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
842 sizeof(struct xgene_dma_desc_sw),
843 0, 0);
844 if (!chan->desc_pool) {
845 chan_err(chan, "Failed to allocate descriptor pool\n");
846 return -ENOMEM;
847 }
848
849 chan_dbg(chan, "Allocate descripto pool\n");
850
851 return 1;
852 }
853
854 /**
855 * xgene_dma_free_desc_list - Free all descriptors in a queue
856 * @chan: X-Gene DMA channel
857 * @list: the list to free
858 *
859 * LOCKING: must hold chan->lock
860 */
861 static void xgene_dma_free_desc_list(struct xgene_dma_chan *chan,
862 struct list_head *list)
863 {
864 struct xgene_dma_desc_sw *desc, *_desc;
865
866 list_for_each_entry_safe(desc, _desc, list, node)
867 xgene_dma_clean_descriptor(chan, desc);
868 }
869
870 static void xgene_dma_free_chan_resources(struct dma_chan *dchan)
871 {
872 struct xgene_dma_chan *chan = to_dma_chan(dchan);
873
874 chan_dbg(chan, "Free all resources\n");
875
876 if (!chan->desc_pool)
877 return;
878
879 /* Process all running descriptor */
880 xgene_dma_cleanup_descriptors(chan);
881
882 spin_lock_bh(&chan->lock);
883
884 /* Clean all link descriptor queues */
885 xgene_dma_free_desc_list(chan, &chan->ld_pending);
886 xgene_dma_free_desc_list(chan, &chan->ld_running);
887 xgene_dma_free_desc_list(chan, &chan->ld_completed);
888
889 spin_unlock_bh(&chan->lock);
890
891 /* Delete this channel DMA pool */
892 dma_pool_destroy(chan->desc_pool);
893 chan->desc_pool = NULL;
894 }
895
896 static struct dma_async_tx_descriptor *xgene_dma_prep_sg(
897 struct dma_chan *dchan, struct scatterlist *dst_sg,
898 u32 dst_nents, struct scatterlist *src_sg,
899 u32 src_nents, unsigned long flags)
900 {
901 struct xgene_dma_desc_sw *first = NULL, *new = NULL;
902 struct xgene_dma_chan *chan;
903 size_t dst_avail, src_avail;
904 dma_addr_t dst, src;
905 size_t len;
906
907 if (unlikely(!dchan))
908 return NULL;
909
910 if (unlikely(!dst_nents || !src_nents))
911 return NULL;
912
913 if (unlikely(!dst_sg || !src_sg))
914 return NULL;
915
916 chan = to_dma_chan(dchan);
917
918 /* Get prepared for the loop */
919 dst_avail = sg_dma_len(dst_sg);
920 src_avail = sg_dma_len(src_sg);
921 dst_nents--;
922 src_nents--;
923
924 /* Run until we are out of scatterlist entries */
925 while (true) {
926 /* Create the largest transaction possible */
927 len = min_t(size_t, src_avail, dst_avail);
928 len = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT);
929 if (len == 0)
930 goto fetch;
931
932 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
933 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
934
935 /* Allocate the link descriptor from DMA pool */
936 new = xgene_dma_alloc_descriptor(chan);
937 if (!new)
938 goto fail;
939
940 /* Prepare DMA descriptor */
941 xgene_dma_prep_cpy_desc(chan, new, dst, src, len);
942
943 if (!first)
944 first = new;
945
946 new->tx.cookie = 0;
947 async_tx_ack(&new->tx);
948
949 /* update metadata */
950 dst_avail -= len;
951 src_avail -= len;
952
953 /* Insert the link descriptor to the LD ring */
954 list_add_tail(&new->node, &first->tx_list);
955
956 fetch:
957 /* fetch the next dst scatterlist entry */
958 if (dst_avail == 0) {
959 /* no more entries: we're done */
960 if (dst_nents == 0)
961 break;
962
963 /* fetch the next entry: if there are no more: done */
964 dst_sg = sg_next(dst_sg);
965 if (!dst_sg)
966 break;
967
968 dst_nents--;
969 dst_avail = sg_dma_len(dst_sg);
970 }
971
972 /* fetch the next src scatterlist entry */
973 if (src_avail == 0) {
974 /* no more entries: we're done */
975 if (src_nents == 0)
976 break;
977
978 /* fetch the next entry: if there are no more: done */
979 src_sg = sg_next(src_sg);
980 if (!src_sg)
981 break;
982
983 src_nents--;
984 src_avail = sg_dma_len(src_sg);
985 }
986 }
987
988 if (!new)
989 return NULL;
990
991 new->tx.flags = flags; /* client is in control of this ack */
992 new->tx.cookie = -EBUSY;
993 list_splice(&first->tx_list, &new->tx_list);
994
995 return &new->tx;
996 fail:
997 if (!first)
998 return NULL;
999
1000 xgene_dma_free_desc_list(chan, &first->tx_list);
1001 return NULL;
1002 }
1003
1004 static struct dma_async_tx_descriptor *xgene_dma_prep_xor(
1005 struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src,
1006 u32 src_cnt, size_t len, unsigned long flags)
1007 {
1008 struct xgene_dma_desc_sw *first = NULL, *new;
1009 struct xgene_dma_chan *chan;
1010 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {
1011 0x01, 0x01, 0x01, 0x01, 0x01};
1012
1013 if (unlikely(!dchan || !len))
1014 return NULL;
1015
1016 chan = to_dma_chan(dchan);
1017
1018 do {
1019 /* Allocate the link descriptor from DMA pool */
1020 new = xgene_dma_alloc_descriptor(chan);
1021 if (!new)
1022 goto fail;
1023
1024 /* Prepare xor DMA descriptor */
1025 xgene_dma_prep_xor_desc(chan, new, &dst, src,
1026 src_cnt, &len, multi);
1027
1028 if (!first)
1029 first = new;
1030
1031 new->tx.cookie = 0;
1032 async_tx_ack(&new->tx);
1033
1034 /* Insert the link descriptor to the LD ring */
1035 list_add_tail(&new->node, &first->tx_list);
1036 } while (len);
1037
1038 new->tx.flags = flags; /* client is in control of this ack */
1039 new->tx.cookie = -EBUSY;
1040 list_splice(&first->tx_list, &new->tx_list);
1041
1042 return &new->tx;
1043
1044 fail:
1045 if (!first)
1046 return NULL;
1047
1048 xgene_dma_free_desc_list(chan, &first->tx_list);
1049 return NULL;
1050 }
1051
1052 static struct dma_async_tx_descriptor *xgene_dma_prep_pq(
1053 struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src,
1054 u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
1055 {
1056 struct xgene_dma_desc_sw *first = NULL, *new;
1057 struct xgene_dma_chan *chan;
1058 size_t _len = len;
1059 dma_addr_t _src[XGENE_DMA_MAX_XOR_SRC];
1060 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {0x01, 0x01, 0x01, 0x01, 0x01};
1061
1062 if (unlikely(!dchan || !len))
1063 return NULL;
1064
1065 chan = to_dma_chan(dchan);
1066
1067 /*
1068 * Save source addresses on local variable, may be we have to
1069 * prepare two descriptor to generate P and Q if both enabled
1070 * in the flags by client
1071 */
1072 memcpy(_src, src, sizeof(*src) * src_cnt);
1073
1074 if (flags & DMA_PREP_PQ_DISABLE_P)
1075 len = 0;
1076
1077 if (flags & DMA_PREP_PQ_DISABLE_Q)
1078 _len = 0;
1079
1080 do {
1081 /* Allocate the link descriptor from DMA pool */
1082 new = xgene_dma_alloc_descriptor(chan);
1083 if (!new)
1084 goto fail;
1085
1086 if (!first)
1087 first = new;
1088
1089 new->tx.cookie = 0;
1090 async_tx_ack(&new->tx);
1091
1092 /* Insert the link descriptor to the LD ring */
1093 list_add_tail(&new->node, &first->tx_list);
1094
1095 /*
1096 * Prepare DMA descriptor to generate P,
1097 * if DMA_PREP_PQ_DISABLE_P flag is not set
1098 */
1099 if (len) {
1100 xgene_dma_prep_xor_desc(chan, new, &dst[0], src,
1101 src_cnt, &len, multi);
1102 continue;
1103 }
1104
1105 /*
1106 * Prepare DMA descriptor to generate Q,
1107 * if DMA_PREP_PQ_DISABLE_Q flag is not set
1108 */
1109 if (_len) {
1110 xgene_dma_prep_xor_desc(chan, new, &dst[1], _src,
1111 src_cnt, &_len, scf);
1112 }
1113 } while (len || _len);
1114
1115 new->tx.flags = flags; /* client is in control of this ack */
1116 new->tx.cookie = -EBUSY;
1117 list_splice(&first->tx_list, &new->tx_list);
1118
1119 return &new->tx;
1120
1121 fail:
1122 if (!first)
1123 return NULL;
1124
1125 xgene_dma_free_desc_list(chan, &first->tx_list);
1126 return NULL;
1127 }
1128
1129 static void xgene_dma_issue_pending(struct dma_chan *dchan)
1130 {
1131 struct xgene_dma_chan *chan = to_dma_chan(dchan);
1132
1133 spin_lock_bh(&chan->lock);
1134 xgene_chan_xfer_ld_pending(chan);
1135 spin_unlock_bh(&chan->lock);
1136 }
1137
1138 static enum dma_status xgene_dma_tx_status(struct dma_chan *dchan,
1139 dma_cookie_t cookie,
1140 struct dma_tx_state *txstate)
1141 {
1142 return dma_cookie_status(dchan, cookie, txstate);
1143 }
1144
1145 static void xgene_dma_tasklet_cb(unsigned long data)
1146 {
1147 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)data;
1148
1149 /* Run all cleanup for descriptors which have been completed */
1150 xgene_dma_cleanup_descriptors(chan);
1151
1152 /* Re-enable DMA channel IRQ */
1153 enable_irq(chan->rx_irq);
1154 }
1155
1156 static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id)
1157 {
1158 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)id;
1159
1160 BUG_ON(!chan);
1161
1162 /*
1163 * Disable DMA channel IRQ until we process completed
1164 * descriptors
1165 */
1166 disable_irq_nosync(chan->rx_irq);
1167
1168 /*
1169 * Schedule the tasklet to handle all cleanup of the current
1170 * transaction. It will start a new transaction if there is
1171 * one pending.
1172 */
1173 tasklet_schedule(&chan->tasklet);
1174
1175 return IRQ_HANDLED;
1176 }
1177
1178 static irqreturn_t xgene_dma_err_isr(int irq, void *id)
1179 {
1180 struct xgene_dma *pdma = (struct xgene_dma *)id;
1181 unsigned long int_mask;
1182 u32 val, i;
1183
1184 val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
1185
1186 /* Clear DMA interrupts */
1187 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
1188
1189 /* Print DMA error info */
1190 int_mask = val >> XGENE_DMA_INT_MASK_SHIFT;
1191 for_each_set_bit(i, &int_mask, ARRAY_SIZE(xgene_dma_err))
1192 dev_err(pdma->dev,
1193 "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]);
1194
1195 return IRQ_HANDLED;
1196 }
1197
1198 static void xgene_dma_wr_ring_state(struct xgene_dma_ring *ring)
1199 {
1200 int i;
1201
1202 iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE);
1203
1204 for (i = 0; i < XGENE_DMA_RING_NUM_CONFIG; i++)
1205 iowrite32(ring->state[i], ring->pdma->csr_ring +
1206 XGENE_DMA_RING_STATE_WR_BASE + (i * 4));
1207 }
1208
1209 static void xgene_dma_clr_ring_state(struct xgene_dma_ring *ring)
1210 {
1211 memset(ring->state, 0, sizeof(u32) * XGENE_DMA_RING_NUM_CONFIG);
1212 xgene_dma_wr_ring_state(ring);
1213 }
1214
1215 static void xgene_dma_setup_ring(struct xgene_dma_ring *ring)
1216 {
1217 void *ring_cfg = ring->state;
1218 u64 addr = ring->desc_paddr;
1219 u32 i, val;
1220
1221 ring->slots = ring->size / XGENE_DMA_RING_WQ_DESC_SIZE;
1222
1223 /* Clear DMA ring state */
1224 xgene_dma_clr_ring_state(ring);
1225
1226 /* Set DMA ring type */
1227 XGENE_DMA_RING_TYPE_SET(ring_cfg, XGENE_DMA_RING_TYPE_REGULAR);
1228
1229 if (ring->owner == XGENE_DMA_RING_OWNER_DMA) {
1230 /* Set recombination buffer and timeout */
1231 XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg);
1232 XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg);
1233 XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg);
1234 }
1235
1236 /* Initialize DMA ring state */
1237 XGENE_DMA_RING_SELTHRSH_SET(ring_cfg);
1238 XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg);
1239 XGENE_DMA_RING_COHERENT_SET(ring_cfg);
1240 XGENE_DMA_RING_ADDRL_SET(ring_cfg, addr);
1241 XGENE_DMA_RING_ADDRH_SET(ring_cfg, addr);
1242 XGENE_DMA_RING_SIZE_SET(ring_cfg, ring->cfgsize);
1243
1244 /* Write DMA ring configurations */
1245 xgene_dma_wr_ring_state(ring);
1246
1247 /* Set DMA ring id */
1248 iowrite32(XGENE_DMA_RING_ID_SETUP(ring->id),
1249 ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1250
1251 /* Set DMA ring buffer */
1252 iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring->num),
1253 ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1254
1255 if (ring->owner != XGENE_DMA_RING_OWNER_CPU)
1256 return;
1257
1258 /* Set empty signature to DMA Rx ring descriptors */
1259 for (i = 0; i < ring->slots; i++) {
1260 struct xgene_dma_desc_hw *desc;
1261
1262 desc = &ring->desc_hw[i];
1263 desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
1264 }
1265
1266 /* Enable DMA Rx ring interrupt */
1267 val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1268 XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num);
1269 iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1270 }
1271
1272 static void xgene_dma_clear_ring(struct xgene_dma_ring *ring)
1273 {
1274 u32 ring_id, val;
1275
1276 if (ring->owner == XGENE_DMA_RING_OWNER_CPU) {
1277 /* Disable DMA Rx ring interrupt */
1278 val = ioread32(ring->pdma->csr_ring +
1279 XGENE_DMA_RING_NE_INT_MODE);
1280 XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num);
1281 iowrite32(val, ring->pdma->csr_ring +
1282 XGENE_DMA_RING_NE_INT_MODE);
1283 }
1284
1285 /* Clear DMA ring state */
1286 ring_id = XGENE_DMA_RING_ID_SETUP(ring->id);
1287 iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1288
1289 iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1290 xgene_dma_clr_ring_state(ring);
1291 }
1292
1293 static void xgene_dma_set_ring_cmd(struct xgene_dma_ring *ring)
1294 {
1295 ring->cmd_base = ring->pdma->csr_ring_cmd +
1296 XGENE_DMA_RING_CMD_BASE_OFFSET((ring->num -
1297 XGENE_DMA_RING_NUM));
1298
1299 ring->cmd = ring->cmd_base + XGENE_DMA_RING_CMD_OFFSET;
1300 }
1301
1302 static int xgene_dma_get_ring_size(struct xgene_dma_chan *chan,
1303 enum xgene_dma_ring_cfgsize cfgsize)
1304 {
1305 int size;
1306
1307 switch (cfgsize) {
1308 case XGENE_DMA_RING_CFG_SIZE_512B:
1309 size = 0x200;
1310 break;
1311 case XGENE_DMA_RING_CFG_SIZE_2KB:
1312 size = 0x800;
1313 break;
1314 case XGENE_DMA_RING_CFG_SIZE_16KB:
1315 size = 0x4000;
1316 break;
1317 case XGENE_DMA_RING_CFG_SIZE_64KB:
1318 size = 0x10000;
1319 break;
1320 case XGENE_DMA_RING_CFG_SIZE_512KB:
1321 size = 0x80000;
1322 break;
1323 default:
1324 chan_err(chan, "Unsupported cfg ring size %d\n", cfgsize);
1325 return -EINVAL;
1326 }
1327
1328 return size;
1329 }
1330
1331 static void xgene_dma_delete_ring_one(struct xgene_dma_ring *ring)
1332 {
1333 /* Clear DMA ring configurations */
1334 xgene_dma_clear_ring(ring);
1335
1336 /* De-allocate DMA ring descriptor */
1337 if (ring->desc_vaddr) {
1338 dma_free_coherent(ring->pdma->dev, ring->size,
1339 ring->desc_vaddr, ring->desc_paddr);
1340 ring->desc_vaddr = NULL;
1341 }
1342 }
1343
1344 static void xgene_dma_delete_chan_rings(struct xgene_dma_chan *chan)
1345 {
1346 xgene_dma_delete_ring_one(&chan->rx_ring);
1347 xgene_dma_delete_ring_one(&chan->tx_ring);
1348 }
1349
1350 static int xgene_dma_create_ring_one(struct xgene_dma_chan *chan,
1351 struct xgene_dma_ring *ring,
1352 enum xgene_dma_ring_cfgsize cfgsize)
1353 {
1354 int ret;
1355
1356 /* Setup DMA ring descriptor variables */
1357 ring->pdma = chan->pdma;
1358 ring->cfgsize = cfgsize;
1359 ring->num = chan->pdma->ring_num++;
1360 ring->id = XGENE_DMA_RING_ID_GET(ring->owner, ring->buf_num);
1361
1362 ret = xgene_dma_get_ring_size(chan, cfgsize);
1363 if (ret <= 0)
1364 return ret;
1365 ring->size = ret;
1366
1367 /* Allocate memory for DMA ring descriptor */
1368 ring->desc_vaddr = dma_zalloc_coherent(chan->dev, ring->size,
1369 &ring->desc_paddr, GFP_KERNEL);
1370 if (!ring->desc_vaddr) {
1371 chan_err(chan, "Failed to allocate ring desc\n");
1372 return -ENOMEM;
1373 }
1374
1375 /* Configure and enable DMA ring */
1376 xgene_dma_set_ring_cmd(ring);
1377 xgene_dma_setup_ring(ring);
1378
1379 return 0;
1380 }
1381
1382 static int xgene_dma_create_chan_rings(struct xgene_dma_chan *chan)
1383 {
1384 struct xgene_dma_ring *rx_ring = &chan->rx_ring;
1385 struct xgene_dma_ring *tx_ring = &chan->tx_ring;
1386 int ret;
1387
1388 /* Create DMA Rx ring descriptor */
1389 rx_ring->owner = XGENE_DMA_RING_OWNER_CPU;
1390 rx_ring->buf_num = XGENE_DMA_CPU_BUFNUM + chan->id;
1391
1392 ret = xgene_dma_create_ring_one(chan, rx_ring,
1393 XGENE_DMA_RING_CFG_SIZE_64KB);
1394 if (ret)
1395 return ret;
1396
1397 chan_dbg(chan, "Rx ring id 0x%X num %d desc 0x%p\n",
1398 rx_ring->id, rx_ring->num, rx_ring->desc_vaddr);
1399
1400 /* Create DMA Tx ring descriptor */
1401 tx_ring->owner = XGENE_DMA_RING_OWNER_DMA;
1402 tx_ring->buf_num = XGENE_DMA_BUFNUM + chan->id;
1403
1404 ret = xgene_dma_create_ring_one(chan, tx_ring,
1405 XGENE_DMA_RING_CFG_SIZE_64KB);
1406 if (ret) {
1407 xgene_dma_delete_ring_one(rx_ring);
1408 return ret;
1409 }
1410
1411 tx_ring->dst_ring_num = XGENE_DMA_RING_DST_ID(rx_ring->num);
1412
1413 chan_dbg(chan,
1414 "Tx ring id 0x%X num %d desc 0x%p\n",
1415 tx_ring->id, tx_ring->num, tx_ring->desc_vaddr);
1416
1417 /* Set the max outstanding request possible to this channel */
1418 chan->max_outstanding = tx_ring->slots;
1419
1420 return ret;
1421 }
1422
1423 static int xgene_dma_init_rings(struct xgene_dma *pdma)
1424 {
1425 int ret, i, j;
1426
1427 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1428 ret = xgene_dma_create_chan_rings(&pdma->chan[i]);
1429 if (ret) {
1430 for (j = 0; j < i; j++)
1431 xgene_dma_delete_chan_rings(&pdma->chan[j]);
1432 return ret;
1433 }
1434 }
1435
1436 return ret;
1437 }
1438
1439 static void xgene_dma_enable(struct xgene_dma *pdma)
1440 {
1441 u32 val;
1442
1443 /* Configure and enable DMA engine */
1444 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1445 XGENE_DMA_CH_SETUP(val);
1446 XGENE_DMA_ENABLE(val);
1447 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1448 }
1449
1450 static void xgene_dma_disable(struct xgene_dma *pdma)
1451 {
1452 u32 val;
1453
1454 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1455 XGENE_DMA_DISABLE(val);
1456 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1457 }
1458
1459 static void xgene_dma_mask_interrupts(struct xgene_dma *pdma)
1460 {
1461 /*
1462 * Mask DMA ring overflow, underflow and
1463 * AXI write/read error interrupts
1464 */
1465 iowrite32(XGENE_DMA_INT_ALL_MASK,
1466 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1467 iowrite32(XGENE_DMA_INT_ALL_MASK,
1468 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1469 iowrite32(XGENE_DMA_INT_ALL_MASK,
1470 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1471 iowrite32(XGENE_DMA_INT_ALL_MASK,
1472 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1473 iowrite32(XGENE_DMA_INT_ALL_MASK,
1474 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1475
1476 /* Mask DMA error interrupts */
1477 iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
1478 }
1479
1480 static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma)
1481 {
1482 /*
1483 * Unmask DMA ring overflow, underflow and
1484 * AXI write/read error interrupts
1485 */
1486 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1487 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1488 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1489 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1490 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1491 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1492 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1493 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1494 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1495 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1496
1497 /* Unmask DMA error interrupts */
1498 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1499 pdma->csr_dma + XGENE_DMA_INT_MASK);
1500 }
1501
1502 static void xgene_dma_init_hw(struct xgene_dma *pdma)
1503 {
1504 u32 val;
1505
1506 /* Associate DMA ring to corresponding ring HW */
1507 iowrite32(XGENE_DMA_ASSOC_RING_MNGR1,
1508 pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
1509
1510 /* Configure RAID6 polynomial control setting */
1511 if (is_pq_enabled(pdma))
1512 iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D),
1513 pdma->csr_dma + XGENE_DMA_RAID6_CONT);
1514 else
1515 dev_info(pdma->dev, "PQ is disabled in HW\n");
1516
1517 xgene_dma_enable(pdma);
1518 xgene_dma_unmask_interrupts(pdma);
1519
1520 /* Get DMA id and version info */
1521 val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
1522
1523 /* DMA device info */
1524 dev_info(pdma->dev,
1525 "X-Gene DMA v%d.%02d.%02d driver registered %d channels",
1526 XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val),
1527 XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL);
1528 }
1529
1530 static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma)
1531 {
1532 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) &&
1533 (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST)))
1534 return 0;
1535
1536 iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN);
1537 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST);
1538
1539 /* Bring up memory */
1540 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1541
1542 /* Force a barrier */
1543 ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1544
1545 /* reset may take up to 1ms */
1546 usleep_range(1000, 1100);
1547
1548 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY)
1549 != XGENE_DMA_RING_BLK_MEM_RDY_VAL) {
1550 dev_err(pdma->dev,
1551 "Failed to release ring mngr memory from shutdown\n");
1552 return -ENODEV;
1553 }
1554
1555 /* program threshold set 1 and all hysteresis */
1556 iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL,
1557 pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1);
1558 iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL,
1559 pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1);
1560 iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL,
1561 pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS);
1562
1563 /* Enable QPcore and assign error queue */
1564 iowrite32(XGENE_DMA_RING_ENABLE,
1565 pdma->csr_ring + XGENE_DMA_RING_CONFIG);
1566
1567 return 0;
1568 }
1569
1570 static int xgene_dma_init_mem(struct xgene_dma *pdma)
1571 {
1572 int ret;
1573
1574 ret = xgene_dma_init_ring_mngr(pdma);
1575 if (ret)
1576 return ret;
1577
1578 /* Bring up memory */
1579 iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1580
1581 /* Force a barrier */
1582 ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1583
1584 /* reset may take up to 1ms */
1585 usleep_range(1000, 1100);
1586
1587 if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
1588 != XGENE_DMA_BLK_MEM_RDY_VAL) {
1589 dev_err(pdma->dev,
1590 "Failed to release DMA memory from shutdown\n");
1591 return -ENODEV;
1592 }
1593
1594 return 0;
1595 }
1596
1597 static int xgene_dma_request_irqs(struct xgene_dma *pdma)
1598 {
1599 struct xgene_dma_chan *chan;
1600 int ret, i, j;
1601
1602 /* Register DMA error irq */
1603 ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr,
1604 0, "dma_error", pdma);
1605 if (ret) {
1606 dev_err(pdma->dev,
1607 "Failed to register error IRQ %d\n", pdma->err_irq);
1608 return ret;
1609 }
1610
1611 /* Register DMA channel rx irq */
1612 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1613 chan = &pdma->chan[i];
1614 irq_set_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
1615 ret = devm_request_irq(chan->dev, chan->rx_irq,
1616 xgene_dma_chan_ring_isr,
1617 0, chan->name, chan);
1618 if (ret) {
1619 chan_err(chan, "Failed to register Rx IRQ %d\n",
1620 chan->rx_irq);
1621 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1622
1623 for (j = 0; j < i; j++) {
1624 chan = &pdma->chan[i];
1625 irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
1626 devm_free_irq(chan->dev, chan->rx_irq, chan);
1627 }
1628
1629 return ret;
1630 }
1631 }
1632
1633 return 0;
1634 }
1635
1636 static void xgene_dma_free_irqs(struct xgene_dma *pdma)
1637 {
1638 struct xgene_dma_chan *chan;
1639 int i;
1640
1641 /* Free DMA device error irq */
1642 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1643
1644 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1645 chan = &pdma->chan[i];
1646 irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
1647 devm_free_irq(chan->dev, chan->rx_irq, chan);
1648 }
1649 }
1650
1651 static void xgene_dma_set_caps(struct xgene_dma_chan *chan,
1652 struct dma_device *dma_dev)
1653 {
1654 /* Initialize DMA device capability mask */
1655 dma_cap_zero(dma_dev->cap_mask);
1656
1657 /* Set DMA device capability */
1658 dma_cap_set(DMA_SG, dma_dev->cap_mask);
1659
1660 /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR
1661 * and channel 1 supports XOR, PQ both. First thing here is we have
1662 * mechanism in hw to enable/disable PQ/XOR supports on channel 1,
1663 * we can make sure this by reading SoC Efuse register.
1664 * Second thing, we have hw errata that if we run channel 0 and
1665 * channel 1 simultaneously with executing XOR and PQ request,
1666 * suddenly DMA engine hangs, So here we enable XOR on channel 0 only
1667 * if XOR and PQ supports on channel 1 is disabled.
1668 */
1669 if ((chan->id == XGENE_DMA_PQ_CHANNEL) &&
1670 is_pq_enabled(chan->pdma)) {
1671 dma_cap_set(DMA_PQ, dma_dev->cap_mask);
1672 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1673 } else if ((chan->id == XGENE_DMA_XOR_CHANNEL) &&
1674 !is_pq_enabled(chan->pdma)) {
1675 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1676 }
1677
1678 /* Set base and prep routines */
1679 dma_dev->dev = chan->dev;
1680 dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources;
1681 dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources;
1682 dma_dev->device_issue_pending = xgene_dma_issue_pending;
1683 dma_dev->device_tx_status = xgene_dma_tx_status;
1684 dma_dev->device_prep_dma_sg = xgene_dma_prep_sg;
1685
1686 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1687 dma_dev->device_prep_dma_xor = xgene_dma_prep_xor;
1688 dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC;
1689 dma_dev->xor_align = DMAENGINE_ALIGN_64_BYTES;
1690 }
1691
1692 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1693 dma_dev->device_prep_dma_pq = xgene_dma_prep_pq;
1694 dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC;
1695 dma_dev->pq_align = DMAENGINE_ALIGN_64_BYTES;
1696 }
1697 }
1698
1699 static int xgene_dma_async_register(struct xgene_dma *pdma, int id)
1700 {
1701 struct xgene_dma_chan *chan = &pdma->chan[id];
1702 struct dma_device *dma_dev = &pdma->dma_dev[id];
1703 int ret;
1704
1705 chan->dma_chan.device = dma_dev;
1706
1707 spin_lock_init(&chan->lock);
1708 INIT_LIST_HEAD(&chan->ld_pending);
1709 INIT_LIST_HEAD(&chan->ld_running);
1710 INIT_LIST_HEAD(&chan->ld_completed);
1711 tasklet_init(&chan->tasklet, xgene_dma_tasklet_cb,
1712 (unsigned long)chan);
1713
1714 chan->pending = 0;
1715 chan->desc_pool = NULL;
1716 dma_cookie_init(&chan->dma_chan);
1717
1718 /* Setup dma device capabilities and prep routines */
1719 xgene_dma_set_caps(chan, dma_dev);
1720
1721 /* Initialize DMA device list head */
1722 INIT_LIST_HEAD(&dma_dev->channels);
1723 list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels);
1724
1725 /* Register with Linux async DMA framework*/
1726 ret = dma_async_device_register(dma_dev);
1727 if (ret) {
1728 chan_err(chan, "Failed to register async device %d", ret);
1729 tasklet_kill(&chan->tasklet);
1730
1731 return ret;
1732 }
1733
1734 /* DMA capability info */
1735 dev_info(pdma->dev,
1736 "%s: CAPABILITY ( %s%s%s)\n", dma_chan_name(&chan->dma_chan),
1737 dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "",
1738 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "",
1739 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : "");
1740
1741 return 0;
1742 }
1743
1744 static int xgene_dma_init_async(struct xgene_dma *pdma)
1745 {
1746 int ret, i, j;
1747
1748 for (i = 0; i < XGENE_DMA_MAX_CHANNEL ; i++) {
1749 ret = xgene_dma_async_register(pdma, i);
1750 if (ret) {
1751 for (j = 0; j < i; j++) {
1752 dma_async_device_unregister(&pdma->dma_dev[j]);
1753 tasklet_kill(&pdma->chan[j].tasklet);
1754 }
1755
1756 return ret;
1757 }
1758 }
1759
1760 return ret;
1761 }
1762
1763 static void xgene_dma_async_unregister(struct xgene_dma *pdma)
1764 {
1765 int i;
1766
1767 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1768 dma_async_device_unregister(&pdma->dma_dev[i]);
1769 }
1770
1771 static void xgene_dma_init_channels(struct xgene_dma *pdma)
1772 {
1773 struct xgene_dma_chan *chan;
1774 int i;
1775
1776 pdma->ring_num = XGENE_DMA_RING_NUM;
1777
1778 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1779 chan = &pdma->chan[i];
1780 chan->dev = pdma->dev;
1781 chan->pdma = pdma;
1782 chan->id = i;
1783 snprintf(chan->name, sizeof(chan->name), "dmachan%d", chan->id);
1784 }
1785 }
1786
1787 static int xgene_dma_get_resources(struct platform_device *pdev,
1788 struct xgene_dma *pdma)
1789 {
1790 struct resource *res;
1791 int irq, i;
1792
1793 /* Get DMA csr region */
1794 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1795 if (!res) {
1796 dev_err(&pdev->dev, "Failed to get csr region\n");
1797 return -ENXIO;
1798 }
1799
1800 pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
1801 resource_size(res));
1802 if (!pdma->csr_dma) {
1803 dev_err(&pdev->dev, "Failed to ioremap csr region");
1804 return -ENOMEM;
1805 }
1806
1807 /* Get DMA ring csr region */
1808 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1809 if (!res) {
1810 dev_err(&pdev->dev, "Failed to get ring csr region\n");
1811 return -ENXIO;
1812 }
1813
1814 pdma->csr_ring = devm_ioremap(&pdev->dev, res->start,
1815 resource_size(res));
1816 if (!pdma->csr_ring) {
1817 dev_err(&pdev->dev, "Failed to ioremap ring csr region");
1818 return -ENOMEM;
1819 }
1820
1821 /* Get DMA ring cmd csr region */
1822 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1823 if (!res) {
1824 dev_err(&pdev->dev, "Failed to get ring cmd csr region\n");
1825 return -ENXIO;
1826 }
1827
1828 pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
1829 resource_size(res));
1830 if (!pdma->csr_ring_cmd) {
1831 dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region");
1832 return -ENOMEM;
1833 }
1834
1835 pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET;
1836
1837 /* Get efuse csr region */
1838 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1839 if (!res) {
1840 dev_err(&pdev->dev, "Failed to get efuse csr region\n");
1841 return -ENXIO;
1842 }
1843
1844 pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
1845 resource_size(res));
1846 if (!pdma->csr_efuse) {
1847 dev_err(&pdev->dev, "Failed to ioremap efuse csr region");
1848 return -ENOMEM;
1849 }
1850
1851 /* Get DMA error interrupt */
1852 irq = platform_get_irq(pdev, 0);
1853 if (irq <= 0) {
1854 dev_err(&pdev->dev, "Failed to get Error IRQ\n");
1855 return -ENXIO;
1856 }
1857
1858 pdma->err_irq = irq;
1859
1860 /* Get DMA Rx ring descriptor interrupts for all DMA channels */
1861 for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) {
1862 irq = platform_get_irq(pdev, i);
1863 if (irq <= 0) {
1864 dev_err(&pdev->dev, "Failed to get Rx IRQ\n");
1865 return -ENXIO;
1866 }
1867
1868 pdma->chan[i - 1].rx_irq = irq;
1869 }
1870
1871 return 0;
1872 }
1873
1874 static int xgene_dma_probe(struct platform_device *pdev)
1875 {
1876 struct xgene_dma *pdma;
1877 int ret, i;
1878
1879 pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
1880 if (!pdma)
1881 return -ENOMEM;
1882
1883 pdma->dev = &pdev->dev;
1884 platform_set_drvdata(pdev, pdma);
1885
1886 ret = xgene_dma_get_resources(pdev, pdma);
1887 if (ret)
1888 return ret;
1889
1890 pdma->clk = devm_clk_get(&pdev->dev, NULL);
1891 if (IS_ERR(pdma->clk) && !ACPI_COMPANION(&pdev->dev)) {
1892 dev_err(&pdev->dev, "Failed to get clk\n");
1893 return PTR_ERR(pdma->clk);
1894 }
1895
1896 /* Enable clk before accessing registers */
1897 if (!IS_ERR(pdma->clk)) {
1898 ret = clk_prepare_enable(pdma->clk);
1899 if (ret) {
1900 dev_err(&pdev->dev, "Failed to enable clk %d\n", ret);
1901 return ret;
1902 }
1903 }
1904
1905 /* Remove DMA RAM out of shutdown */
1906 ret = xgene_dma_init_mem(pdma);
1907 if (ret)
1908 goto err_clk_enable;
1909
1910 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(42));
1911 if (ret) {
1912 dev_err(&pdev->dev, "No usable DMA configuration\n");
1913 goto err_dma_mask;
1914 }
1915
1916 /* Initialize DMA channels software state */
1917 xgene_dma_init_channels(pdma);
1918
1919 /* Configue DMA rings */
1920 ret = xgene_dma_init_rings(pdma);
1921 if (ret)
1922 goto err_clk_enable;
1923
1924 ret = xgene_dma_request_irqs(pdma);
1925 if (ret)
1926 goto err_request_irq;
1927
1928 /* Configure and enable DMA engine */
1929 xgene_dma_init_hw(pdma);
1930
1931 /* Register DMA device with linux async framework */
1932 ret = xgene_dma_init_async(pdma);
1933 if (ret)
1934 goto err_async_init;
1935
1936 return 0;
1937
1938 err_async_init:
1939 xgene_dma_free_irqs(pdma);
1940
1941 err_request_irq:
1942 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1943 xgene_dma_delete_chan_rings(&pdma->chan[i]);
1944
1945 err_dma_mask:
1946 err_clk_enable:
1947 if (!IS_ERR(pdma->clk))
1948 clk_disable_unprepare(pdma->clk);
1949
1950 return ret;
1951 }
1952
1953 static int xgene_dma_remove(struct platform_device *pdev)
1954 {
1955 struct xgene_dma *pdma = platform_get_drvdata(pdev);
1956 struct xgene_dma_chan *chan;
1957 int i;
1958
1959 xgene_dma_async_unregister(pdma);
1960
1961 /* Mask interrupts and disable DMA engine */
1962 xgene_dma_mask_interrupts(pdma);
1963 xgene_dma_disable(pdma);
1964 xgene_dma_free_irqs(pdma);
1965
1966 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1967 chan = &pdma->chan[i];
1968 tasklet_kill(&chan->tasklet);
1969 xgene_dma_delete_chan_rings(chan);
1970 }
1971
1972 if (!IS_ERR(pdma->clk))
1973 clk_disable_unprepare(pdma->clk);
1974
1975 return 0;
1976 }
1977
1978 #ifdef CONFIG_ACPI
1979 static const struct acpi_device_id xgene_dma_acpi_match_ptr[] = {
1980 {"APMC0D43", 0},
1981 {},
1982 };
1983 MODULE_DEVICE_TABLE(acpi, xgene_dma_acpi_match_ptr);
1984 #endif
1985
1986 static const struct of_device_id xgene_dma_of_match_ptr[] = {
1987 {.compatible = "apm,xgene-storm-dma",},
1988 {},
1989 };
1990 MODULE_DEVICE_TABLE(of, xgene_dma_of_match_ptr);
1991
1992 static struct platform_driver xgene_dma_driver = {
1993 .probe = xgene_dma_probe,
1994 .remove = xgene_dma_remove,
1995 .driver = {
1996 .name = "X-Gene-DMA",
1997 .of_match_table = xgene_dma_of_match_ptr,
1998 .acpi_match_table = ACPI_PTR(xgene_dma_acpi_match_ptr),
1999 },
2000 };
2001
2002 module_platform_driver(xgene_dma_driver);
2003
2004 MODULE_DESCRIPTION("APM X-Gene SoC DMA driver");
2005 MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>");
2006 MODULE_AUTHOR("Loc Ho <lho@apm.com>");
2007 MODULE_LICENSE("GPL");
2008 MODULE_VERSION("1.0");
Linux with added FPC-III support