2 tristate "Intel(R) Trace Hub controller"
4 Intel(R) Trace Hub (TH) is a set of hardware blocks (subdevices) that
5 produce, switch and output trace data from multiple hardware and
6 software sources over several types of trace output ports encoded
7 in System Trace Protocol (MIPI STPv2) and is intended to perform
10 This option enables intel_th bus and common code used by TH
11 subdevices to interact with each other and hardware and for
12 platform glue layers to drive Intel TH devices.
14 Say Y here to enable Intel(R) Trace Hub controller support.
19 tristate "Intel(R) Trace Hub PCI controller"
22 Intel(R) Trace Hub may exist as a PCI device. This option enables
23 support glue layer for PCI-based Intel TH.
25 Say Y here to enable PCI Intel TH support.
28 tristate "Intel(R) Trace Hub Global Trace Hub"
30 Global Trace Hub (GTH) is the central component of the
31 Intel TH infrastructure and acts as a switch for source
32 and output devices. This driver is required for other
33 Intel TH subdevices to initialize.
35 Say Y here to enable GTH subdevice of Intel(R) Trace Hub.
38 tristate "Intel(R) Trace Hub Software Trace Hub support"
41 Software Trace Hub (STH) enables trace data from software
42 trace sources to be sent out via Intel(R) Trace Hub. It
43 uses stm class device to interface with its sources.
45 Say Y here to enable STH subdevice of Intel(R) Trace Hub.
48 tristate "Intel(R) Trace Hub Memory Storage Unit"
50 Memory Storage Unit (MSU) trace output device enables
51 storing STP traces to system memory. It supports single
52 and multiblock modes of operation and provides read()
53 and mmap() access to the collected data.
55 Say Y here to enable MSU output device for Intel TH.
58 tristate "Intel(R) Trace Hub PTI output"
60 Parallel Trace Interface unit (PTI) is a trace output device
61 of Intel TH architecture that facilitates STP trace output via
64 Say Y to enable PTI output of Intel TH data.
67 bool "Intel(R) Trace Hub debugging"
70 Say Y here to enable debugging.