?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / drivers / infiniband / hw / cxgb3 / iwch_qp.c
blobd0548fc6395eac2343775ea4a4b85d3c83bb98b0
1 /*
2 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <linux/sched.h>
33 #include <linux/gfp.h>
34 #include "iwch_provider.h"
35 #include "iwch.h"
36 #include "iwch_cm.h"
37 #include "cxio_hal.h"
38 #include "cxio_resource.h"
39
40 #define NO_SUPPORT -1
41
42 static int build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
43 u8 * flit_cnt)
44 {
45 int i;
46 u32 plen;
47
48 switch (wr->opcode) {
49 case IB_WR_SEND:
50 if (wr->send_flags & IB_SEND_SOLICITED)
51 wqe->send.rdmaop = T3_SEND_WITH_SE;
52 else
53 wqe->send.rdmaop = T3_SEND;
54 wqe->send.rem_stag = 0;
55 break;
56 case IB_WR_SEND_WITH_INV:
57 if (wr->send_flags & IB_SEND_SOLICITED)
58 wqe->send.rdmaop = T3_SEND_WITH_SE_INV;
59 else
60 wqe->send.rdmaop = T3_SEND_WITH_INV;
61 wqe->send.rem_stag = cpu_to_be32(wr->ex.invalidate_rkey);
62 break;
63 default:
64 return -EINVAL;
65 }
66 if (wr->num_sge > T3_MAX_SGE)
67 return -EINVAL;
68 wqe->send.reserved[0] = 0;
69 wqe->send.reserved[1] = 0;
70 wqe->send.reserved[2] = 0;
71 plen = 0;
72 for (i = 0; i < wr->num_sge; i++) {
73 if ((plen + wr->sg_list[i].length) < plen)
74 return -EMSGSIZE;
75
76 plen += wr->sg_list[i].length;
77 wqe->send.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
78 wqe->send.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
79 wqe->send.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
80 }
81 wqe->send.num_sgle = cpu_to_be32(wr->num_sge);
82 *flit_cnt = 4 + ((wr->num_sge) << 1);
83 wqe->send.plen = cpu_to_be32(plen);
84 return 0;
85 }
86
87 static int build_rdma_write(union t3_wr *wqe, struct ib_send_wr *wr,
88 u8 *flit_cnt)
89 {
90 int i;
91 u32 plen;
92 if (wr->num_sge > T3_MAX_SGE)
93 return -EINVAL;
94 wqe->write.rdmaop = T3_RDMA_WRITE;
95 wqe->write.reserved[0] = 0;
96 wqe->write.reserved[1] = 0;
97 wqe->write.reserved[2] = 0;
98 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
99 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
100
101 if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) {
102 plen = 4;
103 wqe->write.sgl[0].stag = wr->ex.imm_data;
104 wqe->write.sgl[0].len = cpu_to_be32(0);
105 wqe->write.num_sgle = cpu_to_be32(0);
106 *flit_cnt = 6;
107 } else {
108 plen = 0;
109 for (i = 0; i < wr->num_sge; i++) {
110 if ((plen + wr->sg_list[i].length) < plen) {
111 return -EMSGSIZE;
112 }
113 plen += wr->sg_list[i].length;
114 wqe->write.sgl[i].stag =
115 cpu_to_be32(wr->sg_list[i].lkey);
116 wqe->write.sgl[i].len =
117 cpu_to_be32(wr->sg_list[i].length);
118 wqe->write.sgl[i].to =
119 cpu_to_be64(wr->sg_list[i].addr);
120 }
121 wqe->write.num_sgle = cpu_to_be32(wr->num_sge);
122 *flit_cnt = 5 + ((wr->num_sge) << 1);
123 }
124 wqe->write.plen = cpu_to_be32(plen);
125 return 0;
126 }
127
128 static int build_rdma_read(union t3_wr *wqe, struct ib_send_wr *wr,
129 u8 *flit_cnt)
130 {
131 if (wr->num_sge > 1)
132 return -EINVAL;
133 wqe->read.rdmaop = T3_READ_REQ;
134 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
135 wqe->read.local_inv = 1;
136 else
137 wqe->read.local_inv = 0;
138 wqe->read.reserved[0] = 0;
139 wqe->read.reserved[1] = 0;
140 wqe->read.rem_stag = cpu_to_be32(rdma_wr(wr)->rkey);
141 wqe->read.rem_to = cpu_to_be64(rdma_wr(wr)->remote_addr);
142 wqe->read.local_stag = cpu_to_be32(wr->sg_list[0].lkey);
143 wqe->read.local_len = cpu_to_be32(wr->sg_list[0].length);
144 wqe->read.local_to = cpu_to_be64(wr->sg_list[0].addr);
145 *flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
146 return 0;
147 }
148
149 static int build_memreg(union t3_wr *wqe, struct ib_reg_wr *wr,
150 u8 *flit_cnt, int *wr_cnt, struct t3_wq *wq)
151 {
152 struct iwch_mr *mhp = to_iwch_mr(wr->mr);
153 int i;
154 __be64 *p;
155
156 if (mhp->npages > T3_MAX_FASTREG_DEPTH)
157 return -EINVAL;
158 *wr_cnt = 1;
159 wqe->fastreg.stag = cpu_to_be32(wr->key);
160 wqe->fastreg.len = cpu_to_be32(mhp->ibmr.length);
161 wqe->fastreg.va_base_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
162 wqe->fastreg.va_base_lo_fbo =
163 cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
164 wqe->fastreg.page_type_perms = cpu_to_be32(
165 V_FR_PAGE_COUNT(mhp->npages) |
166 V_FR_PAGE_SIZE(ilog2(wr->mr->page_size) - 12) |
167 V_FR_TYPE(TPT_VATO) |
168 V_FR_PERMS(iwch_ib_to_tpt_access(wr->access)));
169 p = &wqe->fastreg.pbl_addrs[0];
170 for (i = 0; i < mhp->npages; i++, p++) {
171
172 /* If we need a 2nd WR, then set it up */
173 if (i == T3_MAX_FASTREG_FRAG) {
174 *wr_cnt = 2;
175 wqe = (union t3_wr *)(wq->queue +
176 Q_PTR2IDX((wq->wptr+1), wq->size_log2));
177 build_fw_riwrh((void *)wqe, T3_WR_FASTREG, 0,
178 Q_GENBIT(wq->wptr + 1, wq->size_log2),
179 0, 1 + mhp->npages - T3_MAX_FASTREG_FRAG,
180 T3_EOP);
181
182 p = &wqe->pbl_frag.pbl_addrs[0];
183 }
184 *p = cpu_to_be64((u64)mhp->pages[i]);
185 }
186 *flit_cnt = 5 + mhp->npages;
187 if (*flit_cnt > 15)
188 *flit_cnt = 15;
189 return 0;
190 }
191
192 static int build_inv_stag(union t3_wr *wqe, struct ib_send_wr *wr,
193 u8 *flit_cnt)
194 {
195 wqe->local_inv.stag = cpu_to_be32(wr->ex.invalidate_rkey);
196 wqe->local_inv.reserved = 0;
197 *flit_cnt = sizeof(struct t3_local_inv_wr) >> 3;
198 return 0;
199 }
200
201 static int iwch_sgl2pbl_map(struct iwch_dev *rhp, struct ib_sge *sg_list,
202 u32 num_sgle, u32 * pbl_addr, u8 * page_size)
203 {
204 int i;
205 struct iwch_mr *mhp;
206 u64 offset;
207 for (i = 0; i < num_sgle; i++) {
208
209 mhp = get_mhp(rhp, (sg_list[i].lkey) >> 8);
210 if (!mhp) {
211 PDBG("%s %d\n", __func__, __LINE__);
212 return -EIO;
213 }
214 if (!mhp->attr.state) {
215 PDBG("%s %d\n", __func__, __LINE__);
216 return -EIO;
217 }
218 if (mhp->attr.zbva) {
219 PDBG("%s %d\n", __func__, __LINE__);
220 return -EIO;
221 }
222
223 if (sg_list[i].addr < mhp->attr.va_fbo) {
224 PDBG("%s %d\n", __func__, __LINE__);
225 return -EINVAL;
226 }
227 if (sg_list[i].addr + ((u64) sg_list[i].length) <
228 sg_list[i].addr) {
229 PDBG("%s %d\n", __func__, __LINE__);
230 return -EINVAL;
231 }
232 if (sg_list[i].addr + ((u64) sg_list[i].length) >
233 mhp->attr.va_fbo + ((u64) mhp->attr.len)) {
234 PDBG("%s %d\n", __func__, __LINE__);
235 return -EINVAL;
236 }
237 offset = sg_list[i].addr - mhp->attr.va_fbo;
238 offset += mhp->attr.va_fbo &
239 ((1UL << (12 + mhp->attr.page_size)) - 1);
240 pbl_addr[i] = ((mhp->attr.pbl_addr -
241 rhp->rdev.rnic_info.pbl_base) >> 3) +
242 (offset >> (12 + mhp->attr.page_size));
243 page_size[i] = mhp->attr.page_size;
244 }
245 return 0;
246 }
247
248 static int build_rdma_recv(struct iwch_qp *qhp, union t3_wr *wqe,
249 struct ib_recv_wr *wr)
250 {
251 int i, err = 0;
252 u32 pbl_addr[T3_MAX_SGE];
253 u8 page_size[T3_MAX_SGE];
254
255 err = iwch_sgl2pbl_map(qhp->rhp, wr->sg_list, wr->num_sge, pbl_addr,
256 page_size);
257 if (err)
258 return err;
259 wqe->recv.pagesz[0] = page_size[0];
260 wqe->recv.pagesz[1] = page_size[1];
261 wqe->recv.pagesz[2] = page_size[2];
262 wqe->recv.pagesz[3] = page_size[3];
263 wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
264 for (i = 0; i < wr->num_sge; i++) {
265 wqe->recv.sgl[i].stag = cpu_to_be32(wr->sg_list[i].lkey);
266 wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
267
268 /* to in the WQE == the offset into the page */
269 wqe->recv.sgl[i].to = cpu_to_be64(((u32)wr->sg_list[i].addr) &
270 ((1UL << (12 + page_size[i])) - 1));
271
272 /* pbl_addr is the adapters address in the PBL */
273 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_addr[i]);
274 }
275 for (; i < T3_MAX_SGE; i++) {
276 wqe->recv.sgl[i].stag = 0;
277 wqe->recv.sgl[i].len = 0;
278 wqe->recv.sgl[i].to = 0;
279 wqe->recv.pbl_addr[i] = 0;
280 }
281 qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
282 qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
283 qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
284 qhp->wq.rq_size_log2)].pbl_addr = 0;
285 return 0;
286 }
287
288 static int build_zero_stag_recv(struct iwch_qp *qhp, union t3_wr *wqe,
289 struct ib_recv_wr *wr)
290 {
291 int i;
292 u32 pbl_addr;
293 u32 pbl_offset;
294
295
296 /*
297 * The T3 HW requires the PBL in the HW recv descriptor to reference
298 * a PBL entry. So we allocate the max needed PBL memory here and pass
299 * it to the uP in the recv WR. The uP will build the PBL and setup
300 * the HW recv descriptor.
301 */
302 pbl_addr = cxio_hal_pblpool_alloc(&qhp->rhp->rdev, T3_STAG0_PBL_SIZE);
303 if (!pbl_addr)
304 return -ENOMEM;
305
306 /*
307 * Compute the 8B aligned offset.
308 */
309 pbl_offset = (pbl_addr - qhp->rhp->rdev.rnic_info.pbl_base) >> 3;
310
311 wqe->recv.num_sgle = cpu_to_be32(wr->num_sge);
312
313 for (i = 0; i < wr->num_sge; i++) {
314
315 /*
316 * Use a 128MB page size. This and an imposed 128MB
317 * sge length limit allows us to require only a 2-entry HW
318 * PBL for each SGE. This restriction is acceptable since
319 * since it is not possible to allocate 128MB of contiguous
320 * DMA coherent memory!
321 */
322 if (wr->sg_list[i].length > T3_STAG0_MAX_PBE_LEN)
323 return -EINVAL;
324 wqe->recv.pagesz[i] = T3_STAG0_PAGE_SHIFT;
325
326 /*
327 * T3 restricts a recv to all zero-stag or all non-zero-stag.
328 */
329 if (wr->sg_list[i].lkey != 0)
330 return -EINVAL;
331 wqe->recv.sgl[i].stag = 0;
332 wqe->recv.sgl[i].len = cpu_to_be32(wr->sg_list[i].length);
333 wqe->recv.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
334 wqe->recv.pbl_addr[i] = cpu_to_be32(pbl_offset);
335 pbl_offset += 2;
336 }
337 for (; i < T3_MAX_SGE; i++) {
338 wqe->recv.pagesz[i] = 0;
339 wqe->recv.sgl[i].stag = 0;
340 wqe->recv.sgl[i].len = 0;
341 wqe->recv.sgl[i].to = 0;
342 wqe->recv.pbl_addr[i] = 0;
343 }
344 qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
345 qhp->wq.rq_size_log2)].wr_id = wr->wr_id;
346 qhp->wq.rq[Q_PTR2IDX(qhp->wq.rq_wptr,
347 qhp->wq.rq_size_log2)].pbl_addr = pbl_addr;
348 return 0;
349 }
350
351 int iwch_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
352 struct ib_send_wr **bad_wr)
353 {
354 int err = 0;
355 u8 uninitialized_var(t3_wr_flit_cnt);
356 enum t3_wr_opcode t3_wr_opcode = 0;
357 enum t3_wr_flags t3_wr_flags;
358 struct iwch_qp *qhp;
359 u32 idx;
360 union t3_wr *wqe;
361 u32 num_wrs;
362 unsigned long flag;
363 struct t3_swsq *sqp;
364 int wr_cnt = 1;
365
366 qhp = to_iwch_qp(ibqp);
367 spin_lock_irqsave(&qhp->lock, flag);
368 if (qhp->attr.state > IWCH_QP_STATE_RTS) {
369 spin_unlock_irqrestore(&qhp->lock, flag);
370 err = -EINVAL;
371 goto out;
372 }
373 num_wrs = Q_FREECNT(qhp->wq.sq_rptr, qhp->wq.sq_wptr,
374 qhp->wq.sq_size_log2);
375 if (num_wrs == 0) {
376 spin_unlock_irqrestore(&qhp->lock, flag);
377 err = -ENOMEM;
378 goto out;
379 }
380 while (wr) {
381 if (num_wrs == 0) {
382 err = -ENOMEM;
383 break;
384 }
385 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
386 wqe = (union t3_wr *) (qhp->wq.queue + idx);
387 t3_wr_flags = 0;
388 if (wr->send_flags & IB_SEND_SOLICITED)
389 t3_wr_flags |= T3_SOLICITED_EVENT_FLAG;
390 if (wr->send_flags & IB_SEND_SIGNALED)
391 t3_wr_flags |= T3_COMPLETION_FLAG;
392 sqp = qhp->wq.sq +
393 Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2);
394 switch (wr->opcode) {
395 case IB_WR_SEND:
396 case IB_WR_SEND_WITH_INV:
397 if (wr->send_flags & IB_SEND_FENCE)
398 t3_wr_flags |= T3_READ_FENCE_FLAG;
399 t3_wr_opcode = T3_WR_SEND;
400 err = build_rdma_send(wqe, wr, &t3_wr_flit_cnt);
401 break;
402 case IB_WR_RDMA_WRITE:
403 case IB_WR_RDMA_WRITE_WITH_IMM:
404 t3_wr_opcode = T3_WR_WRITE;
405 err = build_rdma_write(wqe, wr, &t3_wr_flit_cnt);
406 break;
407 case IB_WR_RDMA_READ:
408 case IB_WR_RDMA_READ_WITH_INV:
409 t3_wr_opcode = T3_WR_READ;
410 t3_wr_flags = 0; /* T3 reads are always signaled */
411 err = build_rdma_read(wqe, wr, &t3_wr_flit_cnt);
412 if (err)
413 break;
414 sqp->read_len = wqe->read.local_len;
415 if (!qhp->wq.oldest_read)
416 qhp->wq.oldest_read = sqp;
417 break;
418 case IB_WR_REG_MR:
419 t3_wr_opcode = T3_WR_FASTREG;
420 err = build_memreg(wqe, reg_wr(wr), &t3_wr_flit_cnt,
421 &wr_cnt, &qhp->wq);
422 break;
423 case IB_WR_LOCAL_INV:
424 if (wr->send_flags & IB_SEND_FENCE)
425 t3_wr_flags |= T3_LOCAL_FENCE_FLAG;
426 t3_wr_opcode = T3_WR_INV_STAG;
427 err = build_inv_stag(wqe, wr, &t3_wr_flit_cnt);
428 break;
429 default:
430 PDBG("%s post of type=%d TBD!\n", __func__,
431 wr->opcode);
432 err = -EINVAL;
433 }
434 if (err)
435 break;
436 wqe->send.wrid.id0.hi = qhp->wq.sq_wptr;
437 sqp->wr_id = wr->wr_id;
438 sqp->opcode = wr2opcode(t3_wr_opcode);
439 sqp->sq_wptr = qhp->wq.sq_wptr;
440 sqp->complete = 0;
441 sqp->signaled = (wr->send_flags & IB_SEND_SIGNALED);
442
443 build_fw_riwrh((void *) wqe, t3_wr_opcode, t3_wr_flags,
444 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
445 0, t3_wr_flit_cnt,
446 (wr_cnt == 1) ? T3_SOPEOP : T3_SOP);
447 PDBG("%s cookie 0x%llx wq idx 0x%x swsq idx %ld opcode %d\n",
448 __func__, (unsigned long long) wr->wr_id, idx,
449 Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2),
450 sqp->opcode);
451 wr = wr->next;
452 num_wrs--;
453 qhp->wq.wptr += wr_cnt;
454 ++(qhp->wq.sq_wptr);
455 }
456 spin_unlock_irqrestore(&qhp->lock, flag);
457 if (cxio_wq_db_enabled(&qhp->wq))
458 ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
459
460 out:
461 if (err)
462 *bad_wr = wr;
463 return err;
464 }
465
466 int iwch_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
467 struct ib_recv_wr **bad_wr)
468 {
469 int err = 0;
470 struct iwch_qp *qhp;
471 u32 idx;
472 union t3_wr *wqe;
473 u32 num_wrs;
474 unsigned long flag;
475
476 qhp = to_iwch_qp(ibqp);
477 spin_lock_irqsave(&qhp->lock, flag);
478 if (qhp->attr.state > IWCH_QP_STATE_RTS) {
479 spin_unlock_irqrestore(&qhp->lock, flag);
480 err = -EINVAL;
481 goto out;
482 }
483 num_wrs = Q_FREECNT(qhp->wq.rq_rptr, qhp->wq.rq_wptr,
484 qhp->wq.rq_size_log2) - 1;
485 if (!wr) {
486 spin_unlock_irqrestore(&qhp->lock, flag);
487 err = -ENOMEM;
488 goto out;
489 }
490 while (wr) {
491 if (wr->num_sge > T3_MAX_SGE) {
492 err = -EINVAL;
493 break;
494 }
495 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
496 wqe = (union t3_wr *) (qhp->wq.queue + idx);
497 if (num_wrs)
498 if (wr->sg_list[0].lkey)
499 err = build_rdma_recv(qhp, wqe, wr);
500 else
501 err = build_zero_stag_recv(qhp, wqe, wr);
502 else
503 err = -ENOMEM;
504
505 if (err)
506 break;
507
508 build_fw_riwrh((void *) wqe, T3_WR_RCV, T3_COMPLETION_FLAG,
509 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2),
510 0, sizeof(struct t3_receive_wr) >> 3, T3_SOPEOP);
511 PDBG("%s cookie 0x%llx idx 0x%x rq_wptr 0x%x rw_rptr 0x%x "
512 "wqe %p \n", __func__, (unsigned long long) wr->wr_id,
513 idx, qhp->wq.rq_wptr, qhp->wq.rq_rptr, wqe);
514 ++(qhp->wq.rq_wptr);
515 ++(qhp->wq.wptr);
516 wr = wr->next;
517 num_wrs--;
518 }
519 spin_unlock_irqrestore(&qhp->lock, flag);
520 if (cxio_wq_db_enabled(&qhp->wq))
521 ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
522
523 out:
524 if (err)
525 *bad_wr = wr;
526 return err;
527 }
528
529 int iwch_bind_mw(struct ib_qp *qp,
530 struct ib_mw *mw,
531 struct ib_mw_bind *mw_bind)
532 {
533 struct iwch_dev *rhp;
534 struct iwch_mw *mhp;
535 struct iwch_qp *qhp;
536 union t3_wr *wqe;
537 u32 pbl_addr;
538 u8 page_size;
539 u32 num_wrs;
540 unsigned long flag;
541 struct ib_sge sgl;
542 int err=0;
543 enum t3_wr_flags t3_wr_flags;
544 u32 idx;
545 struct t3_swsq *sqp;
546
547 qhp = to_iwch_qp(qp);
548 mhp = to_iwch_mw(mw);
549 rhp = qhp->rhp;
550
551 spin_lock_irqsave(&qhp->lock, flag);
552 if (qhp->attr.state > IWCH_QP_STATE_RTS) {
553 spin_unlock_irqrestore(&qhp->lock, flag);
554 return -EINVAL;
555 }
556 num_wrs = Q_FREECNT(qhp->wq.sq_rptr, qhp->wq.sq_wptr,
557 qhp->wq.sq_size_log2);
558 if (num_wrs == 0) {
559 spin_unlock_irqrestore(&qhp->lock, flag);
560 return -ENOMEM;
561 }
562 idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2);
563 PDBG("%s: idx 0x%0x, mw 0x%p, mw_bind 0x%p\n", __func__, idx,
564 mw, mw_bind);
565 wqe = (union t3_wr *) (qhp->wq.queue + idx);
566
567 t3_wr_flags = 0;
568 if (mw_bind->send_flags & IB_SEND_SIGNALED)
569 t3_wr_flags = T3_COMPLETION_FLAG;
570
571 sgl.addr = mw_bind->bind_info.addr;
572 sgl.lkey = mw_bind->bind_info.mr->lkey;
573 sgl.length = mw_bind->bind_info.length;
574 wqe->bind.reserved = 0;
575 wqe->bind.type = TPT_VATO;
576
577 /* TBD: check perms */
578 wqe->bind.perms = iwch_ib_to_tpt_bind_access(
579 mw_bind->bind_info.mw_access_flags);
580 wqe->bind.mr_stag = cpu_to_be32(mw_bind->bind_info.mr->lkey);
581 wqe->bind.mw_stag = cpu_to_be32(mw->rkey);
582 wqe->bind.mw_len = cpu_to_be32(mw_bind->bind_info.length);
583 wqe->bind.mw_va = cpu_to_be64(mw_bind->bind_info.addr);
584 err = iwch_sgl2pbl_map(rhp, &sgl, 1, &pbl_addr, &page_size);
585 if (err) {
586 spin_unlock_irqrestore(&qhp->lock, flag);
587 return err;
588 }
589 wqe->send.wrid.id0.hi = qhp->wq.sq_wptr;
590 sqp = qhp->wq.sq + Q_PTR2IDX(qhp->wq.sq_wptr, qhp->wq.sq_size_log2);
591 sqp->wr_id = mw_bind->wr_id;
592 sqp->opcode = T3_BIND_MW;
593 sqp->sq_wptr = qhp->wq.sq_wptr;
594 sqp->complete = 0;
595 sqp->signaled = (mw_bind->send_flags & IB_SEND_SIGNALED);
596 wqe->bind.mr_pbl_addr = cpu_to_be32(pbl_addr);
597 wqe->bind.mr_pagesz = page_size;
598 build_fw_riwrh((void *)wqe, T3_WR_BIND, t3_wr_flags,
599 Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), 0,
600 sizeof(struct t3_bind_mw_wr) >> 3, T3_SOPEOP);
601 ++(qhp->wq.wptr);
602 ++(qhp->wq.sq_wptr);
603 spin_unlock_irqrestore(&qhp->lock, flag);
604
605 if (cxio_wq_db_enabled(&qhp->wq))
606 ring_doorbell(qhp->wq.doorbell, qhp->wq.qpid);
607
608 return err;
609 }
610
611 static inline void build_term_codes(struct respQ_msg_t *rsp_msg,
612 u8 *layer_type, u8 *ecode)
613 {
614 int status = TPT_ERR_INTERNAL_ERR;
615 int tagged = 0;
616 int opcode = -1;
617 int rqtype = 0;
618 int send_inv = 0;
619
620 if (rsp_msg) {
621 status = CQE_STATUS(rsp_msg->cqe);
622 opcode = CQE_OPCODE(rsp_msg->cqe);
623 rqtype = RQ_TYPE(rsp_msg->cqe);
624 send_inv = (opcode == T3_SEND_WITH_INV) ||
625 (opcode == T3_SEND_WITH_SE_INV);
626 tagged = (opcode == T3_RDMA_WRITE) ||
627 (rqtype && (opcode == T3_READ_RESP));
628 }
629
630 switch (status) {
631 case TPT_ERR_STAG:
632 if (send_inv) {
633 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
634 *ecode = RDMAP_CANT_INV_STAG;
635 } else {
636 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
637 *ecode = RDMAP_INV_STAG;
638 }
639 break;
640 case TPT_ERR_PDID:
641 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
642 if ((opcode == T3_SEND_WITH_INV) ||
643 (opcode == T3_SEND_WITH_SE_INV))
644 *ecode = RDMAP_CANT_INV_STAG;
645 else
646 *ecode = RDMAP_STAG_NOT_ASSOC;
647 break;
648 case TPT_ERR_QPID:
649 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
650 *ecode = RDMAP_STAG_NOT_ASSOC;
651 break;
652 case TPT_ERR_ACCESS:
653 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
654 *ecode = RDMAP_ACC_VIOL;
655 break;
656 case TPT_ERR_WRAP:
657 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
658 *ecode = RDMAP_TO_WRAP;
659 break;
660 case TPT_ERR_BOUND:
661 if (tagged) {
662 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
663 *ecode = DDPT_BASE_BOUNDS;
664 } else {
665 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
666 *ecode = RDMAP_BASE_BOUNDS;
667 }
668 break;
669 case TPT_ERR_INVALIDATE_SHARED_MR:
670 case TPT_ERR_INVALIDATE_MR_WITH_MW_BOUND:
671 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
672 *ecode = RDMAP_CANT_INV_STAG;
673 break;
674 case TPT_ERR_ECC:
675 case TPT_ERR_ECC_PSTAG:
676 case TPT_ERR_INTERNAL_ERR:
677 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
678 *ecode = 0;
679 break;
680 case TPT_ERR_OUT_OF_RQE:
681 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
682 *ecode = DDPU_INV_MSN_NOBUF;
683 break;
684 case TPT_ERR_PBL_ADDR_BOUND:
685 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
686 *ecode = DDPT_BASE_BOUNDS;
687 break;
688 case TPT_ERR_CRC:
689 *layer_type = LAYER_MPA|DDP_LLP;
690 *ecode = MPA_CRC_ERR;
691 break;
692 case TPT_ERR_MARKER:
693 *layer_type = LAYER_MPA|DDP_LLP;
694 *ecode = MPA_MARKER_ERR;
695 break;
696 case TPT_ERR_PDU_LEN_ERR:
697 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
698 *ecode = DDPU_MSG_TOOBIG;
699 break;
700 case TPT_ERR_DDP_VERSION:
701 if (tagged) {
702 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
703 *ecode = DDPT_INV_VERS;
704 } else {
705 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
706 *ecode = DDPU_INV_VERS;
707 }
708 break;
709 case TPT_ERR_RDMA_VERSION:
710 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
711 *ecode = RDMAP_INV_VERS;
712 break;
713 case TPT_ERR_OPCODE:
714 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
715 *ecode = RDMAP_INV_OPCODE;
716 break;
717 case TPT_ERR_DDP_QUEUE_NUM:
718 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
719 *ecode = DDPU_INV_QN;
720 break;
721 case TPT_ERR_MSN:
722 case TPT_ERR_MSN_GAP:
723 case TPT_ERR_MSN_RANGE:
724 case TPT_ERR_IRD_OVERFLOW:
725 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
726 *ecode = DDPU_INV_MSN_RANGE;
727 break;
728 case TPT_ERR_TBIT:
729 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
730 *ecode = 0;
731 break;
732 case TPT_ERR_MO:
733 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
734 *ecode = DDPU_INV_MO;
735 break;
736 default:
737 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
738 *ecode = 0;
739 break;
740 }
741 }
742
743 int iwch_post_zb_read(struct iwch_ep *ep)
744 {
745 union t3_wr *wqe;
746 struct sk_buff *skb;
747 u8 flit_cnt = sizeof(struct t3_rdma_read_wr) >> 3;
748
749 PDBG("%s enter\n", __func__);
750 skb = alloc_skb(40, GFP_KERNEL);
751 if (!skb) {
752 printk(KERN_ERR "%s cannot send zb_read!!\n", __func__);
753 return -ENOMEM;
754 }
755 wqe = (union t3_wr *)skb_put(skb, sizeof(struct t3_rdma_read_wr));
756 memset(wqe, 0, sizeof(struct t3_rdma_read_wr));
757 wqe->read.rdmaop = T3_READ_REQ;
758 wqe->read.reserved[0] = 0;
759 wqe->read.reserved[1] = 0;
760 wqe->read.rem_stag = cpu_to_be32(1);
761 wqe->read.rem_to = cpu_to_be64(1);
762 wqe->read.local_stag = cpu_to_be32(1);
763 wqe->read.local_len = cpu_to_be32(0);
764 wqe->read.local_to = cpu_to_be64(1);
765 wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_READ));
766 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(ep->hwtid)|
767 V_FW_RIWR_LEN(flit_cnt));
768 skb->priority = CPL_PRIORITY_DATA;
769 return iwch_cxgb3_ofld_send(ep->com.qp->rhp->rdev.t3cdev_p, skb);
770 }
771
772 /*
773 * This posts a TERMINATE with layer=RDMA, type=catastrophic.
774 */
775 int iwch_post_terminate(struct iwch_qp *qhp, struct respQ_msg_t *rsp_msg)
776 {
777 union t3_wr *wqe;
778 struct terminate_message *term;
779 struct sk_buff *skb;
780
781 PDBG("%s %d\n", __func__, __LINE__);
782 skb = alloc_skb(40, GFP_ATOMIC);
783 if (!skb) {
784 printk(KERN_ERR "%s cannot send TERMINATE!\n", __func__);
785 return -ENOMEM;
786 }
787 wqe = (union t3_wr *)skb_put(skb, 40);
788 memset(wqe, 0, 40);
789 wqe->send.rdmaop = T3_TERMINATE;
790
791 /* immediate data length */
792 wqe->send.plen = htonl(4);
793
794 /* immediate data starts here. */
795 term = (struct terminate_message *)wqe->send.sgl;
796 build_term_codes(rsp_msg, &term->layer_etype, &term->ecode);
797 wqe->send.wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_SEND) |
798 V_FW_RIWR_FLAGS(T3_COMPLETION_FLAG | T3_NOTIFY_FLAG));
799 wqe->send.wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(qhp->ep->hwtid));
800 skb->priority = CPL_PRIORITY_DATA;
801 return iwch_cxgb3_ofld_send(qhp->rhp->rdev.t3cdev_p, skb);
802 }
803
804 /*
805 * Assumes qhp lock is held.
806 */
807 static void __flush_qp(struct iwch_qp *qhp, struct iwch_cq *rchp,
808 struct iwch_cq *schp)
809 {
810 int count;
811 int flushed;
812
813
814 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
815 /* take a ref on the qhp since we must release the lock */
816 atomic_inc(&qhp->refcnt);
817 spin_unlock(&qhp->lock);
818
819 /* locking hierarchy: cq lock first, then qp lock. */
820 spin_lock(&rchp->lock);
821 spin_lock(&qhp->lock);
822 cxio_flush_hw_cq(&rchp->cq);
823 cxio_count_rcqes(&rchp->cq, &qhp->wq, &count);
824 flushed = cxio_flush_rq(&qhp->wq, &rchp->cq, count);
825 spin_unlock(&qhp->lock);
826 spin_unlock(&rchp->lock);
827 if (flushed) {
828 spin_lock(&rchp->comp_handler_lock);
829 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
830 spin_unlock(&rchp->comp_handler_lock);
831 }
832
833 /* locking hierarchy: cq lock first, then qp lock. */
834 spin_lock(&schp->lock);
835 spin_lock(&qhp->lock);
836 cxio_flush_hw_cq(&schp->cq);
837 cxio_count_scqes(&schp->cq, &qhp->wq, &count);
838 flushed = cxio_flush_sq(&qhp->wq, &schp->cq, count);
839 spin_unlock(&qhp->lock);
840 spin_unlock(&schp->lock);
841 if (flushed) {
842 spin_lock(&schp->comp_handler_lock);
843 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
844 spin_unlock(&schp->comp_handler_lock);
845 }
846
847 /* deref */
848 if (atomic_dec_and_test(&qhp->refcnt))
849 wake_up(&qhp->wait);
850
851 spin_lock(&qhp->lock);
852 }
853
854 static void flush_qp(struct iwch_qp *qhp)
855 {
856 struct iwch_cq *rchp, *schp;
857
858 rchp = get_chp(qhp->rhp, qhp->attr.rcq);
859 schp = get_chp(qhp->rhp, qhp->attr.scq);
860
861 if (qhp->ibqp.uobject) {
862 cxio_set_wq_in_error(&qhp->wq);
863 cxio_set_cq_in_error(&rchp->cq);
864 spin_lock(&rchp->comp_handler_lock);
865 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
866 spin_unlock(&rchp->comp_handler_lock);
867 if (schp != rchp) {
868 cxio_set_cq_in_error(&schp->cq);
869 spin_lock(&schp->comp_handler_lock);
870 (*schp->ibcq.comp_handler)(&schp->ibcq,
871 schp->ibcq.cq_context);
872 spin_unlock(&schp->comp_handler_lock);
873 }
874 return;
875 }
876 __flush_qp(qhp, rchp, schp);
877 }
878
879
880 /*
881 * Return count of RECV WRs posted
882 */
883 u16 iwch_rqes_posted(struct iwch_qp *qhp)
884 {
885 union t3_wr *wqe = qhp->wq.queue;
886 u16 count = 0;
887
888 while (count < USHRT_MAX && fw_riwrh_opcode((struct fw_riwrh *)wqe) == T3_WR_RCV) {
889 count++;
890 wqe++;
891 }
892 PDBG("%s qhp %p count %u\n", __func__, qhp, count);
893 return count;
894 }
895
896 static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp,
897 enum iwch_qp_attr_mask mask,
898 struct iwch_qp_attributes *attrs)
899 {
900 struct t3_rdma_init_attr init_attr;
901 int ret;
902
903 init_attr.tid = qhp->ep->hwtid;
904 init_attr.qpid = qhp->wq.qpid;
905 init_attr.pdid = qhp->attr.pd;
906 init_attr.scqid = qhp->attr.scq;
907 init_attr.rcqid = qhp->attr.rcq;
908 init_attr.rq_addr = qhp->wq.rq_addr;
909 init_attr.rq_size = 1 << qhp->wq.rq_size_log2;
910 init_attr.mpaattrs = uP_RI_MPA_IETF_ENABLE |
911 qhp->attr.mpa_attr.recv_marker_enabled |
912 (qhp->attr.mpa_attr.xmit_marker_enabled << 1) |
913 (qhp->attr.mpa_attr.crc_enabled << 2);
914
915 init_attr.qpcaps = uP_RI_QP_RDMA_READ_ENABLE |
916 uP_RI_QP_RDMA_WRITE_ENABLE |
917 uP_RI_QP_BIND_ENABLE;
918 if (!qhp->ibqp.uobject)
919 init_attr.qpcaps |= uP_RI_QP_STAG0_ENABLE |
920 uP_RI_QP_FAST_REGISTER_ENABLE;
921
922 init_attr.tcp_emss = qhp->ep->emss;
923 init_attr.ord = qhp->attr.max_ord;
924 init_attr.ird = qhp->attr.max_ird;
925 init_attr.qp_dma_addr = qhp->wq.dma_addr;
926 init_attr.qp_dma_size = (1UL << qhp->wq.size_log2);
927 init_attr.rqe_count = iwch_rqes_posted(qhp);
928 init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0;
929 init_attr.chan = qhp->ep->l2t->smt_idx;
930 if (peer2peer) {
931 init_attr.rtr_type = RTR_READ;
932 if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator)
933 init_attr.ord = 1;
934 if (init_attr.ird == 0 && !qhp->attr.mpa_attr.initiator)
935 init_attr.ird = 1;
936 } else
937 init_attr.rtr_type = 0;
938 init_attr.irs = qhp->ep->rcv_seq;
939 PDBG("%s init_attr.rq_addr 0x%x init_attr.rq_size = %d "
940 "flags 0x%x qpcaps 0x%x\n", __func__,
941 init_attr.rq_addr, init_attr.rq_size,
942 init_attr.flags, init_attr.qpcaps);
943 ret = cxio_rdma_init(&rhp->rdev, &init_attr);
944 PDBG("%s ret %d\n", __func__, ret);
945 return ret;
946 }
947
948 int iwch_modify_qp(struct iwch_dev *rhp, struct iwch_qp *qhp,
949 enum iwch_qp_attr_mask mask,
950 struct iwch_qp_attributes *attrs,
951 int internal)
952 {
953 int ret = 0;
954 struct iwch_qp_attributes newattr = qhp->attr;
955 unsigned long flag;
956 int disconnect = 0;
957 int terminate = 0;
958 int abort = 0;
959 int free = 0;
960 struct iwch_ep *ep = NULL;
961
962 PDBG("%s qhp %p qpid 0x%x ep %p state %d -> %d\n", __func__,
963 qhp, qhp->wq.qpid, qhp->ep, qhp->attr.state,
964 (mask & IWCH_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
965
966 spin_lock_irqsave(&qhp->lock, flag);
967
968 /* Process attr changes if in IDLE */
969 if (mask & IWCH_QP_ATTR_VALID_MODIFY) {
970 if (qhp->attr.state != IWCH_QP_STATE_IDLE) {
971 ret = -EIO;
972 goto out;
973 }
974 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_READ)
975 newattr.enable_rdma_read = attrs->enable_rdma_read;
976 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_WRITE)
977 newattr.enable_rdma_write = attrs->enable_rdma_write;
978 if (mask & IWCH_QP_ATTR_ENABLE_RDMA_BIND)
979 newattr.enable_bind = attrs->enable_bind;
980 if (mask & IWCH_QP_ATTR_MAX_ORD) {
981 if (attrs->max_ord >
982 rhp->attr.max_rdma_read_qp_depth) {
983 ret = -EINVAL;
984 goto out;
985 }
986 newattr.max_ord = attrs->max_ord;
987 }
988 if (mask & IWCH_QP_ATTR_MAX_IRD) {
989 if (attrs->max_ird >
990 rhp->attr.max_rdma_reads_per_qp) {
991 ret = -EINVAL;
992 goto out;
993 }
994 newattr.max_ird = attrs->max_ird;
995 }
996 qhp->attr = newattr;
997 }
998
999 if (!(mask & IWCH_QP_ATTR_NEXT_STATE))
1000 goto out;
1001 if (qhp->attr.state == attrs->next_state)
1002 goto out;
1003
1004 switch (qhp->attr.state) {
1005 case IWCH_QP_STATE_IDLE:
1006 switch (attrs->next_state) {
1007 case IWCH_QP_STATE_RTS:
1008 if (!(mask & IWCH_QP_ATTR_LLP_STREAM_HANDLE)) {
1009 ret = -EINVAL;
1010 goto out;
1011 }
1012 if (!(mask & IWCH_QP_ATTR_MPA_ATTR)) {
1013 ret = -EINVAL;
1014 goto out;
1015 }
1016 qhp->attr.mpa_attr = attrs->mpa_attr;
1017 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1018 qhp->ep = qhp->attr.llp_stream_handle;
1019 qhp->attr.state = IWCH_QP_STATE_RTS;
1020
1021 /*
1022 * Ref the endpoint here and deref when we
1023 * disassociate the endpoint from the QP. This
1024 * happens in CLOSING->IDLE transition or *->ERROR
1025 * transition.
1026 */
1027 get_ep(&qhp->ep->com);
1028 spin_unlock_irqrestore(&qhp->lock, flag);
1029 ret = rdma_init(rhp, qhp, mask, attrs);
1030 spin_lock_irqsave(&qhp->lock, flag);
1031 if (ret)
1032 goto err;
1033 break;
1034 case IWCH_QP_STATE_ERROR:
1035 qhp->attr.state = IWCH_QP_STATE_ERROR;
1036 flush_qp(qhp);
1037 break;
1038 default:
1039 ret = -EINVAL;
1040 goto out;
1041 }
1042 break;
1043 case IWCH_QP_STATE_RTS:
1044 switch (attrs->next_state) {
1045 case IWCH_QP_STATE_CLOSING:
1046 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1047 qhp->attr.state = IWCH_QP_STATE_CLOSING;
1048 if (!internal) {
1049 abort=0;
1050 disconnect = 1;
1051 ep = qhp->ep;
1052 get_ep(&ep->com);
1053 }
1054 break;
1055 case IWCH_QP_STATE_TERMINATE:
1056 qhp->attr.state = IWCH_QP_STATE_TERMINATE;
1057 if (qhp->ibqp.uobject)
1058 cxio_set_wq_in_error(&qhp->wq);
1059 if (!internal)
1060 terminate = 1;
1061 break;
1062 case IWCH_QP_STATE_ERROR:
1063 qhp->attr.state = IWCH_QP_STATE_ERROR;
1064 if (!internal) {
1065 abort=1;
1066 disconnect = 1;
1067 ep = qhp->ep;
1068 get_ep(&ep->com);
1069 }
1070 goto err;
1071 break;
1072 default:
1073 ret = -EINVAL;
1074 goto out;
1075 }
1076 break;
1077 case IWCH_QP_STATE_CLOSING:
1078 if (!internal) {
1079 ret = -EINVAL;
1080 goto out;
1081 }
1082 switch (attrs->next_state) {
1083 case IWCH_QP_STATE_IDLE:
1084 flush_qp(qhp);
1085 qhp->attr.state = IWCH_QP_STATE_IDLE;
1086 qhp->attr.llp_stream_handle = NULL;
1087 put_ep(&qhp->ep->com);
1088 qhp->ep = NULL;
1089 wake_up(&qhp->wait);
1090 break;
1091 case IWCH_QP_STATE_ERROR:
1092 goto err;
1093 default:
1094 ret = -EINVAL;
1095 goto err;
1096 }
1097 break;
1098 case IWCH_QP_STATE_ERROR:
1099 if (attrs->next_state != IWCH_QP_STATE_IDLE) {
1100 ret = -EINVAL;
1101 goto out;
1102 }
1103
1104 if (!Q_EMPTY(qhp->wq.sq_rptr, qhp->wq.sq_wptr) ||
1105 !Q_EMPTY(qhp->wq.rq_rptr, qhp->wq.rq_wptr)) {
1106 ret = -EINVAL;
1107 goto out;
1108 }
1109 qhp->attr.state = IWCH_QP_STATE_IDLE;
1110 break;
1111 case IWCH_QP_STATE_TERMINATE:
1112 if (!internal) {
1113 ret = -EINVAL;
1114 goto out;
1115 }
1116 goto err;
1117 break;
1118 default:
1119 printk(KERN_ERR "%s in a bad state %d\n",
1120 __func__, qhp->attr.state);
1121 ret = -EINVAL;
1122 goto err;
1123 break;
1124 }
1125 goto out;
1126 err:
1127 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1128 qhp->wq.qpid);
1129
1130 /* disassociate the LLP connection */
1131 qhp->attr.llp_stream_handle = NULL;
1132 ep = qhp->ep;
1133 qhp->ep = NULL;
1134 qhp->attr.state = IWCH_QP_STATE_ERROR;
1135 free=1;
1136 wake_up(&qhp->wait);
1137 BUG_ON(!ep);
1138 flush_qp(qhp);
1139 out:
1140 spin_unlock_irqrestore(&qhp->lock, flag);
1141
1142 if (terminate)
1143 iwch_post_terminate(qhp, NULL);
1144
1145 /*
1146 * If disconnect is 1, then we need to initiate a disconnect
1147 * on the EP. This can be a normal close (RTS->CLOSING) or
1148 * an abnormal close (RTS/CLOSING->ERROR).
1149 */
1150 if (disconnect) {
1151 iwch_ep_disconnect(ep, abort, GFP_KERNEL);
1152 put_ep(&ep->com);
1153 }
1154
1155 /*
1156 * If free is 1, then we've disassociated the EP from the QP
1157 * and we need to dereference the EP.
1158 */
1159 if (free)
1160 put_ep(&ep->com);
1161
1162 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1163 return ret;
1164 }
Linux with added FPC-III support