drivers/infiniband/hw/ocrdma/ocrdma.h

   1 /* This file is part of the Emulex RoCE Device Driver for
   2  * RoCE (RDMA over Converged Ethernet) adapters.
   3  * Copyright (C) 2012-2015 Emulex. All rights reserved.
   4  * EMULEX and SLI are trademarks of Emulex.
   5  * www.emulex.com
   6  *
   7  * This software is available to you under a choice of one of two licenses.
   8  * You may choose to be licensed under the terms of the GNU General Public
   9  * License (GPL) Version 2, available from the file COPYING in the main
  10  * directory of this source tree, or the BSD license below:
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  *
  16  * - Redistributions of source code must retain the above copyright notice,
  17  *   this list of conditions and the following disclaimer.
  18  *
  19  * - Redistributions in binary form must reproduce the above copyright
  20  *   notice, this list of conditions and the following disclaimer in
  21  *   the documentation and/or other materials provided with the distribution.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  24  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  27  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  32  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  33  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  *
  35  * Contact Information:
  36  * linux-drivers@emulex.com
  37  *
  38  * Emulex
  39  * 3333 Susan Street
  40  * Costa Mesa, CA 92626
  41  */
  42
  43 #ifndef __OCRDMA_H__
  44 #define __OCRDMA_H__
  45
  46 #include <linux/mutex.h>
  47 #include <linux/list.h>
  48 #include <linux/spinlock.h>
  49 #include <linux/pci.h>
  50
  51 #include <rdma/ib_verbs.h>
  52 #include <rdma/ib_user_verbs.h>
  53 #include <rdma/ib_addr.h>
  54
  55 #include <be_roce.h>
  56 #include "ocrdma_sli.h"
  57
  58 #define OCRDMA_ROCE_DRV_VERSION "11.0.0.0"
  59
  60 #define OCRDMA_ROCE_DRV_DESC "Emulex OneConnect RoCE Driver"
  61 #define OCRDMA_NODE_DESC "Emulex OneConnect RoCE HCA"
  62
  63 #define OC_NAME_SH      OCRDMA_NODE_DESC "(Skyhawk)"
  64 #define OC_NAME_UNKNOWN OCRDMA_NODE_DESC "(Unknown)"
  65
  66 #define OC_SKH_DEVICE_PF 0x720
  67 #define OC_SKH_DEVICE_VF 0x728
  68 #define OCRDMA_MAX_AH 512
  69
  70 #define OCRDMA_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
  71
  72 #define convert_to_64bit(lo, hi) ((u64)hi << 32 | (u64)lo)
  73 #define EQ_INTR_PER_SEC_THRSH_HI 150000
  74 #define EQ_INTR_PER_SEC_THRSH_LOW 100000
  75 #define EQ_AIC_MAX_EQD 20
  76 #define EQ_AIC_MIN_EQD 0
  77
  78 void ocrdma_eqd_set_task(struct work_struct *work);
  79
  80 struct ocrdma_dev_attr {
  81         u8 fw_ver[32];
  82         u32 vendor_id;
  83         u32 device_id;
  84         u16 max_pd;
  85         u16 max_dpp_pds;
  86         u16 max_cq;
  87         u16 max_cqe;
  88         u16 max_qp;
  89         u16 max_wqe;
  90         u16 max_rqe;
  91         u16 max_srq;
  92         u32 max_inline_data;
  93         int max_send_sge;
  94         int max_recv_sge;
  95         int max_srq_sge;
  96         int max_rdma_sge;
  97         int max_mr;
  98         u64 max_mr_size;
  99         u32 max_num_mr_pbl;
 100         int max_mw;
 101         int max_fmr;
 102         int max_map_per_fmr;
 103         int max_pages_per_frmr;
 104         u16 max_ord_per_qp;
 105         u16 max_ird_per_qp;
 106
 107         int device_cap_flags;
 108         u8 cq_overflow_detect;
 109         u8 srq_supported;
 110
 111         u32 wqe_size;
 112         u32 rqe_size;
 113         u32 ird_page_size;
 114         u8 local_ca_ack_delay;
 115         u8 ird;
 116         u8 num_ird_pages;
 117 };
 118
 119 struct ocrdma_dma_mem {
 120         void *va;
 121         dma_addr_t pa;
 122         u32 size;
 123 };
 124
 125 struct ocrdma_pbl {
 126         void *va;
 127         dma_addr_t pa;
 128 };
 129
 130 struct ocrdma_queue_info {
 131         void *va;
 132         dma_addr_t dma;
 133         u32 size;
 134         u16 len;
 135         u16 entry_size;         /* Size of an element in the queue */
 136         u16 id;                 /* qid, where to ring the doorbell. */
 137         u16 head, tail;
 138         bool created;
 139 };
 140
 141 struct ocrdma_aic_obj {         /* Adaptive interrupt coalescing (AIC) info */
 142         u32 prev_eqd;
 143         u64 eq_intr_cnt;
 144         u64 prev_eq_intr_cnt;
 145 };
 146
 147 struct ocrdma_eq {
 148         struct ocrdma_queue_info q;
 149         u32 vector;
 150         int cq_cnt;
 151         struct ocrdma_dev *dev;
 152         char irq_name[32];
 153         struct ocrdma_aic_obj aic_obj;
 154 };
 155
 156 struct ocrdma_mq {
 157         struct ocrdma_queue_info sq;
 158         struct ocrdma_queue_info cq;
 159         bool rearm_cq;
 160 };
 161
 162 struct mqe_ctx {
 163         struct mutex lock; /* for serializing mailbox commands on MQ */
 164         wait_queue_head_t cmd_wait;
 165         u32 tag;
 166         u16 cqe_status;
 167         u16 ext_status;
 168         bool cmd_done;
 169         bool fw_error_state;
 170 };
 171
 172 struct ocrdma_hw_mr {
 173         u32 lkey;
 174         u8 fr_mr;
 175         u8 remote_atomic;
 176         u8 remote_rd;
 177         u8 remote_wr;
 178         u8 local_rd;
 179         u8 local_wr;
 180         u8 mw_bind;
 181         u8 rsvd;
 182         u64 len;
 183         struct ocrdma_pbl *pbl_table;
 184         u32 num_pbls;
 185         u32 num_pbes;
 186         u32 pbl_size;
 187         u32 pbe_size;
 188         u64 fbo;
 189         u64 va;
 190 };
 191
 192 struct ocrdma_mr {
 193         struct ib_mr ibmr;
 194         struct ib_umem *umem;
 195         struct ocrdma_hw_mr hwmr;
 196         u64 *pages;
 197         u32 npages;
 198 };
 199
 200 struct ocrdma_stats {
 201         u8 type;
 202         struct ocrdma_dev *dev;
 203 };
 204
 205 struct ocrdma_pd_resource_mgr {
 206         u32 pd_norm_start;
 207         u16 pd_norm_count;
 208         u16 pd_norm_thrsh;
 209         u16 max_normal_pd;
 210         u32 pd_dpp_start;
 211         u16 pd_dpp_count;
 212         u16 pd_dpp_thrsh;
 213         u16 max_dpp_pd;
 214         u16 dpp_page_index;
 215         unsigned long *pd_norm_bitmap;
 216         unsigned long *pd_dpp_bitmap;
 217         bool pd_prealloc_valid;
 218 };
 219
 220 struct stats_mem {
 221         struct ocrdma_mqe mqe;
 222         void *va;
 223         dma_addr_t pa;
 224         u32 size;
 225         char *debugfs_mem;
 226 };
 227
 228 struct phy_info {
 229         u16 auto_speeds_supported;
 230         u16 fixed_speeds_supported;
 231         u16 phy_type;
 232         u16 interface_type;
 233 };
 234
 235 enum ocrdma_flags {
 236         OCRDMA_FLAGS_LINK_STATUS_INIT = 0x01
 237 };
 238
 239 struct ocrdma_dev {
 240         struct ib_device ibdev;
 241         struct ocrdma_dev_attr attr;
 242
 243         struct mutex dev_lock; /* provides syncronise access to device data */
 244         spinlock_t flush_q_lock ____cacheline_aligned;
 245
 246         struct ocrdma_cq **cq_tbl;
 247         struct ocrdma_qp **qp_tbl;
 248
 249         struct ocrdma_eq *eq_tbl;
 250         int eq_cnt;
 251         struct delayed_work eqd_work;
 252         u16 base_eqid;
 253         u16 max_eq;
 254
 255         /* provided synchronization to sgid table for
 256          * updating gid entries triggered by notifier.
 257          */
 258         spinlock_t sgid_lock;
 259
 260         int gsi_qp_created;
 261         struct ocrdma_cq *gsi_sqcq;
 262         struct ocrdma_cq *gsi_rqcq;
 263
 264         struct {
 265                 struct ocrdma_av *va;
 266                 dma_addr_t pa;
 267                 u32 size;
 268                 u32 num_ah;
 269                 /* provide synchronization for av
 270                  * entry allocations.
 271                  */
 272                 spinlock_t lock;
 273                 u32 ahid;
 274                 struct ocrdma_pbl pbl;
 275         } av_tbl;
 276
 277         void *mbx_cmd;
 278         struct ocrdma_mq mq;
 279         struct mqe_ctx mqe_ctx;
 280
 281         struct be_dev_info nic_info;
 282         struct phy_info phy;
 283         char model_number[32];
 284         u32 hba_port_num;
 285
 286         struct list_head entry;
 287         int id;
 288         u64 *stag_arr;
 289         u8 sl; /* service level */
 290         bool pfc_state;
 291         atomic_t update_sl;
 292         u16 pvid;
 293         u32 asic_id;
 294         u32 flags;
 295
 296         ulong last_stats_time;
 297         struct mutex stats_lock; /* provide synch for debugfs operations */
 298         struct stats_mem stats_mem;
 299         struct ocrdma_stats rsrc_stats;
 300         struct ocrdma_stats rx_stats;
 301         struct ocrdma_stats wqe_stats;
 302         struct ocrdma_stats tx_stats;
 303         struct ocrdma_stats db_err_stats;
 304         struct ocrdma_stats tx_qp_err_stats;
 305         struct ocrdma_stats rx_qp_err_stats;
 306         struct ocrdma_stats tx_dbg_stats;
 307         struct ocrdma_stats rx_dbg_stats;
 308         struct ocrdma_stats driver_stats;
 309         struct ocrdma_stats reset_stats;
 310         struct dentry *dir;
 311         atomic_t async_err_stats[OCRDMA_MAX_ASYNC_ERRORS];
 312         atomic_t cqe_err_stats[OCRDMA_MAX_CQE_ERR];
 313         struct ocrdma_pd_resource_mgr *pd_mgr;
 314 };
 315
 316 struct ocrdma_cq {
 317         struct ib_cq ibcq;
 318         struct ocrdma_cqe *va;
 319         u32 phase;
 320         u32 getp;       /* pointer to pending wrs to
 321                          * return to stack, wrap arounds
 322                          * at max_hw_cqe
 323                          */
 324         u32 max_hw_cqe;
 325         bool phase_change;
 326         bool deferred_arm, deferred_sol;
 327         bool first_arm;
 328
 329         spinlock_t cq_lock ____cacheline_aligned; /* provide synchronization
 330                                                    * to cq polling
 331                                                    */
 332         /* syncronizes cq completion handler invoked from multiple context */
 333         spinlock_t comp_handler_lock ____cacheline_aligned;
 334         u16 id;
 335         u16 eqn;
 336
 337         struct ocrdma_ucontext *ucontext;
 338         dma_addr_t pa;
 339         u32 len;
 340         u32 cqe_cnt;
 341
 342         /* head of all qp's sq and rq for which cqes need to be flushed
 343          * by the software.
 344          */
 345         struct list_head sq_head, rq_head;
 346 };
 347
 348 struct ocrdma_pd {
 349         struct ib_pd ibpd;
 350         struct ocrdma_ucontext *uctx;
 351         u32 id;
 352         int num_dpp_qp;
 353         u32 dpp_page;
 354         bool dpp_enabled;
 355 };
 356
 357 struct ocrdma_ah {
 358         struct ib_ah ibah;
 359         struct ocrdma_av *av;
 360         u16 sgid_index;
 361         u32 id;
 362 };
 363
 364 struct ocrdma_qp_hwq_info {
 365         u8 *va;                 /* virtual address */
 366         u32 max_sges;
 367         u32 head, tail;
 368         u32 entry_size;
 369         u32 max_cnt;
 370         u32 max_wqe_idx;
 371         u16 dbid;               /* qid, where to ring the doorbell. */
 372         u32 len;
 373         dma_addr_t pa;
 374 };
 375
 376 struct ocrdma_srq {
 377         struct ib_srq ibsrq;
 378         u8 __iomem *db;
 379         struct ocrdma_qp_hwq_info rq;
 380         u64 *rqe_wr_id_tbl;
 381         u32 *idx_bit_fields;
 382         u32 bit_fields_len;
 383
 384         /* provide synchronization to multiple context(s) posting rqe */
 385         spinlock_t q_lock ____cacheline_aligned;
 386
 387         struct ocrdma_pd *pd;
 388         u32 id;
 389 };
 390
 391 struct ocrdma_qp {
 392         struct ib_qp ibqp;
 393
 394         u8 __iomem *sq_db;
 395         struct ocrdma_qp_hwq_info sq;
 396         struct {
 397                 uint64_t wrid;
 398                 uint16_t dpp_wqe_idx;
 399                 uint16_t dpp_wqe;
 400                 uint8_t  signaled;
 401                 uint8_t  rsvd[3];
 402         } *wqe_wr_id_tbl;
 403         u32 max_inline_data;
 404
 405         /* provide synchronization to multiple context(s) posting wqe, rqe */
 406         spinlock_t q_lock ____cacheline_aligned;
 407         struct ocrdma_cq *sq_cq;
 408         /* list maintained per CQ to flush SQ errors */
 409         struct list_head sq_entry;
 410
 411         u8 __iomem *rq_db;
 412         struct ocrdma_qp_hwq_info rq;
 413         u64 *rqe_wr_id_tbl;
 414         struct ocrdma_cq *rq_cq;
 415         struct ocrdma_srq *srq;
 416         /* list maintained per CQ to flush RQ errors */
 417         struct list_head rq_entry;
 418
 419         enum ocrdma_qp_state state;     /*  QP state */
 420         int cap_flags;
 421         u32 max_ord, max_ird;
 422
 423         u32 id;
 424         struct ocrdma_pd *pd;
 425
 426         enum ib_qp_type qp_type;
 427
 428         int sgid_idx;
 429         u32 qkey;
 430         bool dpp_enabled;
 431         u8 *ird_q_va;
 432         bool signaled;
 433 };
 434
 435 struct ocrdma_ucontext {
 436         struct ib_ucontext ibucontext;
 437
 438         struct list_head mm_head;
 439         struct mutex mm_list_lock; /* protects list entries of mm type */
 440         struct ocrdma_pd *cntxt_pd;
 441         int pd_in_use;
 442
 443         struct {
 444                 u32 *va;
 445                 dma_addr_t pa;
 446                 u32 len;
 447         } ah_tbl;
 448 };
 449
 450 struct ocrdma_mm {
 451         struct {
 452                 u64 phy_addr;
 453                 unsigned long len;
 454         } key;
 455         struct list_head entry;
 456 };
 457
 458 static inline struct ocrdma_dev *get_ocrdma_dev(struct ib_device *ibdev)
 459 {
 460         return container_of(ibdev, struct ocrdma_dev, ibdev);
 461 }
 462
 463 static inline struct ocrdma_ucontext *get_ocrdma_ucontext(struct ib_ucontext
 464                                                           *ibucontext)
 465 {
 466         return container_of(ibucontext, struct ocrdma_ucontext, ibucontext);
 467 }
 468
 469 static inline struct ocrdma_pd *get_ocrdma_pd(struct ib_pd *ibpd)
 470 {
 471         return container_of(ibpd, struct ocrdma_pd, ibpd);
 472 }
 473
 474 static inline struct ocrdma_cq *get_ocrdma_cq(struct ib_cq *ibcq)
 475 {
 476         return container_of(ibcq, struct ocrdma_cq, ibcq);
 477 }
 478
 479 static inline struct ocrdma_qp *get_ocrdma_qp(struct ib_qp *ibqp)
 480 {
 481         return container_of(ibqp, struct ocrdma_qp, ibqp);
 482 }
 483
 484 static inline struct ocrdma_mr *get_ocrdma_mr(struct ib_mr *ibmr)
 485 {
 486         return container_of(ibmr, struct ocrdma_mr, ibmr);
 487 }
 488
 489 static inline struct ocrdma_ah *get_ocrdma_ah(struct ib_ah *ibah)
 490 {
 491         return container_of(ibah, struct ocrdma_ah, ibah);
 492 }
 493
 494 static inline struct ocrdma_srq *get_ocrdma_srq(struct ib_srq *ibsrq)
 495 {
 496         return container_of(ibsrq, struct ocrdma_srq, ibsrq);
 497 }
 498
 499 static inline int is_cqe_valid(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe)
 500 {
 501         int cqe_valid;
 502         cqe_valid = le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID;
 503         return (cqe_valid == cq->phase);
 504 }
 505
 506 static inline int is_cqe_for_sq(struct ocrdma_cqe *cqe)
 507 {
 508         return (le32_to_cpu(cqe->flags_status_srcqpn) &
 509                 OCRDMA_CQE_QTYPE) ? 0 : 1;
 510 }
 511
 512 static inline int is_cqe_invalidated(struct ocrdma_cqe *cqe)
 513 {
 514         return (le32_to_cpu(cqe->flags_status_srcqpn) &
 515                 OCRDMA_CQE_INVALIDATE) ? 1 : 0;
 516 }
 517
 518 static inline int is_cqe_imm(struct ocrdma_cqe *cqe)
 519 {
 520         return (le32_to_cpu(cqe->flags_status_srcqpn) &
 521                 OCRDMA_CQE_IMM) ? 1 : 0;
 522 }
 523
 524 static inline int is_cqe_wr_imm(struct ocrdma_cqe *cqe)
 525 {
 526         return (le32_to_cpu(cqe->flags_status_srcqpn) &
 527                 OCRDMA_CQE_WRITE_IMM) ? 1 : 0;
 528 }
 529
 530 static inline int ocrdma_resolve_dmac(struct ocrdma_dev *dev,
 531                 struct ib_ah_attr *ah_attr, u8 *mac_addr)
 532 {
 533         struct in6_addr in6;
 534
 535         memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6));
 536         if (rdma_is_multicast_addr(&in6))
 537                 rdma_get_mcast_mac(&in6, mac_addr);
 538         else if (rdma_link_local_addr(&in6))
 539                 rdma_get_ll_mac(&in6, mac_addr);
 540         else
 541                 memcpy(mac_addr, ah_attr->dmac, ETH_ALEN);
 542         return 0;
 543 }
 544
 545 static inline char *hca_name(struct ocrdma_dev *dev)
 546 {
 547         switch (dev->nic_info.pdev->device) {
 548         case OC_SKH_DEVICE_PF:
 549         case OC_SKH_DEVICE_VF:
 550                 return OC_NAME_SH;
 551         default:
 552                 return OC_NAME_UNKNOWN;
 553         }
 554 }
 555
 556 static inline int ocrdma_get_eq_table_index(struct ocrdma_dev *dev,
 557                 int eqid)
 558 {
 559         int indx;
 560
 561         for (indx = 0; indx < dev->eq_cnt; indx++) {
 562                 if (dev->eq_tbl[indx].q.id == eqid)
 563                         return indx;
 564         }
 565
 566         return -EINVAL;
 567 }
 568
 569 static inline u8 ocrdma_get_asic_type(struct ocrdma_dev *dev)
 570 {
 571         if (dev->nic_info.dev_family == 0xF && !dev->asic_id) {
 572                 pci_read_config_dword(
 573                         dev->nic_info.pdev,
 574                         OCRDMA_SLI_ASIC_ID_OFFSET, &dev->asic_id);
 575         }
 576
 577         return (dev->asic_id & OCRDMA_SLI_ASIC_GEN_NUM_MASK) >>
 578                                 OCRDMA_SLI_ASIC_GEN_NUM_SHIFT;
 579 }
 580
 581 static inline u8 ocrdma_get_pfc_prio(u8 *pfc, u8 prio)
 582 {
 583         return *(pfc + prio);
 584 }
 585
 586 static inline u8 ocrdma_get_app_prio(u8 *app_prio, u8 prio)
 587 {
 588         return *(app_prio + prio);
 589 }
 590
 591 static inline u8 ocrdma_is_enabled_and_synced(u32 state)
 592 {       /* May also be used to interpret TC-state, QCN-state
 593          * Appl-state and Logical-link-state in future.
 594          */
 595         return (state & OCRDMA_STATE_FLAG_ENABLED) &&
 596                 (state & OCRDMA_STATE_FLAG_SYNC);
 597 }
 598
 599 static inline u8 ocrdma_get_ae_link_state(u32 ae_state)
 600 {
 601         return ((ae_state & OCRDMA_AE_LSC_LS_MASK) >> OCRDMA_AE_LSC_LS_SHIFT);
 602 }
 603
 604 #endif