| blob | 99dd6fdf06d7b44bcea2f0fb28b90edf54aefcc0 |
1 /* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
5 * www.emulex.com
6 *
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * Contact Information:
36 * linux-drivers@emulex.com
37 *
38 * Emulex
39 * 3333 Susan Street
40 * Costa Mesa, CA 92626
41 */
43 #ifndef __OCRDMA_SLI_H__
44 #define __OCRDMA_SLI_H__
49 };
55 };
57 #define OCRDMA_SUBSYS_ROCE 10
96 OCRDMA_CMD_MAX
97 };
99 #define OCRDMA_SUBSYS_COMMON 1
114 };
120 };
122 #define OCRDMA_MAX_SGID 16
124 #define OCRDMA_MAX_QP 2048
125 #define OCRDMA_MAX_CQ 2048
126 #define OCRDMA_MAX_STAG 16384
141 };
143 #define OCRDMA_ROUDP_FLAGS_SHIFT 0x03
147 /* qid #2 msbits at 12-11 */
148 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1
150 /* Rearm bit */
152 /* solicited bit */
159 /* Clear the interrupt for this eq */
161 /* Must be 1 */
163 /* Number of event entries processed */
165 /* Rearm bit */
169 /* Number of entries posted */
172 #define OCRDMA_MIN_HPAGE_SIZE 4096
174 #define OCRDMA_MIN_Q_PAGE_SIZE 4096
175 #define OCRDMA_MAX_Q_PAGES 8
177 #define OCRDMA_SLI_ASIC_ID_OFFSET 0x9C
178 #define OCRDMA_SLI_ASIC_REV_MASK 0x000000FF
179 #define OCRDMA_SLI_ASIC_GEN_NUM_MASK 0x0000FF00
180 #define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT 0x08
181 /*
182 # 0: 4K Bytes
183 # 1: 8K Bytes
184 # 2: 16K Bytes
185 # 3: 32K Bytes
186 # 4: 64K Bytes
187 # 5: 128K Bytes
188 # 6: 256K Bytes
189 # 7: 512K Bytes
190 */
191 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT 8
192 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
194 #define MAX_OCRDMA_QP_PAGES 8
195 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
197 #define OCRDMA_CREATE_CQ_MAX_PAGES 4
198 #define OCRDMA_DPP_CQE_SIZE 4
200 #define OCRDMA_GEN2_MAX_CQE 1024
201 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
202 #define OCRDMA_GEN2_WQE_SIZE 256
203 #define OCRDMA_MAX_CQE 4095
204 #define OCRDMA_CQ_PAGE_SIZE 16384
205 #define OCRDMA_WQE_SIZE 128
206 #define OCRDMA_WQE_STRIDE 8
207 #define OCRDMA_WQE_ALIGN_BYTES 16
209 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
216 };
218 /* mailbox cmd header */
220 u32 subsys_op;
222 u32 cmd_len;
223 u32 rsvd_version;
224 };
236 };
238 /* mailbox cmd response */
240 u32 subsys_op;
241 u32 status;
242 u32 rsp_len;
243 u32 add_rsp_len;
244 };
249 };
252 u32 pa_lo;
253 u32 pa_hi;
254 u32 len;
255 };
264 };
267 u32 spcl_sge_cnt_emb;
268 u32 pyld_len;
269 u32 tag_lo;
270 u32 tag_hi;
271 u32 rsvd3;
272 };
277 };
289 };
291 #define OCRDMA_EQ_LEN 4096
292 #define OCRDMA_MQ_CQ_LEN 256
293 #define OCRDMA_MQ_LEN 128
295 #define PAGE_SHIFT_4K 12
296 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
298 /* Returns number of pages spanned by the data starting at the given addr */
299 #define PAGES_4K_SPANNED(_address, size) \
300 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
301 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
305 u32 id;
306 };
309 u32 lo;
310 u32 hi;
311 };
313 #define MAX_OCRDMA_EQ_PAGES 8
316 u32 num_pages;
317 u32 valid;
318 u32 cnt;
319 u32 delay;
320 u32 rsvd;
322 };
328 };
332 u32 vector_eqid;
333 };
335 #define OCRDMA_EQ_MINOR_OTHER 0x1
338 u32 eq_id;
339 u32 phase;
340 u32 delay_multiplier;
341 };
345 u32 num_eq;
352 };
357 u32 rsvd0;
373 };
376 u32 status;
377 u32 tag_lo;
378 u32 tag_hi;
379 u32 valid_ae_cmpl_cons;
380 };
391 OCRDMA_AE_MCQE_EVENT_TYPE_MASK =
394 OCRDMA_AE_MCQE_EVENT_CODE_MASK =
396 };
398 u32 qpvalid_qpid;
399 u32 cqvalid_cqid;
400 u32 evt_tag;
401 u32 valid_ae_event;
402 };
409 };
412 u32 tag_enabled;
413 u32 event_tag;
414 u32 rsvd1;
415 u32 rsvd2;
416 };
421 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
425 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
428 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
433 };
436 u32 req_id;
437 u32 w1;
438 u32 w2;
439 u32 valid_ae_event;
440 };
447 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
451 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
454 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
459 };
462 u32 qp_id_state;
463 u32 w1;
464 u32 w2;
465 u32 valid_ae_event;
466 };
472 };
478 };
492 OCRDMA_MAX_ASYNC_ERRORS
493 };
496 u32 speed_state_ptn;
497 u32 qos_reason_falut;
498 u32 evt_tag;
499 u32 valid_ae_event;
500 };
506 OCRDMA_AE_LSC_PT_SHIFT),
509 OCRDMA_AE_LSC_LS_SHIFT),
512 OCRDMA_AE_LSC_LD_SHIFT),
515 OCRDMA_AE_LSC_PPS_SHIFT),
519 OCRDMA_AE_LSC_ER_SHIFT),
522 OCRDMA_AE_LSC_QOS_SHIFT)
523 };
531 };
533 /* mailbox command request and responses */
541 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
545 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
548 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
554 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT,
560 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
564 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
567 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
570 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
574 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
577 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
581 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
584 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
588 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
592 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
595 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,
599 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
602 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
606 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
609 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
610 };
615 u32 qp_srq_cq_ird_ord;
616 u32 max_pd_ca_ack_delay;
617 u32 max_write_send_sge;
618 u32 max_ird_ord_per_qp;
619 u32 max_shared_ird_ord;
620 u32 max_mr;
621 u32 max_mr_size_hi;
622 u32 max_mr_size_lo;
623 u32 max_num_mr_pbl;
624 u32 max_mw;
625 u32 max_fmr;
626 u32 max_pages_per_frmr;
627 u32 max_mcast_group;
628 u32 max_mcast_qp_attach;
629 u32 max_total_mcast_qp_attach;
630 u32 wqe_rqe_stride_max_dpp_cqs;
631 u32 max_srq_rpir_qps;
632 u32 max_dpp_pds_credits;
633 u32 max_dpp_credits_pds_per_pd;
634 u32 max_wqes_rqes_per_q;
635 u32 max_cq_cqes_per_cq;
636 u32 max_srq_rqe_sge;
637 };
644 };
650 u32 config_num;
651 u32 asic_revision;
652 u32 phy_port;
653 u32 fn_mode;
655 u32 mode;
656 u32 nic_wqid_base;
657 u32 nic_wq_tot;
658 u32 prot_wqid_base;
659 u32 prot_wq_tot;
660 u32 prot_rqid_base;
661 u32 prot_rqid_tot;
664 u32 fn_capabilities;
665 u32 rsvd1;
666 u32 rsvd2;
667 u32 base_eqid;
668 u32 max_eq;
670 };
674 };
686 };
692 u32 ityp_ptyp;
693 u32 misc_params;
694 u32 ftrdtl_exphydtl;
695 u32 fspeed_aspeed;
697 };
706 };
727 };
733 u32 pflt_pps_ld_pnum;
734 u32 qos_lsp;
735 u32 res_lnk_st;
736 };
748 };
765 };
777 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
778 OCRDMA_CREATE_CQ_FLAGS_NODELAY
779 };
783 u32 pgsz_pgcnt;
784 u32 ev_cnt_flags;
785 u32 eqn;
786 u32 pdid_cqecnt;
787 u32 rsvd6;
789 };
794 };
798 };
802 };
806 u32 cq_id;
807 };
812 };
820 };
824 u32 cqid_pages;
825 u32 async_event_bitmap;
826 u32 async_cqid_ringsize;
827 u32 valid;
828 u32 async_cqid_valid;
829 u32 rsvd;
831 };
835 u32 id;
836 };
843 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
844 };
850 u32 bypass_flush_qid;
851 };
856 };
862 };
876 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
882 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
904 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
910 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
916 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
922 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
928 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
934 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
935 };
940 };
942 #define MAX_OCRDMA_IRD_PAGES 4
950 };
961 };
967 u32 type_pgsz_pdn;
968 u32 max_wqe_rqe;
969 u32 max_sge_send_write;
970 u32 max_sge_recv_flags;
971 u32 max_ord_ird;
972 u32 num_wq_rq_pages;
973 u32 wqe_rqe_size;
974 u32 wq_rq_cqid;
977 u32 dpp_credits_cqid;
978 u32 rpir_lkey;
980 };
990 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
996 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
1000 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
1006 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
1012 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
1017 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
1020 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
1021 };
1027 u32 qp_id;
1028 u32 max_wqe_rqe;
1029 u32 max_sge_send_write;
1030 u32 max_sge_recv;
1031 u32 max_ord_ird;
1032 u32 sq_rq_id;
1033 u32 dpp_response;
1034 };
1039 u32 qp_id;
1040 };
1045 };
1083 };
1093 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
1099 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
1112 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
1118 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
1124 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
1130 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
1136 OCRDMA_QP_PARAMS_TCLASS_SHIFT,
1142 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
1145 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
1151 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
1157 OCRDMA_QP_PARAMS_SL_SHIFT,
1160 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
1163 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
1169 OCRDMA_QP_PARAMS_VLAN_SHIFT
1170 };
1173 u32 id;
1174 u32 max_wqe_rqe;
1175 u32 max_sge_send_write;
1176 u32 max_sge_recv_flags;
1177 u32 max_ord_ird;
1178 u32 wq_rq_cqid;
1179 u32 hop_lmt_rq_psn;
1180 u32 tclass_sq_psn;
1181 u32 ack_to_rnr_rtc_dest_qpn;
1182 u32 path_mtu_pkey_indx;
1183 u32 rnt_rc_sl_fl;
1186 u32 dmac_b0_to_b3;
1187 u32 vlan_dmac_b4_to_b5;
1188 u32 qkey;
1189 };
1197 u32 flags;
1198 u32 rdma_flags;
1199 u32 num_outstanding_atomic_rd;
1200 };
1207 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1213 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1214 };
1220 u32 max_wqe_rqe;
1221 u32 max_ord_ird;
1222 };
1228 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0
1229 #define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF
1230 u32 qp_id;
1231 };
1237 u32 dpp_credits_cqid;
1238 u32 rbq_id;
1239 };
1246 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1251 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1257 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1258 };
1264 u32 pgsz_pdid;
1265 u32 max_sge_rqe;
1266 u32 pages_rqe_sz;
1268 };
1278 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1279 };
1285 u32 id;
1286 u32 max_sge_rqe_allocated;
1287 };
1297 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1298 };
1304 u32 id;
1305 u32 limit_max_rqe;
1306 };
1311 };
1317 u32 id;
1318 };
1325 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1331 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1332 };
1338 u32 max_rqe_pdid;
1339 u32 srq_lmt_max_sge;
1340 };
1345 };
1351 u32 id;
1352 };
1357 };
1362 u32 enable_dpp_rsvd;
1363 };
1369 };
1374 u32 dpp_page_pdid;
1375 };
1380 u32 id;
1381 };
1386 };
1391 u32 enable_dpp_rsvd;
1392 u32 pd_count;
1393 };
1398 u32 dpp_page_pdid;
1399 u32 pd_count;
1400 };
1404 };
1409 u32 start_pd_id;
1410 u32 pd_count;
1411 };
1416 u32 rsvd;
1417 };
1422 };
1444 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1445 };
1451 u32 pdid;
1452 u32 pbl_sz_flags;
1453 };
1459 u32 lrkey;
1460 u32 num_pbl_rsvd;
1461 };
1467 u32 lkey;
1468 u32 rsvd_frmr;
1469 };
1474 };
1476 #define MAX_OCRDMA_NSMR_PBL (u32)22
1477 #define MAX_OCRDMA_PBL_SIZE 65536
1478 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1485 OCRDMA_REG_NSMR_LRKEY_SHIFT,
1491 OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1497 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1514 };
1520 u32 fr_mr;
1521 u32 num_pbl_pdid;
1522 u32 flags_hpage_pbe_sz;
1523 u32 totlen_low;
1524 u32 totlen_high;
1525 u32 fbo_low;
1526 u32 fbo_high;
1527 u32 va_loaddr;
1528 u32 va_hiaddr;
1530 };
1537 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1541 };
1547 u32 lrkey;
1548 u32 num_pbl_offset;
1549 u32 last;
1552 };
1555 u32 pa_hi;
1556 u32 pa_lo;
1557 };
1562 };
1567 u32 lrkey;
1568 u32 num_pbl;
1569 };
1576 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1580 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1581 };
1587 u32 lrkey_key_index;
1588 u32 num_pbl;
1589 };
1594 };
1600 u32 pdid;
1601 };
1606 };
1612 u32 lrkey_index;
1613 };
1618 u32 qp_id;
1620 u32 mac_b0_to_b3;
1621 u32 vlan_mac_b4_to_b5;
1622 };
1627 };
1632 u32 qp_id;
1634 u32 mac_b0_to_b3;
1635 u32 vlan_mac_b4_to_b5;
1636 };
1641 };
1646 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1650 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1654 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1655 };
1657 #define OCRDMA_AH_TBL_PAGES 8
1663 u32 ah_conf;
1665 };
1670 u32 ahid;
1671 };
1676 u32 ahid;
1677 };
1682 };
1692 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1693 };
1698 };
1701 u32 id_valid;
1702 };
1706 OCRDMA_CQE_LOC_LEN_ERR,
1707 OCRDMA_CQE_LOC_QP_OP_ERR,
1708 OCRDMA_CQE_LOC_EEC_OP_ERR,
1709 OCRDMA_CQE_LOC_PROT_ERR,
1710 OCRDMA_CQE_WR_FLUSH_ERR,
1711 OCRDMA_CQE_MW_BIND_ERR,
1712 OCRDMA_CQE_BAD_RESP_ERR,
1713 OCRDMA_CQE_LOC_ACCESS_ERR,
1714 OCRDMA_CQE_REM_INV_REQ_ERR,
1715 OCRDMA_CQE_REM_ACCESS_ERR,
1716 OCRDMA_CQE_REM_OP_ERR,
1717 OCRDMA_CQE_RETRY_EXC_ERR,
1718 OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1719 OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1720 OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1721 OCRDMA_CQE_REM_ABORT_ERR,
1722 OCRDMA_CQE_INV_EECN_ERR,
1723 OCRDMA_CQE_INV_EEC_STATE_ERR,
1724 OCRDMA_CQE_FATAL_ERR,
1725 OCRDMA_CQE_RESP_TIMEOUT_ERR,
1726 OCRDMA_CQE_GENERAL_ERR,
1728 OCRDMA_MAX_CQE_ERR
1729 };
1732 /* w0 */
1736 /* w1 */
1741 /* w2 */
1748 /* w3 */
1761 };
1765 /* w0 to w2 */
1767 u32 wqeidx;
1768 u32 bytes_xfered;
1769 u32 qpn;
1772 u32 lkey_immdt;
1773 u32 rxlen;
1774 u32 buftag_qpn;
1777 u32 lkey_immdt;
1778 u32 rxlen_pkey;
1779 u32 buftag_qpn;
1782 u32 word_0;
1783 u32 word_1;
1784 u32 qpn;
1786 };
1788 };
1791 u32 addr_hi;
1792 u32 addr_lo;
1793 u32 lrkey;
1794 u32 len;
1795 };
1806 /* Stag flags */
1811 };
1825 };
1830 };
1844 };
1846 /* header WQE for all the SQ and RQ operations */
1848 u32 cw;
1850 u32 rsvd_tag;
1851 u32 rsvd_lkey_flags;
1852 };
1854 u32 immdt;
1855 u32 lkey;
1856 };
1857 u32 total_len;
1858 };
1861 u32 rsvd_dest_qpn;
1862 u32 qkey;
1863 u32 rsvd_ahid;
1864 u32 rsvd;
1865 };
1867 /* extended wqe followed by hdr_wqe for Fast Memory register */
1869 u32 va_hi;
1870 u32 va_lo;
1871 u32 fbo_hi;
1872 u32 fbo_lo;
1873 u32 size_sge;
1874 u32 num_sges;
1875 u32 rsvd;
1876 u32 rsvd2;
1877 };
1882 __be16 eth_type;
1888 __be16 eth_type;
1889 __be16 vlan_tag;
1890 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1891 __be16 roce_eth_type;
1895 __be32 tclass_flow;
1896 __be32 pdid_hoplimit;
1899 u16 rsvd;
1902 #define OCRDMA_AV_VALID BIT(7)
1903 #define OCRDMA_AV_VLAN_VALID BIT(1)
1908 u32 valid;
1912 u32 dpp_pds;
1913 u32 non_dpp_pds;
1914 u32 rc_dpp_qps;
1915 u32 uc_dpp_qps;
1916 u32 ud_dpp_qps;
1917 u32 rc_non_dpp_qps;
1918 u32 rsvd;
1919 u32 uc_non_dpp_qps;
1920 u32 ud_non_dpp_qps;
1921 u32 rsvd1;
1922 u32 srqs;
1923 u32 rbqs;
1924 u32 r64K_nsmr;
1925 u32 r64K_to_2M_nsmr;
1926 u32 r2M_to_44M_nsmr;
1927 u32 r44M_to_1G_nsmr;
1928 u32 r1G_to_4G_nsmr;
1929 u32 nsmr_count_4G_to_32G;
1930 u32 r32G_to_64G_nsmr;
1931 u32 r64G_to_128G_nsmr;
1932 u32 r128G_to_higher_nsmr;
1933 u32 embedded_nsmr;
1934 u32 frmr;
1935 u32 prefetch_qps;
1936 u32 ondemand_qps;
1937 u32 phy_mr;
1938 u32 mw;
1940 };
1943 u32 sq_doorbell_errors;
1944 u32 cq_doorbell_errors;
1945 u32 rq_srq_doorbell_errors;
1946 u32 cq_overflow_errors;
1948 };
1951 u32 large_send_rc_wqes_lo;
1952 u32 large_send_rc_wqes_hi;
1953 u32 large_write_rc_wqes_lo;
1954 u32 large_write_rc_wqes_hi;
1956 u32 read_wqes_lo;
1957 u32 read_wqes_hi;
1958 u32 frmr_wqes_lo;
1959 u32 frmr_wqes_hi;
1960 u32 mw_bind_wqes_lo;
1961 u32 mw_bind_wqes_hi;
1962 u32 invalidate_wqes_lo;
1963 u32 invalidate_wqes_hi;
1965 u32 dpp_wqe_drops;
1967 };
1970 u32 send_pkts_lo;
1971 u32 send_pkts_hi;
1972 u32 write_pkts_lo;
1973 u32 write_pkts_hi;
1974 u32 read_pkts_lo;
1975 u32 read_pkts_hi;
1976 u32 read_rsp_pkts_lo;
1977 u32 read_rsp_pkts_hi;
1978 u32 ack_pkts_lo;
1979 u32 ack_pkts_hi;
1980 u32 send_bytes_lo;
1981 u32 send_bytes_hi;
1982 u32 write_bytes_lo;
1983 u32 write_bytes_hi;
1984 u32 read_req_bytes_lo;
1985 u32 read_req_bytes_hi;
1986 u32 read_rsp_bytes_lo;
1987 u32 read_rsp_bytes_hi;
1988 u32 ack_timeouts;
1990 };
1994 u32 local_length_errors;
1995 u32 local_protection_errors;
1996 u32 local_qp_operation_errors;
1997 u32 retry_count_exceeded_errors;
1998 u32 rnr_retry_count_exceeded_errors;
2000 };
2003 u32 roce_frame_bytes_lo;
2004 u32 roce_frame_bytes_hi;
2005 u32 roce_frame_icrc_drops;
2006 u32 roce_frame_payload_len_drops;
2007 u32 ud_drops;
2008 u32 qp1_drops;
2009 u32 psn_error_request_packets;
2010 u32 psn_error_resp_packets;
2011 u32 rnr_nak_timeouts;
2012 u32 rnr_nak_receives;
2013 u32 roce_frame_rxmt_drops;
2014 u32 nak_count_psn_sequence_errors;
2015 u32 rc_drop_count_lookup_errors;
2016 u32 rq_rnr_naks;
2017 u32 srq_rnr_naks;
2018 u32 roce_frames_lo;
2019 u32 roce_frames_hi;
2020 u32 rsvd;
2021 };
2024 u32 nak_invalid_requst_errors;
2025 u32 nak_remote_operation_errors;
2026 u32 nak_count_remote_access_errors;
2027 u32 local_length_errors;
2028 u32 local_protection_errors;
2029 u32 local_qp_operation_errors;
2031 };
2035 };
2039 };
2043 u8 reset_stats;
2108 };
2113 u32 supported_modes;
2114 u32 rsvd_eprom_verhi_verlo;
2115 u32 mbx_ds_ver;
2116 u32 epfw_ds_ver;
2118 u32 default_extended_timeout;
2128 u32 functionalities_supported;
2129 u32 guid0_asicrev_cdblen;
2131 u32 portcnt_guid15;
2132 u32 mfuncdev_iscsi_ldtout;
2133 u32 ptpnum_maxdoms_hbast_cv;
2134 u32 firmware_post_status;
2136 u32 res_asicgen_iscsi_feaures;
2138 };
2142 u32 pci_did_vid;
2143 u32 pci_ssid_svid;
2144 u32 ityp_fnum_devnum_bnum;
2145 u32 uid_hi;
2146 u32 uid_lo;
2147 u32 res_nnetfil;
2149 };
2154 };
2156 #define OCRDMA_SUBSYS_DCBX 0x10
2160 };
2166 };
2170 };
2175 };
2183 };
2192 };
2200 };
2203 u32 valid_proto_app;
2204 u32 oui;
2206 };
2209 u32 tcv_aev_opv_st;
2210 u32 tc_state;
2211 u32 pfc_state;
2212 u32 qcn_state;
2213 u32 appl_state;
2214 u32 ll_state;
2219 };
2223 u32 param_type;