2 * Sony CXD2820R demodulator driver
4 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "cxd2820r_priv.h"
24 int cxd2820r_set_frontend_t(struct dvb_frontend
*fe
)
26 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
27 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
32 u8 bw_params1
[][5] = {
33 { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
34 { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
35 { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
37 u8 bw_params2
[][2] = {
38 { 0x1f, 0xdc }, /* 6 MHz */
39 { 0x12, 0xf8 }, /* 7 MHz */
40 { 0x01, 0xe0 }, /* 8 MHz */
42 struct reg_val_mask tab
[] = {
43 { 0x00080, 0x00, 0xff },
44 { 0x00081, 0x03, 0xff },
45 { 0x00085, 0x07, 0xff },
46 { 0x00088, 0x01, 0xff },
48 { 0x00070, priv
->cfg
.ts_mode
, 0xff },
49 { 0x00071, !priv
->cfg
.ts_clock_inv
<< 4, 0x10 },
50 { 0x000cb, priv
->cfg
.if_agc_polarity
<< 6, 0x40 },
51 { 0x000a5, 0x00, 0x01 },
52 { 0x00082, 0x20, 0x60 },
53 { 0x000c2, 0xc3, 0xff },
54 { 0x0016a, 0x50, 0xff },
55 { 0x00427, 0x41, 0xff },
58 dev_dbg(&priv
->i2c
->dev
, "%s: frequency=%d bandwidth_hz=%d\n", __func__
,
59 c
->frequency
, c
->bandwidth_hz
);
61 switch (c
->bandwidth_hz
) {
79 if (fe
->ops
.tuner_ops
.set_params
)
80 fe
->ops
.tuner_ops
.set_params(fe
);
82 if (priv
->delivery_system
!= SYS_DVBT
) {
83 for (i
= 0; i
< ARRAY_SIZE(tab
); i
++) {
84 ret
= cxd2820r_wr_reg_mask(priv
, tab
[i
].reg
,
85 tab
[i
].val
, tab
[i
].mask
);
91 priv
->delivery_system
= SYS_DVBT
;
92 priv
->ber_running
= false; /* tune stops BER counter */
94 /* program IF frequency */
95 if (fe
->ops
.tuner_ops
.get_if_frequency
) {
96 ret
= fe
->ops
.tuner_ops
.get_if_frequency(fe
, &if_freq
);
102 dev_dbg(&priv
->i2c
->dev
, "%s: if_freq=%d\n", __func__
, if_freq
);
104 num
= if_freq
/ 1000; /* Hz => kHz */
106 if_ctl
= DIV_ROUND_CLOSEST_ULL(num
, 41000);
107 buf
[0] = ((if_ctl
>> 16) & 0xff);
108 buf
[1] = ((if_ctl
>> 8) & 0xff);
109 buf
[2] = ((if_ctl
>> 0) & 0xff);
111 ret
= cxd2820r_wr_regs(priv
, 0x000b6, buf
, 3);
115 ret
= cxd2820r_wr_regs(priv
, 0x0009f, bw_params1
[bw_i
], 5);
119 ret
= cxd2820r_wr_reg_mask(priv
, 0x000d7, bw_param
<< 6, 0xc0);
123 ret
= cxd2820r_wr_regs(priv
, 0x000d9, bw_params2
[bw_i
], 2);
127 ret
= cxd2820r_wr_reg(priv
, 0x000ff, 0x08);
131 ret
= cxd2820r_wr_reg(priv
, 0x000fe, 0x01);
137 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
141 int cxd2820r_get_frontend_t(struct dvb_frontend
*fe
)
143 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
144 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
148 ret
= cxd2820r_rd_regs(priv
, 0x0002f, buf
, sizeof(buf
));
152 switch ((buf
[0] >> 6) & 0x03) {
154 c
->modulation
= QPSK
;
157 c
->modulation
= QAM_16
;
160 c
->modulation
= QAM_64
;
164 switch ((buf
[1] >> 1) & 0x03) {
166 c
->transmission_mode
= TRANSMISSION_MODE_2K
;
169 c
->transmission_mode
= TRANSMISSION_MODE_8K
;
173 switch ((buf
[1] >> 3) & 0x03) {
175 c
->guard_interval
= GUARD_INTERVAL_1_32
;
178 c
->guard_interval
= GUARD_INTERVAL_1_16
;
181 c
->guard_interval
= GUARD_INTERVAL_1_8
;
184 c
->guard_interval
= GUARD_INTERVAL_1_4
;
188 switch ((buf
[0] >> 3) & 0x07) {
190 c
->hierarchy
= HIERARCHY_NONE
;
193 c
->hierarchy
= HIERARCHY_1
;
196 c
->hierarchy
= HIERARCHY_2
;
199 c
->hierarchy
= HIERARCHY_4
;
203 switch ((buf
[0] >> 0) & 0x07) {
205 c
->code_rate_HP
= FEC_1_2
;
208 c
->code_rate_HP
= FEC_2_3
;
211 c
->code_rate_HP
= FEC_3_4
;
214 c
->code_rate_HP
= FEC_5_6
;
217 c
->code_rate_HP
= FEC_7_8
;
221 switch ((buf
[1] >> 5) & 0x07) {
223 c
->code_rate_LP
= FEC_1_2
;
226 c
->code_rate_LP
= FEC_2_3
;
229 c
->code_rate_LP
= FEC_3_4
;
232 c
->code_rate_LP
= FEC_5_6
;
235 c
->code_rate_LP
= FEC_7_8
;
239 ret
= cxd2820r_rd_reg(priv
, 0x007c6, &buf
[0]);
243 switch ((buf
[0] >> 0) & 0x01) {
245 c
->inversion
= INVERSION_OFF
;
248 c
->inversion
= INVERSION_ON
;
254 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
258 int cxd2820r_read_ber_t(struct dvb_frontend
*fe
, u32
*ber
)
260 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
262 u8 buf
[3], start_ber
= 0;
265 if (priv
->ber_running
) {
266 ret
= cxd2820r_rd_regs(priv
, 0x00076, buf
, sizeof(buf
));
270 if ((buf
[2] >> 7) & 0x01 || (buf
[2] >> 4) & 0x01) {
271 *ber
= (buf
[2] & 0x0f) << 16 | buf
[1] << 8 | buf
[0];
275 priv
->ber_running
= true;
281 ret
= cxd2820r_wr_reg(priv
, 0x00079, 0x01);
288 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
292 int cxd2820r_read_signal_strength_t(struct dvb_frontend
*fe
,
295 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
300 ret
= cxd2820r_rd_regs(priv
, 0x00026, buf
, sizeof(buf
));
304 tmp
= (buf
[0] & 0x0f) << 8 | buf
[1];
307 /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
308 *strength
= tmp
* 0xffff / 0x0fff;
312 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
316 int cxd2820r_read_snr_t(struct dvb_frontend
*fe
, u16
*snr
)
318 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
322 /* report SNR in dB * 10 */
324 ret
= cxd2820r_rd_regs(priv
, 0x00028, buf
, sizeof(buf
));
328 tmp
= (buf
[0] & 0x1f) << 8 | buf
[1];
329 #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
331 *snr
= (intlog10(tmp
) - CXD2820R_LOG10_8_24
) / ((1 << 24)
336 dev_dbg(&priv
->i2c
->dev
, "%s: dBx10=%d val=%04x\n", __func__
, *snr
,
341 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
345 int cxd2820r_read_ucblocks_t(struct dvb_frontend
*fe
, u32
*ucblocks
)
348 /* no way to read ? */
352 int cxd2820r_read_status_t(struct dvb_frontend
*fe
, enum fe_status
*status
)
354 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
359 ret
= cxd2820r_rd_reg(priv
, 0x00010, &buf
[0]);
363 if ((buf
[0] & 0x07) == 6) {
364 ret
= cxd2820r_rd_reg(priv
, 0x00073, &buf
[1]);
368 if (((buf
[1] >> 3) & 0x01) == 1) {
369 *status
|= FE_HAS_SIGNAL
| FE_HAS_CARRIER
|
370 FE_HAS_VITERBI
| FE_HAS_SYNC
| FE_HAS_LOCK
;
372 *status
|= FE_HAS_SIGNAL
| FE_HAS_CARRIER
|
373 FE_HAS_VITERBI
| FE_HAS_SYNC
;
376 ret
= cxd2820r_rd_reg(priv
, 0x00014, &buf
[2]);
380 if ((buf
[2] & 0x0f) >= 4) {
381 ret
= cxd2820r_rd_reg(priv
, 0x00a14, &buf
[3]);
385 if (((buf
[3] >> 4) & 0x01) == 1)
386 *status
|= FE_HAS_SIGNAL
;
390 dev_dbg(&priv
->i2c
->dev
, "%s: lock=%*ph\n", __func__
, 4, buf
);
394 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
398 int cxd2820r_init_t(struct dvb_frontend
*fe
)
400 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
403 ret
= cxd2820r_wr_reg(priv
, 0x00085, 0x07);
409 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
413 int cxd2820r_sleep_t(struct dvb_frontend
*fe
)
415 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
417 struct reg_val_mask tab
[] = {
418 { 0x000ff, 0x1f, 0xff },
419 { 0x00085, 0x00, 0xff },
420 { 0x00088, 0x01, 0xff },
421 { 0x00081, 0x00, 0xff },
422 { 0x00080, 0x00, 0xff },
425 dev_dbg(&priv
->i2c
->dev
, "%s\n", __func__
);
427 priv
->delivery_system
= SYS_UNDEFINED
;
429 for (i
= 0; i
< ARRAY_SIZE(tab
); i
++) {
430 ret
= cxd2820r_wr_reg_mask(priv
, tab
[i
].reg
, tab
[i
].val
,
438 dev_dbg(&priv
->i2c
->dev
, "%s: failed=%d\n", __func__
, ret
);
442 int cxd2820r_get_tune_settings_t(struct dvb_frontend
*fe
,
443 struct dvb_frontend_tune_settings
*s
)
445 s
->min_delay_ms
= 500;
446 s
->step_size
= fe
->ops
.info
.frequency_stepsize
* 2;
447 s
->max_drift
= (fe
->ops
.info
.frequency_stepsize
* 2) + 1;