drivers/misc/cxl/cxl.h

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #ifndef _CXL_H_
  11 #define _CXL_H_
  12
  13 #include <linux/interrupt.h>
  14 #include <linux/semaphore.h>
  15 #include <linux/device.h>
  16 #include <linux/types.h>
  17 #include <linux/cdev.h>
  18 #include <linux/pid.h>
  19 #include <linux/io.h>
  20 #include <linux/pci.h>
  21 #include <linux/fs.h>
  22 #include <asm/cputable.h>
  23 #include <asm/mmu.h>
  24 #include <asm/reg.h>
  25 #include <misc/cxl-base.h>
  26
  27 #include <uapi/misc/cxl.h>
  28
  29 extern uint cxl_verbose;
  30
  31 #define CXL_TIMEOUT 5
  32
  33 /*
  34  * Bump version each time a user API change is made, whether it is
  35  * backwards compatible ot not.
  36  */
  37 #define CXL_API_VERSION 2
  38 #define CXL_API_VERSION_COMPATIBLE 1
  39
  40 /*
  41  * Opaque types to avoid accidentally passing registers for the wrong MMIO
  42  *
  43  * At the end of the day, I'm not married to using typedef here, but it might
  44  * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
  45  * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
  46  *
  47  * I'm quite happy if these are changed back to #defines before upstreaming, it
  48  * should be little more than a regexp search+replace operation in this file.
  49  */
  50 typedef struct {
  51         const int x;
  52 } cxl_p1_reg_t;
  53 typedef struct {
  54         const int x;
  55 } cxl_p1n_reg_t;
  56 typedef struct {
  57         const int x;
  58 } cxl_p2n_reg_t;
  59 #define cxl_reg_off(reg) \
  60         (reg.x)
  61
  62 /* Memory maps. Ref CXL Appendix A */
  63
  64 /* PSL Privilege 1 Memory Map */
  65 /* Configuration and Control area */
  66 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
  67 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
  68 static const cxl_p1_reg_t CXL_PSL_KEY1    = {0x0010};
  69 static const cxl_p1_reg_t CXL_PSL_KEY2    = {0x0018};
  70 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
  71 /* Downloading */
  72 static const cxl_p1_reg_t CXL_PSL_DLCNTL  = {0x0060};
  73 static const cxl_p1_reg_t CXL_PSL_DLADDR  = {0x0068};
  74
  75 /* PSL Lookaside Buffer Management Area */
  76 static const cxl_p1_reg_t CXL_PSL_LBISEL  = {0x0080};
  77 static const cxl_p1_reg_t CXL_PSL_SLBIE   = {0x0088};
  78 static const cxl_p1_reg_t CXL_PSL_SLBIA   = {0x0090};
  79 static const cxl_p1_reg_t CXL_PSL_TLBIE   = {0x00A0};
  80 static const cxl_p1_reg_t CXL_PSL_TLBIA   = {0x00A8};
  81 static const cxl_p1_reg_t CXL_PSL_AFUSEL  = {0x00B0};
  82
  83 /* 0x00C0:7EFF Implementation dependent area */
  84 static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
  85 static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
  86 static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
  87 static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
  88 static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
  89 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
  90 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
  91 static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
  92 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
  93 static const cxl_p1_reg_t CXL_PSL_TRACE     = {0x0170};
  94 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
  95 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
  96
  97 /* PSL Slice Privilege 1 Memory Map */
  98 /* Configuration Area */
  99 static const cxl_p1n_reg_t CXL_PSL_SR_An          = {0x00};
 100 static const cxl_p1n_reg_t CXL_PSL_LPID_An        = {0x08};
 101 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An       = {0x10};
 102 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An    = {0x18};
 103 static const cxl_p1n_reg_t CXL_PSL_ID_An          = {0x20};
 104 static const cxl_p1n_reg_t CXL_PSL_SERR_An        = {0x28};
 105 /* Memory Management and Lookaside Buffer Management */
 106 static const cxl_p1n_reg_t CXL_PSL_SDR_An         = {0x30};
 107 static const cxl_p1n_reg_t CXL_PSL_AMOR_An        = {0x38};
 108 /* Pointer Area */
 109 static const cxl_p1n_reg_t CXL_HAURP_An           = {0x80};
 110 static const cxl_p1n_reg_t CXL_PSL_SPAP_An        = {0x88};
 111 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An       = {0x90};
 112 /* Control Area */
 113 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An       = {0xA0};
 114 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An     = {0xA8};
 115 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
 116 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An  = {0xB8};
 117 /* 0xC0:FF Implementation Dependent Area */
 118 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An   = {0xC0};
 119 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An       = {0xC8};
 120 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A     = {0xD0};
 121 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A      = {0xD8};
 122 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A        = {0xE0};
 123 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE    = {0xE8};
 124
 125 /* PSL Slice Privilege 2 Memory Map */
 126 /* Configuration and Control Area */
 127 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
 128 static const cxl_p2n_reg_t CXL_CSRP_An        = {0x008};
 129 static const cxl_p2n_reg_t CXL_AURP0_An       = {0x010};
 130 static const cxl_p2n_reg_t CXL_AURP1_An       = {0x018};
 131 static const cxl_p2n_reg_t CXL_SSTP0_An       = {0x020};
 132 static const cxl_p2n_reg_t CXL_SSTP1_An       = {0x028};
 133 static const cxl_p2n_reg_t CXL_PSL_AMR_An     = {0x030};
 134 /* Segment Lookaside Buffer Management */
 135 static const cxl_p2n_reg_t CXL_SLBIE_An       = {0x040};
 136 static const cxl_p2n_reg_t CXL_SLBIA_An       = {0x048};
 137 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
 138 /* Interrupt Registers */
 139 static const cxl_p2n_reg_t CXL_PSL_DSISR_An   = {0x060};
 140 static const cxl_p2n_reg_t CXL_PSL_DAR_An     = {0x068};
 141 static const cxl_p2n_reg_t CXL_PSL_DSR_An     = {0x070};
 142 static const cxl_p2n_reg_t CXL_PSL_TFC_An     = {0x078};
 143 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
 144 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
 145 /* AFU Registers */
 146 static const cxl_p2n_reg_t CXL_AFU_Cntl_An    = {0x090};
 147 static const cxl_p2n_reg_t CXL_AFU_ERR_An     = {0x098};
 148 /* Work Element Descriptor */
 149 static const cxl_p2n_reg_t CXL_PSL_WED_An     = {0x0A0};
 150 /* 0x0C0:FFF Implementation Dependent Area */
 151
 152 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
 153 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
 154 #define CXL_PSL_SPAP_Size_Shift 4
 155 #define CXL_PSL_SPAP_V    0x0000000000000001ULL
 156
 157 /****** CXL_PSL_Control ****************************************************/
 158 #define CXL_PSL_Control_tb 0x0000000000000001ULL
 159
 160 /****** CXL_PSL_DLCNTL *****************************************************/
 161 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
 162 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
 163 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
 164 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
 165 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
 166 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
 167
 168 /****** CXL_PSL_SR_An ******************************************************/
 169 #define CXL_PSL_SR_An_SF  MSR_SF            /* 64bit */
 170 #define CXL_PSL_SR_An_TA  (1ull << (63-1))  /* Tags active,   GA1: 0 */
 171 #define CXL_PSL_SR_An_HV  MSR_HV            /* Hypervisor,    GA1: 0 */
 172 #define CXL_PSL_SR_An_PR  MSR_PR            /* Problem state, GA1: 1 */
 173 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
 174 #define CXL_PSL_SR_An_TC  (1ull << (63-54)) /* Page Table secondary hash */
 175 #define CXL_PSL_SR_An_US  (1ull << (63-56)) /* User state,    GA1: X */
 176 #define CXL_PSL_SR_An_SC  (1ull << (63-58)) /* Segment Table secondary hash */
 177 #define CXL_PSL_SR_An_R   MSR_DR            /* Relocate,      GA1: 1 */
 178 #define CXL_PSL_SR_An_MP  (1ull << (63-62)) /* Master Process */
 179 #define CXL_PSL_SR_An_LE  (1ull << (63-63)) /* Little Endian */
 180
 181 /****** CXL_PSL_LLCMD_An ****************************************************/
 182 #define CXL_LLCMD_TERMINATE   0x0001000000000000ULL
 183 #define CXL_LLCMD_REMOVE      0x0002000000000000ULL
 184 #define CXL_LLCMD_SUSPEND     0x0003000000000000ULL
 185 #define CXL_LLCMD_RESUME      0x0004000000000000ULL
 186 #define CXL_LLCMD_ADD         0x0005000000000000ULL
 187 #define CXL_LLCMD_UPDATE      0x0006000000000000ULL
 188 #define CXL_LLCMD_HANDLE_MASK 0x000000000000ffffULL
 189
 190 /****** CXL_PSL_ID_An ****************************************************/
 191 #define CXL_PSL_ID_An_F (1ull << (63-31))
 192 #define CXL_PSL_ID_An_L (1ull << (63-30))
 193
 194 /****** CXL_PSL_SCNTL_An ****************************************************/
 195 #define CXL_PSL_SCNTL_An_CR          (0x1ull << (63-15))
 196 /* Programming Modes: */
 197 #define CXL_PSL_SCNTL_An_PM_MASK     (0xffffull << (63-31))
 198 #define CXL_PSL_SCNTL_An_PM_Shared   (0x0000ull << (63-31))
 199 #define CXL_PSL_SCNTL_An_PM_OS       (0x0001ull << (63-31))
 200 #define CXL_PSL_SCNTL_An_PM_Process  (0x0002ull << (63-31))
 201 #define CXL_PSL_SCNTL_An_PM_AFU      (0x0004ull << (63-31))
 202 #define CXL_PSL_SCNTL_An_PM_AFU_PBT  (0x0104ull << (63-31))
 203 /* Purge Status (ro) */
 204 #define CXL_PSL_SCNTL_An_Ps_MASK     (0x3ull << (63-39))
 205 #define CXL_PSL_SCNTL_An_Ps_Pending  (0x1ull << (63-39))
 206 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
 207 /* Purge */
 208 #define CXL_PSL_SCNTL_An_Pc          (0x1ull << (63-48))
 209 /* Suspend Status (ro) */
 210 #define CXL_PSL_SCNTL_An_Ss_MASK     (0x3ull << (63-55))
 211 #define CXL_PSL_SCNTL_An_Ss_Pending  (0x1ull << (63-55))
 212 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
 213 /* Suspend Control */
 214 #define CXL_PSL_SCNTL_An_Sc          (0x1ull << (63-63))
 215
 216 /* AFU Slice Enable Status (ro) */
 217 #define CXL_AFU_Cntl_An_ES_MASK     (0x7ull << (63-2))
 218 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
 219 #define CXL_AFU_Cntl_An_ES_Enabled  (0x4ull << (63-2))
 220 /* AFU Slice Enable */
 221 #define CXL_AFU_Cntl_An_E           (0x1ull << (63-3))
 222 /* AFU Slice Reset status (ro) */
 223 #define CXL_AFU_Cntl_An_RS_MASK     (0x3ull << (63-5))
 224 #define CXL_AFU_Cntl_An_RS_Pending  (0x1ull << (63-5))
 225 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
 226 /* AFU Slice Reset */
 227 #define CXL_AFU_Cntl_An_RA          (0x1ull << (63-7))
 228
 229 /****** CXL_SSTP0/1_An ******************************************************/
 230 /* These top bits are for the segment that CONTAINS the segment table */
 231 #define CXL_SSTP0_An_B_SHIFT    SLB_VSID_SSIZE_SHIFT
 232 #define CXL_SSTP0_An_KS             (1ull << (63-2))
 233 #define CXL_SSTP0_An_KP             (1ull << (63-3))
 234 #define CXL_SSTP0_An_N              (1ull << (63-4))
 235 #define CXL_SSTP0_An_L              (1ull << (63-5))
 236 #define CXL_SSTP0_An_C              (1ull << (63-6))
 237 #define CXL_SSTP0_An_TA             (1ull << (63-7))
 238 #define CXL_SSTP0_An_LP_SHIFT                (63-9)  /* 2 Bits */
 239 /* And finally, the virtual address & size of the segment table: */
 240 #define CXL_SSTP0_An_SegTableSize_SHIFT      (63-31) /* 12 Bits */
 241 #define CXL_SSTP0_An_SegTableSize_MASK \
 242         (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
 243 #define CXL_SSTP0_An_STVA_U_MASK   ((1ull << (63-49))-1)
 244 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
 245 #define CXL_SSTP1_An_V              (1ull << (63-63))
 246
 247 /****** CXL_PSL_SLBIE_[An] **************************************************/
 248 /* write: */
 249 #define CXL_SLBIE_C        PPC_BIT(36)         /* Class */
 250 #define CXL_SLBIE_SS       PPC_BITMASK(37, 38) /* Segment Size */
 251 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
 252 #define CXL_SLBIE_TA       PPC_BIT(38)         /* Tags Active */
 253 /* read: */
 254 #define CXL_SLBIE_MAX      PPC_BITMASK(24, 31)
 255 #define CXL_SLBIE_PENDING  PPC_BITMASK(56, 63)
 256
 257 /****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/
 258 #define CXL_TLB_SLB_P          (1ull) /* Pending (read) */
 259
 260 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/
 261 #define CXL_TLB_SLB_IQ_ALL     (0ull) /* Inv qualifier */
 262 #define CXL_TLB_SLB_IQ_LPID    (1ull) /* Inv qualifier */
 263 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
 264
 265 /****** CXL_PSL_AFUSEL ******************************************************/
 266 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
 267
 268 /****** CXL_PSL_DSISR_An ****************************************************/
 269 #define CXL_PSL_DSISR_An_DS (1ull << (63-0))  /* Segment not found */
 270 #define CXL_PSL_DSISR_An_DM (1ull << (63-1))  /* PTE not found (See also: M) or protection fault */
 271 #define CXL_PSL_DSISR_An_ST (1ull << (63-2))  /* Segment Table PTE not found */
 272 #define CXL_PSL_DSISR_An_UR (1ull << (63-3))  /* AURP PTE not found */
 273 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
 274 #define CXL_PSL_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 275 #define CXL_PSL_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 276 #define CXL_PSL_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
 277 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
 278 #define CXL_PSL_DSISR_An_M  DSISR_NOHPTE      /* PTE not found */
 279 #define CXL_PSL_DSISR_An_P  DSISR_PROTFAULT   /* Storage protection violation */
 280 #define CXL_PSL_DSISR_An_A  (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
 281 #define CXL_PSL_DSISR_An_S  DSISR_ISSTORE     /* Access was afu_wr or afu_zero */
 282 #define CXL_PSL_DSISR_An_K  DSISR_KEYFAULT    /* Access not permitted by virtual page class key protection */
 283
 284 /****** CXL_PSL_TFC_An ******************************************************/
 285 #define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation fault */
 286 #define CXL_PSL_TFC_An_C  (1ull << (63-29)) /* Continue (abort transaction) */
 287 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
 288 #define CXL_PSL_TFC_An_R  (1ull << (63-31)) /* Restart PSL transaction */
 289
 290 /* cxl_process_element->software_status */
 291 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 -  0)) /* Valid */
 292 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
 293 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
 294 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
 295
 296 /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
 297  * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
 298  * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
 299  * of the hang pulse frequency.
 300  */
 301 #define CXL_PSL_RXCTL_AFUHP_4S      0x7000000000000000ULL
 302
 303 /* SPA->sw_command_status */
 304 #define CXL_SPA_SW_CMD_MASK         0xffff000000000000ULL
 305 #define CXL_SPA_SW_CMD_TERMINATE    0x0001000000000000ULL
 306 #define CXL_SPA_SW_CMD_REMOVE       0x0002000000000000ULL
 307 #define CXL_SPA_SW_CMD_SUSPEND      0x0003000000000000ULL
 308 #define CXL_SPA_SW_CMD_RESUME       0x0004000000000000ULL
 309 #define CXL_SPA_SW_CMD_ADD          0x0005000000000000ULL
 310 #define CXL_SPA_SW_CMD_UPDATE       0x0006000000000000ULL
 311 #define CXL_SPA_SW_STATE_MASK       0x0000ffff00000000ULL
 312 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
 313 #define CXL_SPA_SW_STATE_REMOVED    0x0000000200000000ULL
 314 #define CXL_SPA_SW_STATE_SUSPENDED  0x0000000300000000ULL
 315 #define CXL_SPA_SW_STATE_RESUMED    0x0000000400000000ULL
 316 #define CXL_SPA_SW_STATE_ADDED      0x0000000500000000ULL
 317 #define CXL_SPA_SW_STATE_UPDATED    0x0000000600000000ULL
 318 #define CXL_SPA_SW_PSL_ID_MASK      0x00000000ffff0000ULL
 319 #define CXL_SPA_SW_LINK_MASK        0x000000000000ffffULL
 320
 321 #define CXL_MAX_SLICES 4
 322 #define MAX_AFU_MMIO_REGS 3
 323
 324 #define CXL_MODE_TIME_SLICED 0x4
 325 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
 326
 327 enum cxl_context_status {
 328         CLOSED,
 329         OPENED,
 330         STARTED
 331 };
 332
 333 enum prefault_modes {
 334         CXL_PREFAULT_NONE,
 335         CXL_PREFAULT_WED,
 336         CXL_PREFAULT_ALL,
 337 };
 338
 339 struct cxl_sste {
 340         __be64 esid_data;
 341         __be64 vsid_data;
 342 };
 343
 344 #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
 345 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
 346
 347 struct cxl_afu {
 348         irq_hw_number_t psl_hwirq;
 349         irq_hw_number_t serr_hwirq;
 350         char *err_irq_name;
 351         char *psl_irq_name;
 352         unsigned int serr_virq;
 353         void __iomem *p1n_mmio;
 354         void __iomem *p2n_mmio;
 355         phys_addr_t psn_phys;
 356         u64 pp_offset;
 357         u64 pp_size;
 358         void __iomem *afu_desc_mmio;
 359         struct cxl *adapter;
 360         struct device dev;
 361         struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
 362         struct device *chardev_s, *chardev_m, *chardev_d;
 363         struct idr contexts_idr;
 364         struct dentry *debugfs;
 365         struct mutex contexts_lock;
 366         struct mutex spa_mutex;
 367         spinlock_t afu_cntl_lock;
 368
 369         /* AFU error buffer fields and bin attribute for sysfs */
 370         u64 eb_len, eb_offset;
 371         struct bin_attribute attr_eb;
 372
 373         /*
 374          * Only the first part of the SPA is used for the process element
 375          * linked list. The only other part that software needs to worry about
 376          * is sw_command_status, which we store a separate pointer to.
 377          * Everything else in the SPA is only used by hardware
 378          */
 379         struct cxl_process_element *spa;
 380         __be64 *sw_command_status;
 381         unsigned int spa_size;
 382         int spa_order;
 383         int spa_max_procs;
 384         unsigned int psl_virq;
 385
 386         /* pointer to the vphb */
 387         struct pci_controller *phb;
 388
 389         int pp_irqs;
 390         int irqs_max;
 391         int num_procs;
 392         int max_procs_virtualised;
 393         int slice;
 394         int modes_supported;
 395         int current_mode;
 396         int crs_num;
 397         u64 crs_len;
 398         u64 crs_offset;
 399         struct list_head crs;
 400         enum prefault_modes prefault_mode;
 401         bool psa;
 402         bool pp_psa;
 403         bool enabled;
 404 };
 405
 406
 407 struct cxl_irq_name {
 408         struct list_head list;
 409         char *name;
 410 };
 411
 412 /*
 413  * This is a cxl context.  If the PSL is in dedicated mode, there will be one
 414  * of these per AFU.  If in AFU directed there can be lots of these.
 415  */
 416 struct cxl_context {
 417         struct cxl_afu *afu;
 418
 419         /* Problem state MMIO */
 420         phys_addr_t psn_phys;
 421         u64 psn_size;
 422
 423         /* Used to unmap any mmaps when force detaching */
 424         struct address_space *mapping;
 425         struct mutex mapping_lock;
 426         struct page *ff_page;
 427         bool mmio_err_ff;
 428         bool kernelapi;
 429
 430         spinlock_t sste_lock; /* Protects segment table entries */
 431         struct cxl_sste *sstp;
 432         u64 sstp0, sstp1;
 433         unsigned int sst_size, sst_lru;
 434
 435         wait_queue_head_t wq;
 436         struct pid *pid;
 437         spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
 438         /* Only used in PR mode */
 439         u64 process_token;
 440
 441         unsigned long *irq_bitmap; /* Accessed from IRQ context */
 442         struct cxl_irq_ranges irqs;
 443         struct list_head irq_names;
 444         u64 fault_addr;
 445         u64 fault_dsisr;
 446         u64 afu_err;
 447
 448         /*
 449          * This status and it's lock pretects start and detach context
 450          * from racing.  It also prevents detach from racing with
 451          * itself
 452          */
 453         enum cxl_context_status status;
 454         struct mutex status_mutex;
 455
 456
 457         /* XXX: Is it possible to need multiple work items at once? */
 458         struct work_struct fault_work;
 459         u64 dsisr;
 460         u64 dar;
 461
 462         struct cxl_process_element *elem;
 463
 464         int pe; /* process element handle */
 465         u32 irq_count;
 466         bool pe_inserted;
 467         bool master;
 468         bool kernel;
 469         bool pending_irq;
 470         bool pending_fault;
 471         bool pending_afu_err;
 472
 473         struct rcu_head rcu;
 474 };
 475
 476 struct cxl {
 477         void __iomem *p1_mmio;
 478         void __iomem *p2_mmio;
 479         irq_hw_number_t err_hwirq;
 480         unsigned int err_virq;
 481         spinlock_t afu_list_lock;
 482         struct cxl_afu *afu[CXL_MAX_SLICES];
 483         struct device dev;
 484         struct dentry *trace;
 485         struct dentry *psl_err_chk;
 486         struct dentry *debugfs;
 487         char *irq_name;
 488         struct bin_attribute cxl_attr;
 489         int adapter_num;
 490         int user_irqs;
 491         u64 afu_desc_off;
 492         u64 afu_desc_size;
 493         u64 ps_off;
 494         u64 ps_size;
 495         u16 psl_rev;
 496         u16 base_image;
 497         u8 vsec_status;
 498         u8 caia_major;
 499         u8 caia_minor;
 500         u8 slices;
 501         bool user_image_loaded;
 502         bool perst_loads_image;
 503         bool perst_select_user;
 504         bool perst_same_image;
 505 };
 506
 507 int cxl_alloc_one_irq(struct cxl *adapter);
 508 void cxl_release_one_irq(struct cxl *adapter, int hwirq);
 509 int cxl_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
 510 void cxl_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
 511 int cxl_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
 512 int cxl_update_image_control(struct cxl *adapter);
 513 int cxl_reset(struct cxl *adapter);
 514
 515 /* common == phyp + powernv */
 516 struct cxl_process_element_common {
 517         __be32 tid;
 518         __be32 pid;
 519         __be64 csrp;
 520         __be64 aurp0;
 521         __be64 aurp1;
 522         __be64 sstp0;
 523         __be64 sstp1;
 524         __be64 amr;
 525         u8     reserved3[4];
 526         __be64 wed;
 527 } __packed;
 528
 529 /* just powernv */
 530 struct cxl_process_element {
 531         __be64 sr;
 532         __be64 SPOffset;
 533         __be64 sdr;
 534         __be64 haurp;
 535         __be32 ctxtime;
 536         __be16 ivte_offsets[4];
 537         __be16 ivte_ranges[4];
 538         __be32 lpid;
 539         struct cxl_process_element_common common;
 540         __be32 software_state;
 541 } __packed;
 542
 543 static inline bool cxl_adapter_link_ok(struct cxl *cxl)
 544 {
 545         struct pci_dev *pdev;
 546
 547         pdev = to_pci_dev(cxl->dev.parent);
 548         return !pci_channel_offline(pdev);
 549 }
 550
 551 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
 552 {
 553         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 554         return cxl->p1_mmio + cxl_reg_off(reg);
 555 }
 556
 557 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
 558 {
 559         if (likely(cxl_adapter_link_ok(cxl)))
 560                 out_be64(_cxl_p1_addr(cxl, reg), val);
 561 }
 562
 563 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
 564 {
 565         if (likely(cxl_adapter_link_ok(cxl)))
 566                 return in_be64(_cxl_p1_addr(cxl, reg));
 567         else
 568                 return ~0ULL;
 569 }
 570
 571 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 572 {
 573         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 574         return afu->p1n_mmio + cxl_reg_off(reg);
 575 }
 576
 577 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
 578 {
 579         if (likely(cxl_adapter_link_ok(afu->adapter)))
 580                 out_be64(_cxl_p1n_addr(afu, reg), val);
 581 }
 582
 583 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 584 {
 585         if (likely(cxl_adapter_link_ok(afu->adapter)))
 586                 return in_be64(_cxl_p1n_addr(afu, reg));
 587         else
 588                 return ~0ULL;
 589 }
 590
 591 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 592 {
 593         return afu->p2n_mmio + cxl_reg_off(reg);
 594 }
 595
 596 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
 597 {
 598         if (likely(cxl_adapter_link_ok(afu->adapter)))
 599                 out_be64(_cxl_p2n_addr(afu, reg), val);
 600 }
 601
 602 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 603 {
 604         if (likely(cxl_adapter_link_ok(afu->adapter)))
 605                 return in_be64(_cxl_p2n_addr(afu, reg));
 606         else
 607                 return ~0ULL;
 608 }
 609
 610 static inline u64 cxl_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off)
 611 {
 612         if (likely(cxl_adapter_link_ok(afu->adapter)))
 613                 return in_le64((afu)->afu_desc_mmio + (afu)->crs_offset +
 614                                ((cr) * (afu)->crs_len) + (off));
 615         else
 616                 return ~0ULL;
 617 }
 618
 619 static inline u32 cxl_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off)
 620 {
 621         if (likely(cxl_adapter_link_ok(afu->adapter)))
 622                 return in_le32((afu)->afu_desc_mmio + (afu)->crs_offset +
 623                                ((cr) * (afu)->crs_len) + (off));
 624         else
 625                 return 0xffffffff;
 626 }
 627 u16 cxl_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off);
 628 u8 cxl_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off);
 629
 630 ssize_t cxl_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
 631                                 loff_t off, size_t count);
 632
 633
 634 struct cxl_calls {
 635         void (*cxl_slbia)(struct mm_struct *mm);
 636         struct module *owner;
 637 };
 638 int register_cxl_calls(struct cxl_calls *calls);
 639 void unregister_cxl_calls(struct cxl_calls *calls);
 640
 641 int cxl_alloc_adapter_nr(struct cxl *adapter);
 642 void cxl_remove_adapter_nr(struct cxl *adapter);
 643
 644 int cxl_alloc_spa(struct cxl_afu *afu);
 645 void cxl_release_spa(struct cxl_afu *afu);
 646
 647 int cxl_file_init(void);
 648 void cxl_file_exit(void);
 649 int cxl_register_adapter(struct cxl *adapter);
 650 int cxl_register_afu(struct cxl_afu *afu);
 651 int cxl_chardev_d_afu_add(struct cxl_afu *afu);
 652 int cxl_chardev_m_afu_add(struct cxl_afu *afu);
 653 int cxl_chardev_s_afu_add(struct cxl_afu *afu);
 654 void cxl_chardev_afu_remove(struct cxl_afu *afu);
 655
 656 void cxl_context_detach_all(struct cxl_afu *afu);
 657 void cxl_context_free(struct cxl_context *ctx);
 658 void cxl_context_detach(struct cxl_context *ctx);
 659
 660 int cxl_sysfs_adapter_add(struct cxl *adapter);
 661 void cxl_sysfs_adapter_remove(struct cxl *adapter);
 662 int cxl_sysfs_afu_add(struct cxl_afu *afu);
 663 void cxl_sysfs_afu_remove(struct cxl_afu *afu);
 664 int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
 665 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
 666
 667 int cxl_afu_activate_mode(struct cxl_afu *afu, int mode);
 668 int _cxl_afu_deactivate_mode(struct cxl_afu *afu, int mode);
 669 int cxl_afu_deactivate_mode(struct cxl_afu *afu);
 670 int cxl_afu_select_best_mode(struct cxl_afu *afu);
 671
 672 int cxl_register_psl_irq(struct cxl_afu *afu);
 673 void cxl_release_psl_irq(struct cxl_afu *afu);
 674 int cxl_register_psl_err_irq(struct cxl *adapter);
 675 void cxl_release_psl_err_irq(struct cxl *adapter);
 676 int cxl_register_serr_irq(struct cxl_afu *afu);
 677 void cxl_release_serr_irq(struct cxl_afu *afu);
 678 int afu_register_irqs(struct cxl_context *ctx, u32 count);
 679 void afu_release_irqs(struct cxl_context *ctx, void *cookie);
 680 void afu_irq_name_free(struct cxl_context *ctx);
 681 irqreturn_t cxl_slice_irq_err(int irq, void *data);
 682
 683 int cxl_debugfs_init(void);
 684 void cxl_debugfs_exit(void);
 685 int cxl_debugfs_adapter_add(struct cxl *adapter);
 686 void cxl_debugfs_adapter_remove(struct cxl *adapter);
 687 int cxl_debugfs_afu_add(struct cxl_afu *afu);
 688 void cxl_debugfs_afu_remove(struct cxl_afu *afu);
 689
 690 void cxl_handle_fault(struct work_struct *work);
 691 void cxl_prefault(struct cxl_context *ctx, u64 wed);
 692
 693 struct cxl *get_cxl_adapter(int num);
 694 int cxl_alloc_sst(struct cxl_context *ctx);
 695
 696 void init_cxl_native(void);
 697
 698 struct cxl_context *cxl_context_alloc(void);
 699 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master,
 700                      struct address_space *mapping);
 701 void cxl_context_free(struct cxl_context *ctx);
 702 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
 703 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
 704                          irq_handler_t handler, void *cookie, const char *name);
 705 void cxl_unmap_irq(unsigned int virq, void *cookie);
 706 int __detach_context(struct cxl_context *ctx);
 707
 708 /* This matches the layout of the H_COLLECT_CA_INT_INFO retbuf */
 709 struct cxl_irq_info {
 710         u64 dsisr;
 711         u64 dar;
 712         u64 dsr;
 713         u32 pid;
 714         u32 tid;
 715         u64 afu_err;
 716         u64 errstat;
 717         u64 padding[3]; /* to match the expected retbuf size for plpar_hcall9 */
 718 };
 719
 720 void cxl_assign_psn_space(struct cxl_context *ctx);
 721 int cxl_attach_process(struct cxl_context *ctx, bool kernel, u64 wed,
 722                             u64 amr);
 723 int cxl_detach_process(struct cxl_context *ctx);
 724
 725 int cxl_get_irq(struct cxl_afu *afu, struct cxl_irq_info *info);
 726 int cxl_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
 727
 728 int cxl_check_error(struct cxl_afu *afu);
 729 int cxl_afu_slbia(struct cxl_afu *afu);
 730 int cxl_tlb_slb_invalidate(struct cxl *adapter);
 731 int cxl_afu_disable(struct cxl_afu *afu);
 732 int __cxl_afu_reset(struct cxl_afu *afu);
 733 int cxl_afu_check_and_enable(struct cxl_afu *afu);
 734 int cxl_psl_purge(struct cxl_afu *afu);
 735
 736 void cxl_stop_trace(struct cxl *cxl);
 737 int cxl_pci_vphb_add(struct cxl_afu *afu);
 738 void cxl_pci_vphb_reconfigure(struct cxl_afu *afu);
 739 void cxl_pci_vphb_remove(struct cxl_afu *afu);
 740
 741 extern struct pci_driver cxl_pci_driver;
 742 int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
 743
 744 int afu_open(struct inode *inode, struct file *file);
 745 int afu_release(struct inode *inode, struct file *file);
 746 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
 747 int afu_mmap(struct file *file, struct vm_area_struct *vm);
 748 unsigned int afu_poll(struct file *file, struct poll_table_struct *poll);
 749 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
 750 extern const struct file_operations afu_fops;
 751
 752 #endif