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of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-at91.c
blob0d2fc0cff35ee6216ef5e62a77376e63cb2675e7
1 /*
2 * at91 pinctrl driver based on at91 pinmux core
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9 #include <linux/clk.h>
10 #include <linux/err.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/gpio.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 /* Since we request GPIOs from ourself */
26 #include <linux/pinctrl/consumer.h>
27
28 #include "pinctrl-at91.h"
29 #include "core.h"
30
31 #define MAX_GPIO_BANKS 5
32 #define MAX_NB_GPIO_PER_BANK 32
33
34 struct at91_pinctrl_mux_ops;
35
36 struct at91_gpio_chip {
37 struct gpio_chip chip;
38 struct pinctrl_gpio_range range;
39 struct at91_gpio_chip *next; /* Bank sharing same clock */
40 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
41 int pioc_virq; /* PIO bank Linux virtual interrupt */
42 int pioc_idx; /* PIO bank index */
43 void __iomem *regbase; /* PIO bank virtual address */
44 struct clk *clock; /* associated clock */
45 struct at91_pinctrl_mux_ops *ops; /* ops */
46 };
47
48 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
49
50 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
51
52 static int gpio_banks;
53
54 #define PULL_UP (1 << 0)
55 #define MULTI_DRIVE (1 << 1)
56 #define DEGLITCH (1 << 2)
57 #define PULL_DOWN (1 << 3)
58 #define DIS_SCHMIT (1 << 4)
59 #define DRIVE_STRENGTH_SHIFT 5
60 #define DRIVE_STRENGTH_MASK 0x3
61 #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
62 #define DEBOUNCE (1 << 16)
63 #define DEBOUNCE_VAL_SHIFT 17
64 #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
65
66 /**
67 * These defines will translated the dt binding settings to our internal
68 * settings. They are not necessarily the same value as the register setting.
69 * The actual drive strength current of low, medium and high must be looked up
70 * from the corresponding device datasheet. This value is different for pins
71 * that are even in the same banks. It is also dependent on VCC.
72 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
73 * strength when there is no dt config for it.
74 */
75 #define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
76 #define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
77 #define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
78 #define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
79
80 /**
81 * struct at91_pmx_func - describes AT91 pinmux functions
82 * @name: the name of this specific function
83 * @groups: corresponding pin groups
84 * @ngroups: the number of groups
85 */
86 struct at91_pmx_func {
87 const char *name;
88 const char **groups;
89 unsigned ngroups;
90 };
91
92 enum at91_mux {
93 AT91_MUX_GPIO = 0,
94 AT91_MUX_PERIPH_A = 1,
95 AT91_MUX_PERIPH_B = 2,
96 AT91_MUX_PERIPH_C = 3,
97 AT91_MUX_PERIPH_D = 4,
98 };
99
100 /**
101 * struct at91_pmx_pin - describes an At91 pin mux
102 * @bank: the bank of the pin
103 * @pin: the pin number in the @bank
104 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
105 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
106 */
107 struct at91_pmx_pin {
108 uint32_t bank;
109 uint32_t pin;
110 enum at91_mux mux;
111 unsigned long conf;
112 };
113
114 /**
115 * struct at91_pin_group - describes an At91 pin group
116 * @name: the name of this specific pin group
117 * @pins_conf: the mux mode for each pin in this group. The size of this
118 * array is the same as pins.
119 * @pins: an array of discrete physical pins used in this group, taken
120 * from the driver-local pin enumeration space
121 * @npins: the number of pins in this group array, i.e. the number of
122 * elements in .pins so we can iterate over that array
123 */
124 struct at91_pin_group {
125 const char *name;
126 struct at91_pmx_pin *pins_conf;
127 unsigned int *pins;
128 unsigned npins;
129 };
130
131 /**
132 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
133 * on new IP with support for periph C and D the way to mux in
134 * periph A and B has changed
135 * So provide the right call back
136 * if not present means the IP does not support it
137 * @get_periph: return the periph mode configured
138 * @mux_A_periph: mux as periph A
139 * @mux_B_periph: mux as periph B
140 * @mux_C_periph: mux as periph C
141 * @mux_D_periph: mux as periph D
142 * @get_deglitch: get deglitch status
143 * @set_deglitch: enable/disable deglitch
144 * @get_debounce: get debounce status
145 * @set_debounce: enable/disable debounce
146 * @get_pulldown: get pulldown status
147 * @set_pulldown: enable/disable pulldown
148 * @get_schmitt_trig: get schmitt trigger status
149 * @disable_schmitt_trig: disable schmitt trigger
150 * @irq_type: return irq type
151 */
152 struct at91_pinctrl_mux_ops {
153 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
154 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
155 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
156 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
157 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
158 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
159 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
160 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
161 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
162 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
163 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
164 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
165 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
166 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
167 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
168 u32 strength);
169 /* irq */
170 int (*irq_type)(struct irq_data *d, unsigned type);
171 };
172
173 static int gpio_irq_type(struct irq_data *d, unsigned type);
174 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
175
176 struct at91_pinctrl {
177 struct device *dev;
178 struct pinctrl_dev *pctl;
179
180 int nactive_banks;
181
182 uint32_t *mux_mask;
183 int nmux;
184
185 struct at91_pmx_func *functions;
186 int nfunctions;
187
188 struct at91_pin_group *groups;
189 int ngroups;
190
191 struct at91_pinctrl_mux_ops *ops;
192 };
193
194 static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
195 const struct at91_pinctrl *info,
196 const char *name)
197 {
198 const struct at91_pin_group *grp = NULL;
199 int i;
200
201 for (i = 0; i < info->ngroups; i++) {
202 if (strcmp(info->groups[i].name, name))
203 continue;
204
205 grp = &info->groups[i];
206 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
207 break;
208 }
209
210 return grp;
211 }
212
213 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
214 {
215 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
216
217 return info->ngroups;
218 }
219
220 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
221 unsigned selector)
222 {
223 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
224
225 return info->groups[selector].name;
226 }
227
228 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
229 const unsigned **pins,
230 unsigned *npins)
231 {
232 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
233
234 if (selector >= info->ngroups)
235 return -EINVAL;
236
237 *pins = info->groups[selector].pins;
238 *npins = info->groups[selector].npins;
239
240 return 0;
241 }
242
243 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
244 unsigned offset)
245 {
246 seq_printf(s, "%s", dev_name(pctldev->dev));
247 }
248
249 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
250 struct device_node *np,
251 struct pinctrl_map **map, unsigned *num_maps)
252 {
253 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
254 const struct at91_pin_group *grp;
255 struct pinctrl_map *new_map;
256 struct device_node *parent;
257 int map_num = 1;
258 int i;
259
260 /*
261 * first find the group of this node and check if we need to create
262 * config maps for pins
263 */
264 grp = at91_pinctrl_find_group_by_name(info, np->name);
265 if (!grp) {
266 dev_err(info->dev, "unable to find group for node %s\n",
267 np->name);
268 return -EINVAL;
269 }
270
271 map_num += grp->npins;
272 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL);
273 if (!new_map)
274 return -ENOMEM;
275
276 *map = new_map;
277 *num_maps = map_num;
278
279 /* create mux map */
280 parent = of_get_parent(np);
281 if (!parent) {
282 devm_kfree(pctldev->dev, new_map);
283 return -EINVAL;
284 }
285 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
286 new_map[0].data.mux.function = parent->name;
287 new_map[0].data.mux.group = np->name;
288 of_node_put(parent);
289
290 /* create config map */
291 new_map++;
292 for (i = 0; i < grp->npins; i++) {
293 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
294 new_map[i].data.configs.group_or_pin =
295 pin_get_name(pctldev, grp->pins[i]);
296 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
297 new_map[i].data.configs.num_configs = 1;
298 }
299
300 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
301 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
302
303 return 0;
304 }
305
306 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
307 struct pinctrl_map *map, unsigned num_maps)
308 {
309 }
310
311 static const struct pinctrl_ops at91_pctrl_ops = {
312 .get_groups_count = at91_get_groups_count,
313 .get_group_name = at91_get_group_name,
314 .get_group_pins = at91_get_group_pins,
315 .pin_dbg_show = at91_pin_dbg_show,
316 .dt_node_to_map = at91_dt_node_to_map,
317 .dt_free_map = at91_dt_free_map,
318 };
319
320 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
321 unsigned int bank)
322 {
323 if (!gpio_chips[bank])
324 return NULL;
325
326 return gpio_chips[bank]->regbase;
327 }
328
329 static inline int pin_to_bank(unsigned pin)
330 {
331 return pin /= MAX_NB_GPIO_PER_BANK;
332 }
333
334 static unsigned pin_to_mask(unsigned int pin)
335 {
336 return 1 << pin;
337 }
338
339 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
340 {
341 /* return the shift value for a pin for "two bit" per pin registers,
342 * i.e. drive strength */
343 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
344 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
345 }
346
347 static unsigned sama5d3_get_drive_register(unsigned int pin)
348 {
349 /* drive strength is split between two registers
350 * with two bits per pin */
351 return (pin >= MAX_NB_GPIO_PER_BANK/2)
352 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
353 }
354
355 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
356 {
357 /* drive strength is split between two registers
358 * with two bits per pin */
359 return (pin >= MAX_NB_GPIO_PER_BANK/2)
360 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
361 }
362
363 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
364 {
365 writel_relaxed(mask, pio + PIO_IDR);
366 }
367
368 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
369 {
370 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
371 }
372
373 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
374 {
375 if (on)
376 writel_relaxed(mask, pio + PIO_PPDDR);
377
378 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
379 }
380
381 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
382 {
383 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
384 }
385
386 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
387 {
388 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
389 }
390
391 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
392 {
393 writel_relaxed(mask, pio + PIO_ASR);
394 }
395
396 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
397 {
398 writel_relaxed(mask, pio + PIO_BSR);
399 }
400
401 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
402 {
403
404 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
405 pio + PIO_ABCDSR1);
406 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
407 pio + PIO_ABCDSR2);
408 }
409
410 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
411 {
412 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
413 pio + PIO_ABCDSR1);
414 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
415 pio + PIO_ABCDSR2);
416 }
417
418 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
419 {
420 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
421 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
422 }
423
424 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
425 {
426 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
427 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
428 }
429
430 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
431 {
432 unsigned select;
433
434 if (readl_relaxed(pio + PIO_PSR) & mask)
435 return AT91_MUX_GPIO;
436
437 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
438 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
439
440 return select + 1;
441 }
442
443 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
444 {
445 unsigned select;
446
447 if (readl_relaxed(pio + PIO_PSR) & mask)
448 return AT91_MUX_GPIO;
449
450 select = readl_relaxed(pio + PIO_ABSR) & mask;
451
452 return select + 1;
453 }
454
455 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
456 {
457 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
458 }
459
460 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
461 {
462 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
463 }
464
465 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
466 {
467 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
468 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
469
470 return false;
471 }
472
473 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
474 {
475 if (is_on)
476 writel_relaxed(mask, pio + PIO_IFSCDR);
477 at91_mux_set_deglitch(pio, mask, is_on);
478 }
479
480 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
481 {
482 *div = readl_relaxed(pio + PIO_SCDR);
483
484 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
485 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
486 }
487
488 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
489 bool is_on, u32 div)
490 {
491 if (is_on) {
492 writel_relaxed(mask, pio + PIO_IFSCER);
493 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
494 writel_relaxed(mask, pio + PIO_IFER);
495 } else
496 writel_relaxed(mask, pio + PIO_IFSCDR);
497 }
498
499 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
500 {
501 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
502 }
503
504 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
505 {
506 if (is_on)
507 writel_relaxed(mask, pio + PIO_PUDR);
508
509 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
510 }
511
512 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
513 {
514 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
515 }
516
517 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
518 {
519 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
520 }
521
522 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
523 {
524 unsigned tmp = readl_relaxed(reg);
525
526 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
527
528 return tmp & DRIVE_STRENGTH_MASK;
529 }
530
531 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
532 unsigned pin)
533 {
534 unsigned tmp = read_drive_strength(pio +
535 sama5d3_get_drive_register(pin), pin);
536
537 /* SAMA5 strength is 1:1 with our defines,
538 * except 0 is equivalent to low per datasheet */
539 if (!tmp)
540 tmp = DRIVE_STRENGTH_LOW;
541
542 return tmp;
543 }
544
545 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
546 unsigned pin)
547 {
548 unsigned tmp = read_drive_strength(pio +
549 at91sam9x5_get_drive_register(pin), pin);
550
551 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
552 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
553 tmp = DRIVE_STRENGTH_HI - tmp;
554
555 return tmp;
556 }
557
558 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
559 {
560 unsigned tmp = readl_relaxed(reg);
561 unsigned shift = two_bit_pin_value_shift_amount(pin);
562
563 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
564 tmp |= strength << shift;
565
566 writel_relaxed(tmp, reg);
567 }
568
569 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
570 u32 setting)
571 {
572 /* do nothing if setting is zero */
573 if (!setting)
574 return;
575
576 /* strength is 1 to 1 with setting for SAMA5 */
577 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
578 }
579
580 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
581 u32 setting)
582 {
583 /* do nothing if setting is zero */
584 if (!setting)
585 return;
586
587 /* strength is inverse on SAM9x5s with our defines
588 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
589 setting = DRIVE_STRENGTH_HI - setting;
590
591 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
592 setting);
593 }
594
595 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
596 .get_periph = at91_mux_get_periph,
597 .mux_A_periph = at91_mux_set_A_periph,
598 .mux_B_periph = at91_mux_set_B_periph,
599 .get_deglitch = at91_mux_get_deglitch,
600 .set_deglitch = at91_mux_set_deglitch,
601 .irq_type = gpio_irq_type,
602 };
603
604 static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
605 .get_periph = at91_mux_pio3_get_periph,
606 .mux_A_periph = at91_mux_pio3_set_A_periph,
607 .mux_B_periph = at91_mux_pio3_set_B_periph,
608 .mux_C_periph = at91_mux_pio3_set_C_periph,
609 .mux_D_periph = at91_mux_pio3_set_D_periph,
610 .get_deglitch = at91_mux_pio3_get_deglitch,
611 .set_deglitch = at91_mux_pio3_set_deglitch,
612 .get_debounce = at91_mux_pio3_get_debounce,
613 .set_debounce = at91_mux_pio3_set_debounce,
614 .get_pulldown = at91_mux_pio3_get_pulldown,
615 .set_pulldown = at91_mux_pio3_set_pulldown,
616 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
617 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
618 .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
619 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
620 .irq_type = alt_gpio_irq_type,
621 };
622
623 static struct at91_pinctrl_mux_ops sama5d3_ops = {
624 .get_periph = at91_mux_pio3_get_periph,
625 .mux_A_periph = at91_mux_pio3_set_A_periph,
626 .mux_B_periph = at91_mux_pio3_set_B_periph,
627 .mux_C_periph = at91_mux_pio3_set_C_periph,
628 .mux_D_periph = at91_mux_pio3_set_D_periph,
629 .get_deglitch = at91_mux_pio3_get_deglitch,
630 .set_deglitch = at91_mux_pio3_set_deglitch,
631 .get_debounce = at91_mux_pio3_get_debounce,
632 .set_debounce = at91_mux_pio3_set_debounce,
633 .get_pulldown = at91_mux_pio3_get_pulldown,
634 .set_pulldown = at91_mux_pio3_set_pulldown,
635 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
636 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
637 .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
638 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
639 .irq_type = alt_gpio_irq_type,
640 };
641
642 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
643 {
644 if (pin->mux) {
645 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
646 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
647 } else {
648 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
649 pin->bank + 'A', pin->pin, pin->conf);
650 }
651 }
652
653 static int pin_check_config(struct at91_pinctrl *info, const char *name,
654 int index, const struct at91_pmx_pin *pin)
655 {
656 int mux;
657
658 /* check if it's a valid config */
659 if (pin->bank >= gpio_banks) {
660 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
661 name, index, pin->bank, gpio_banks);
662 return -EINVAL;
663 }
664
665 if (!gpio_chips[pin->bank]) {
666 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
667 name, index, pin->bank);
668 return -ENXIO;
669 }
670
671 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
672 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
673 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
674 return -EINVAL;
675 }
676
677 if (!pin->mux)
678 return 0;
679
680 mux = pin->mux - 1;
681
682 if (mux >= info->nmux) {
683 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
684 name, index, mux, info->nmux);
685 return -EINVAL;
686 }
687
688 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
689 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
690 name, index, mux, pin->bank + 'A', pin->pin);
691 return -EINVAL;
692 }
693
694 return 0;
695 }
696
697 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
698 {
699 writel_relaxed(mask, pio + PIO_PDR);
700 }
701
702 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
703 {
704 writel_relaxed(mask, pio + PIO_PER);
705 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
706 }
707
708 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
709 unsigned group)
710 {
711 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
712 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
713 const struct at91_pmx_pin *pin;
714 uint32_t npins = info->groups[group].npins;
715 int i, ret;
716 unsigned mask;
717 void __iomem *pio;
718
719 dev_dbg(info->dev, "enable function %s group %s\n",
720 info->functions[selector].name, info->groups[group].name);
721
722 /* first check that all the pins of the group are valid with a valid
723 * parameter */
724 for (i = 0; i < npins; i++) {
725 pin = &pins_conf[i];
726 ret = pin_check_config(info, info->groups[group].name, i, pin);
727 if (ret)
728 return ret;
729 }
730
731 for (i = 0; i < npins; i++) {
732 pin = &pins_conf[i];
733 at91_pin_dbg(info->dev, pin);
734 pio = pin_to_controller(info, pin->bank);
735
736 if (!pio)
737 continue;
738
739 mask = pin_to_mask(pin->pin);
740 at91_mux_disable_interrupt(pio, mask);
741 switch (pin->mux) {
742 case AT91_MUX_GPIO:
743 at91_mux_gpio_enable(pio, mask, 1);
744 break;
745 case AT91_MUX_PERIPH_A:
746 info->ops->mux_A_periph(pio, mask);
747 break;
748 case AT91_MUX_PERIPH_B:
749 info->ops->mux_B_periph(pio, mask);
750 break;
751 case AT91_MUX_PERIPH_C:
752 if (!info->ops->mux_C_periph)
753 return -EINVAL;
754 info->ops->mux_C_periph(pio, mask);
755 break;
756 case AT91_MUX_PERIPH_D:
757 if (!info->ops->mux_D_periph)
758 return -EINVAL;
759 info->ops->mux_D_periph(pio, mask);
760 break;
761 }
762 if (pin->mux)
763 at91_mux_gpio_disable(pio, mask);
764 }
765
766 return 0;
767 }
768
769 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
770 {
771 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
772
773 return info->nfunctions;
774 }
775
776 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
777 unsigned selector)
778 {
779 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
780
781 return info->functions[selector].name;
782 }
783
784 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
785 const char * const **groups,
786 unsigned * const num_groups)
787 {
788 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
789
790 *groups = info->functions[selector].groups;
791 *num_groups = info->functions[selector].ngroups;
792
793 return 0;
794 }
795
796 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
797 struct pinctrl_gpio_range *range,
798 unsigned offset)
799 {
800 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
801 struct at91_gpio_chip *at91_chip;
802 struct gpio_chip *chip;
803 unsigned mask;
804
805 if (!range) {
806 dev_err(npct->dev, "invalid range\n");
807 return -EINVAL;
808 }
809 if (!range->gc) {
810 dev_err(npct->dev, "missing GPIO chip in range\n");
811 return -EINVAL;
812 }
813 chip = range->gc;
814 at91_chip = container_of(chip, struct at91_gpio_chip, chip);
815
816 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
817
818 mask = 1 << (offset - chip->base);
819
820 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
821 offset, 'A' + range->id, offset - chip->base, mask);
822
823 writel_relaxed(mask, at91_chip->regbase + PIO_PER);
824
825 return 0;
826 }
827
828 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
829 struct pinctrl_gpio_range *range,
830 unsigned offset)
831 {
832 struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
833
834 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
835 /* Set the pin to some default state, GPIO is usually default */
836 }
837
838 static const struct pinmux_ops at91_pmx_ops = {
839 .get_functions_count = at91_pmx_get_funcs_count,
840 .get_function_name = at91_pmx_get_func_name,
841 .get_function_groups = at91_pmx_get_groups,
842 .set_mux = at91_pmx_set,
843 .gpio_request_enable = at91_gpio_request_enable,
844 .gpio_disable_free = at91_gpio_disable_free,
845 };
846
847 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
848 unsigned pin_id, unsigned long *config)
849 {
850 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
851 void __iomem *pio;
852 unsigned pin;
853 int div;
854
855 *config = 0;
856 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
857 pio = pin_to_controller(info, pin_to_bank(pin_id));
858
859 if (!pio)
860 return -EINVAL;
861
862 pin = pin_id % MAX_NB_GPIO_PER_BANK;
863
864 if (at91_mux_get_multidrive(pio, pin))
865 *config |= MULTI_DRIVE;
866
867 if (at91_mux_get_pullup(pio, pin))
868 *config |= PULL_UP;
869
870 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
871 *config |= DEGLITCH;
872 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
873 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
874 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
875 *config |= PULL_DOWN;
876 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
877 *config |= DIS_SCHMIT;
878 if (info->ops->get_drivestrength)
879 *config |= (info->ops->get_drivestrength(pio, pin)
880 << DRIVE_STRENGTH_SHIFT);
881
882 return 0;
883 }
884
885 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
886 unsigned pin_id, unsigned long *configs,
887 unsigned num_configs)
888 {
889 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
890 unsigned mask;
891 void __iomem *pio;
892 int i;
893 unsigned long config;
894 unsigned pin;
895
896 for (i = 0; i < num_configs; i++) {
897 config = configs[i];
898
899 dev_dbg(info->dev,
900 "%s:%d, pin_id=%d, config=0x%lx",
901 __func__, __LINE__, pin_id, config);
902 pio = pin_to_controller(info, pin_to_bank(pin_id));
903
904 if (!pio)
905 return -EINVAL;
906
907 pin = pin_id % MAX_NB_GPIO_PER_BANK;
908 mask = pin_to_mask(pin);
909
910 if (config & PULL_UP && config & PULL_DOWN)
911 return -EINVAL;
912
913 at91_mux_set_pullup(pio, mask, config & PULL_UP);
914 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
915 if (info->ops->set_deglitch)
916 info->ops->set_deglitch(pio, mask, config & DEGLITCH);
917 if (info->ops->set_debounce)
918 info->ops->set_debounce(pio, mask, config & DEBOUNCE,
919 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
920 if (info->ops->set_pulldown)
921 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
922 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
923 info->ops->disable_schmitt_trig(pio, mask);
924 if (info->ops->set_drivestrength)
925 info->ops->set_drivestrength(pio, pin,
926 (config & DRIVE_STRENGTH)
927 >> DRIVE_STRENGTH_SHIFT);
928
929 } /* for each config */
930
931 return 0;
932 }
933
934 #define DBG_SHOW_FLAG(flag) do { \
935 if (config & flag) { \
936 if (num_conf) \
937 seq_puts(s, "|"); \
938 seq_puts(s, #flag); \
939 num_conf++; \
940 } \
941 } while (0)
942
943 #define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
944 if ((config & mask) == flag) { \
945 if (num_conf) \
946 seq_puts(s, "|"); \
947 seq_puts(s, #flag); \
948 num_conf++; \
949 } \
950 } while (0)
951
952 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
953 struct seq_file *s, unsigned pin_id)
954 {
955 unsigned long config;
956 int val, num_conf = 0;
957
958 at91_pinconf_get(pctldev, pin_id, &config);
959
960 DBG_SHOW_FLAG(MULTI_DRIVE);
961 DBG_SHOW_FLAG(PULL_UP);
962 DBG_SHOW_FLAG(PULL_DOWN);
963 DBG_SHOW_FLAG(DIS_SCHMIT);
964 DBG_SHOW_FLAG(DEGLITCH);
965 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
966 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
967 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
968 DBG_SHOW_FLAG(DEBOUNCE);
969 if (config & DEBOUNCE) {
970 val = config >> DEBOUNCE_VAL_SHIFT;
971 seq_printf(s, "(%d)", val);
972 }
973
974 return;
975 }
976
977 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
978 struct seq_file *s, unsigned group)
979 {
980 }
981
982 static const struct pinconf_ops at91_pinconf_ops = {
983 .pin_config_get = at91_pinconf_get,
984 .pin_config_set = at91_pinconf_set,
985 .pin_config_dbg_show = at91_pinconf_dbg_show,
986 .pin_config_group_dbg_show = at91_pinconf_group_dbg_show,
987 };
988
989 static struct pinctrl_desc at91_pinctrl_desc = {
990 .pctlops = &at91_pctrl_ops,
991 .pmxops = &at91_pmx_ops,
992 .confops = &at91_pinconf_ops,
993 .owner = THIS_MODULE,
994 };
995
996 static const char *gpio_compat = "atmel,at91rm9200-gpio";
997
998 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
999 struct device_node *np)
1000 {
1001 struct device_node *child;
1002
1003 for_each_child_of_node(np, child) {
1004 if (of_device_is_compatible(child, gpio_compat)) {
1005 if (of_device_is_available(child))
1006 info->nactive_banks++;
1007 } else {
1008 info->nfunctions++;
1009 info->ngroups += of_get_child_count(child);
1010 }
1011 }
1012 }
1013
1014 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1015 struct device_node *np)
1016 {
1017 int ret = 0;
1018 int size;
1019 const __be32 *list;
1020
1021 list = of_get_property(np, "atmel,mux-mask", &size);
1022 if (!list) {
1023 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1024 return -EINVAL;
1025 }
1026
1027 size /= sizeof(*list);
1028 if (!size || size % gpio_banks) {
1029 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1030 return -EINVAL;
1031 }
1032 info->nmux = size / gpio_banks;
1033
1034 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
1035 if (!info->mux_mask) {
1036 dev_err(info->dev, "could not alloc mux_mask\n");
1037 return -ENOMEM;
1038 }
1039
1040 ret = of_property_read_u32_array(np, "atmel,mux-mask",
1041 info->mux_mask, size);
1042 if (ret)
1043 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1044 return ret;
1045 }
1046
1047 static int at91_pinctrl_parse_groups(struct device_node *np,
1048 struct at91_pin_group *grp,
1049 struct at91_pinctrl *info, u32 index)
1050 {
1051 struct at91_pmx_pin *pin;
1052 int size;
1053 const __be32 *list;
1054 int i, j;
1055
1056 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1057
1058 /* Initialise group */
1059 grp->name = np->name;
1060
1061 /*
1062 * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1063 * do sanity check and calculate pins number
1064 */
1065 list = of_get_property(np, "atmel,pins", &size);
1066 /* we do not check return since it's safe node passed down */
1067 size /= sizeof(*list);
1068 if (!size || size % 4) {
1069 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1070 return -EINVAL;
1071 }
1072
1073 grp->npins = size / 4;
1074 pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin),
1075 GFP_KERNEL);
1076 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1077 GFP_KERNEL);
1078 if (!grp->pins_conf || !grp->pins)
1079 return -ENOMEM;
1080
1081 for (i = 0, j = 0; i < size; i += 4, j++) {
1082 pin->bank = be32_to_cpu(*list++);
1083 pin->pin = be32_to_cpu(*list++);
1084 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1085 pin->mux = be32_to_cpu(*list++);
1086 pin->conf = be32_to_cpu(*list++);
1087
1088 at91_pin_dbg(info->dev, pin);
1089 pin++;
1090 }
1091
1092 return 0;
1093 }
1094
1095 static int at91_pinctrl_parse_functions(struct device_node *np,
1096 struct at91_pinctrl *info, u32 index)
1097 {
1098 struct device_node *child;
1099 struct at91_pmx_func *func;
1100 struct at91_pin_group *grp;
1101 int ret;
1102 static u32 grp_index;
1103 u32 i = 0;
1104
1105 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1106
1107 func = &info->functions[index];
1108
1109 /* Initialise function */
1110 func->name = np->name;
1111 func->ngroups = of_get_child_count(np);
1112 if (func->ngroups == 0) {
1113 dev_err(info->dev, "no groups defined\n");
1114 return -EINVAL;
1115 }
1116 func->groups = devm_kzalloc(info->dev,
1117 func->ngroups * sizeof(char *), GFP_KERNEL);
1118 if (!func->groups)
1119 return -ENOMEM;
1120
1121 for_each_child_of_node(np, child) {
1122 func->groups[i] = child->name;
1123 grp = &info->groups[grp_index++];
1124 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1125 if (ret) {
1126 of_node_put(child);
1127 return ret;
1128 }
1129 }
1130
1131 return 0;
1132 }
1133
1134 static const struct of_device_id at91_pinctrl_of_match[] = {
1135 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1136 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1137 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1138 { /* sentinel */ }
1139 };
1140
1141 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1142 struct at91_pinctrl *info)
1143 {
1144 int ret = 0;
1145 int i, j;
1146 uint32_t *tmp;
1147 struct device_node *np = pdev->dev.of_node;
1148 struct device_node *child;
1149
1150 if (!np)
1151 return -ENODEV;
1152
1153 info->dev = &pdev->dev;
1154 info->ops = (struct at91_pinctrl_mux_ops *)
1155 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1156 at91_pinctrl_child_count(info, np);
1157
1158 if (gpio_banks < 1) {
1159 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1160 return -EINVAL;
1161 }
1162
1163 ret = at91_pinctrl_mux_mask(info, np);
1164 if (ret)
1165 return ret;
1166
1167 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1168
1169 dev_dbg(&pdev->dev, "mux-mask\n");
1170 tmp = info->mux_mask;
1171 for (i = 0; i < gpio_banks; i++) {
1172 for (j = 0; j < info->nmux; j++, tmp++) {
1173 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1174 }
1175 }
1176
1177 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1178 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1179 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func),
1180 GFP_KERNEL);
1181 if (!info->functions)
1182 return -ENOMEM;
1183
1184 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group),
1185 GFP_KERNEL);
1186 if (!info->groups)
1187 return -ENOMEM;
1188
1189 dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1190 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1191 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1192
1193 i = 0;
1194
1195 for_each_child_of_node(np, child) {
1196 if (of_device_is_compatible(child, gpio_compat))
1197 continue;
1198 ret = at91_pinctrl_parse_functions(child, info, i++);
1199 if (ret) {
1200 dev_err(&pdev->dev, "failed to parse function\n");
1201 of_node_put(child);
1202 return ret;
1203 }
1204 }
1205
1206 return 0;
1207 }
1208
1209 static int at91_pinctrl_probe(struct platform_device *pdev)
1210 {
1211 struct at91_pinctrl *info;
1212 struct pinctrl_pin_desc *pdesc;
1213 int ret, i, j, k, ngpio_chips_enabled = 0;
1214
1215 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1216 if (!info)
1217 return -ENOMEM;
1218
1219 ret = at91_pinctrl_probe_dt(pdev, info);
1220 if (ret)
1221 return ret;
1222
1223 /*
1224 * We need all the GPIO drivers to probe FIRST, or we will not be able
1225 * to obtain references to the struct gpio_chip * for them, and we
1226 * need this to proceed.
1227 */
1228 for (i = 0; i < gpio_banks; i++)
1229 if (gpio_chips[i])
1230 ngpio_chips_enabled++;
1231
1232 if (ngpio_chips_enabled < info->nactive_banks) {
1233 dev_warn(&pdev->dev,
1234 "All GPIO chips are not registered yet (%d/%d)\n",
1235 ngpio_chips_enabled, info->nactive_banks);
1236 devm_kfree(&pdev->dev, info);
1237 return -EPROBE_DEFER;
1238 }
1239
1240 at91_pinctrl_desc.name = dev_name(&pdev->dev);
1241 at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1242 at91_pinctrl_desc.pins = pdesc =
1243 devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL);
1244
1245 if (!at91_pinctrl_desc.pins)
1246 return -ENOMEM;
1247
1248 for (i = 0, k = 0; i < gpio_banks; i++) {
1249 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1250 pdesc->number = k;
1251 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1252 pdesc++;
1253 }
1254 }
1255
1256 platform_set_drvdata(pdev, info);
1257 info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info);
1258
1259 if (IS_ERR(info->pctl)) {
1260 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1261 return PTR_ERR(info->pctl);
1262 }
1263
1264 /* We will handle a range of GPIO pins */
1265 for (i = 0; i < gpio_banks; i++)
1266 if (gpio_chips[i])
1267 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1268
1269 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1270
1271 return 0;
1272 }
1273
1274 static int at91_pinctrl_remove(struct platform_device *pdev)
1275 {
1276 struct at91_pinctrl *info = platform_get_drvdata(pdev);
1277
1278 pinctrl_unregister(info->pctl);
1279
1280 return 0;
1281 }
1282
1283 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1284 {
1285 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1286 void __iomem *pio = at91_gpio->regbase;
1287 unsigned mask = 1 << offset;
1288 u32 osr;
1289
1290 osr = readl_relaxed(pio + PIO_OSR);
1291 return !(osr & mask);
1292 }
1293
1294 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1295 {
1296 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1297 void __iomem *pio = at91_gpio->regbase;
1298 unsigned mask = 1 << offset;
1299
1300 writel_relaxed(mask, pio + PIO_ODR);
1301 return 0;
1302 }
1303
1304 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1305 {
1306 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1307 void __iomem *pio = at91_gpio->regbase;
1308 unsigned mask = 1 << offset;
1309 u32 pdsr;
1310
1311 pdsr = readl_relaxed(pio + PIO_PDSR);
1312 return (pdsr & mask) != 0;
1313 }
1314
1315 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1316 int val)
1317 {
1318 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1319 void __iomem *pio = at91_gpio->regbase;
1320 unsigned mask = 1 << offset;
1321
1322 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1323 }
1324
1325 static void at91_gpio_set_multiple(struct gpio_chip *chip,
1326 unsigned long *mask, unsigned long *bits)
1327 {
1328 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1329 void __iomem *pio = at91_gpio->regbase;
1330
1331 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1332 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1333 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1334 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1335
1336 writel_relaxed(set_mask, pio + PIO_SODR);
1337 writel_relaxed(clear_mask, pio + PIO_CODR);
1338 }
1339
1340 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1341 int val)
1342 {
1343 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1344 void __iomem *pio = at91_gpio->regbase;
1345 unsigned mask = 1 << offset;
1346
1347 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1348 writel_relaxed(mask, pio + PIO_OER);
1349
1350 return 0;
1351 }
1352
1353 #ifdef CONFIG_DEBUG_FS
1354 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1355 {
1356 enum at91_mux mode;
1357 int i;
1358 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
1359 void __iomem *pio = at91_gpio->regbase;
1360
1361 for (i = 0; i < chip->ngpio; i++) {
1362 unsigned mask = pin_to_mask(i);
1363 const char *gpio_label;
1364
1365 gpio_label = gpiochip_is_requested(chip, i);
1366 if (!gpio_label)
1367 continue;
1368 mode = at91_gpio->ops->get_periph(pio, mask);
1369 seq_printf(s, "[%s] GPIO%s%d: ",
1370 gpio_label, chip->label, i);
1371 if (mode == AT91_MUX_GPIO) {
1372 seq_printf(s, "[gpio] ");
1373 seq_printf(s, "%s ",
1374 readl_relaxed(pio + PIO_OSR) & mask ?
1375 "output" : "input");
1376 seq_printf(s, "%s\n",
1377 readl_relaxed(pio + PIO_PDSR) & mask ?
1378 "set" : "clear");
1379 } else {
1380 seq_printf(s, "[periph %c]\n",
1381 mode + 'A' - 1);
1382 }
1383 }
1384 }
1385 #else
1386 #define at91_gpio_dbg_show NULL
1387 #endif
1388
1389 /* Several AIC controller irqs are dispatched through this GPIO handler.
1390 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1391 * at91_set_gpio_input() then maybe enable its glitch filter.
1392 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1393 * handler.
1394 * First implementation always triggers on rising and falling edges
1395 * whereas the newer PIO3 can be additionally configured to trigger on
1396 * level, edge with any polarity.
1397 *
1398 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1399 * configuring them with at91_set_a_periph() or at91_set_b_periph().
1400 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1401 */
1402
1403 static void gpio_irq_mask(struct irq_data *d)
1404 {
1405 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1406 void __iomem *pio = at91_gpio->regbase;
1407 unsigned mask = 1 << d->hwirq;
1408
1409 if (pio)
1410 writel_relaxed(mask, pio + PIO_IDR);
1411 }
1412
1413 static void gpio_irq_unmask(struct irq_data *d)
1414 {
1415 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1416 void __iomem *pio = at91_gpio->regbase;
1417 unsigned mask = 1 << d->hwirq;
1418
1419 if (pio)
1420 writel_relaxed(mask, pio + PIO_IER);
1421 }
1422
1423 static int gpio_irq_type(struct irq_data *d, unsigned type)
1424 {
1425 switch (type) {
1426 case IRQ_TYPE_NONE:
1427 case IRQ_TYPE_EDGE_BOTH:
1428 return 0;
1429 default:
1430 return -EINVAL;
1431 }
1432 }
1433
1434 /* Alternate irq type for PIO3 support */
1435 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1436 {
1437 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1438 void __iomem *pio = at91_gpio->regbase;
1439 unsigned mask = 1 << d->hwirq;
1440
1441 switch (type) {
1442 case IRQ_TYPE_EDGE_RISING:
1443 irq_set_handler_locked(d, handle_simple_irq);
1444 writel_relaxed(mask, pio + PIO_ESR);
1445 writel_relaxed(mask, pio + PIO_REHLSR);
1446 break;
1447 case IRQ_TYPE_EDGE_FALLING:
1448 irq_set_handler_locked(d, handle_simple_irq);
1449 writel_relaxed(mask, pio + PIO_ESR);
1450 writel_relaxed(mask, pio + PIO_FELLSR);
1451 break;
1452 case IRQ_TYPE_LEVEL_LOW:
1453 irq_set_handler_locked(d, handle_level_irq);
1454 writel_relaxed(mask, pio + PIO_LSR);
1455 writel_relaxed(mask, pio + PIO_FELLSR);
1456 break;
1457 case IRQ_TYPE_LEVEL_HIGH:
1458 irq_set_handler_locked(d, handle_level_irq);
1459 writel_relaxed(mask, pio + PIO_LSR);
1460 writel_relaxed(mask, pio + PIO_REHLSR);
1461 break;
1462 case IRQ_TYPE_EDGE_BOTH:
1463 /*
1464 * disable additional interrupt modes:
1465 * fall back to default behavior
1466 */
1467 irq_set_handler_locked(d, handle_simple_irq);
1468 writel_relaxed(mask, pio + PIO_AIMDR);
1469 return 0;
1470 case IRQ_TYPE_NONE:
1471 default:
1472 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1473 return -EINVAL;
1474 }
1475
1476 /* enable additional interrupt modes */
1477 writel_relaxed(mask, pio + PIO_AIMER);
1478
1479 return 0;
1480 }
1481
1482 static void gpio_irq_ack(struct irq_data *d)
1483 {
1484 /* the interrupt is already cleared before by reading ISR */
1485 }
1486
1487 #ifdef CONFIG_PM
1488
1489 static u32 wakeups[MAX_GPIO_BANKS];
1490 static u32 backups[MAX_GPIO_BANKS];
1491
1492 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1493 {
1494 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1495 unsigned bank = at91_gpio->pioc_idx;
1496 unsigned mask = 1 << d->hwirq;
1497
1498 if (unlikely(bank >= MAX_GPIO_BANKS))
1499 return -EINVAL;
1500
1501 if (state)
1502 wakeups[bank] |= mask;
1503 else
1504 wakeups[bank] &= ~mask;
1505
1506 irq_set_irq_wake(at91_gpio->pioc_virq, state);
1507
1508 return 0;
1509 }
1510
1511 void at91_pinctrl_gpio_suspend(void)
1512 {
1513 int i;
1514
1515 for (i = 0; i < gpio_banks; i++) {
1516 void __iomem *pio;
1517
1518 if (!gpio_chips[i])
1519 continue;
1520
1521 pio = gpio_chips[i]->regbase;
1522
1523 backups[i] = readl_relaxed(pio + PIO_IMR);
1524 writel_relaxed(backups[i], pio + PIO_IDR);
1525 writel_relaxed(wakeups[i], pio + PIO_IER);
1526
1527 if (!wakeups[i])
1528 clk_disable_unprepare(gpio_chips[i]->clock);
1529 else
1530 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1531 'A'+i, wakeups[i]);
1532 }
1533 }
1534
1535 void at91_pinctrl_gpio_resume(void)
1536 {
1537 int i;
1538
1539 for (i = 0; i < gpio_banks; i++) {
1540 void __iomem *pio;
1541
1542 if (!gpio_chips[i])
1543 continue;
1544
1545 pio = gpio_chips[i]->regbase;
1546
1547 if (!wakeups[i])
1548 clk_prepare_enable(gpio_chips[i]->clock);
1549
1550 writel_relaxed(wakeups[i], pio + PIO_IDR);
1551 writel_relaxed(backups[i], pio + PIO_IER);
1552 }
1553 }
1554
1555 #else
1556 #define gpio_irq_set_wake NULL
1557 #endif /* CONFIG_PM */
1558
1559 static struct irq_chip gpio_irqchip = {
1560 .name = "GPIO",
1561 .irq_ack = gpio_irq_ack,
1562 .irq_disable = gpio_irq_mask,
1563 .irq_mask = gpio_irq_mask,
1564 .irq_unmask = gpio_irq_unmask,
1565 /* .irq_set_type is set dynamically */
1566 .irq_set_wake = gpio_irq_set_wake,
1567 };
1568
1569 static void gpio_irq_handler(struct irq_desc *desc)
1570 {
1571 struct irq_chip *chip = irq_desc_get_chip(desc);
1572 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1573 struct at91_gpio_chip *at91_gpio = container_of(gpio_chip,
1574 struct at91_gpio_chip, chip);
1575
1576 void __iomem *pio = at91_gpio->regbase;
1577 unsigned long isr;
1578 int n;
1579
1580 chained_irq_enter(chip, desc);
1581 for (;;) {
1582 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1583 * When there are none pending, we're finished unless we need
1584 * to process multiple banks (like ID_PIOCDE on sam9263).
1585 */
1586 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1587 if (!isr) {
1588 if (!at91_gpio->next)
1589 break;
1590 at91_gpio = at91_gpio->next;
1591 pio = at91_gpio->regbase;
1592 gpio_chip = &at91_gpio->chip;
1593 continue;
1594 }
1595
1596 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1597 generic_handle_irq(irq_find_mapping(
1598 gpio_chip->irqdomain, n));
1599 }
1600 }
1601 chained_irq_exit(chip, desc);
1602 /* now it may re-trigger */
1603 }
1604
1605 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1606 struct at91_gpio_chip *at91_gpio)
1607 {
1608 struct gpio_chip *gpiochip_prev = NULL;
1609 struct at91_gpio_chip *prev = NULL;
1610 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1611 int ret, i;
1612
1613 at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1614
1615 /* Setup proper .irq_set_type function */
1616 gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type;
1617
1618 /* Disable irqs of this PIO controller */
1619 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1620
1621 /*
1622 * Let the generic code handle this edge IRQ, the the chained
1623 * handler will perform the actual work of handling the parent
1624 * interrupt.
1625 */
1626 ret = gpiochip_irqchip_add(&at91_gpio->chip,
1627 &gpio_irqchip,
1628 0,
1629 handle_edge_irq,
1630 IRQ_TYPE_EDGE_BOTH);
1631 if (ret) {
1632 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1633 at91_gpio->pioc_idx);
1634 return ret;
1635 }
1636
1637 /* The top level handler handles one bank of GPIOs, except
1638 * on some SoC it can handle up to three...
1639 * We only set up the handler for the first of the list.
1640 */
1641 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1642 if (!gpiochip_prev) {
1643 /* Then register the chain on the parent IRQ */
1644 gpiochip_set_chained_irqchip(&at91_gpio->chip,
1645 &gpio_irqchip,
1646 at91_gpio->pioc_virq,
1647 gpio_irq_handler);
1648 return 0;
1649 }
1650
1651 prev = container_of(gpiochip_prev, struct at91_gpio_chip, chip);
1652
1653 /* we can only have 2 banks before */
1654 for (i = 0; i < 2; i++) {
1655 if (prev->next) {
1656 prev = prev->next;
1657 } else {
1658 prev->next = at91_gpio;
1659 return 0;
1660 }
1661 }
1662
1663 return -EINVAL;
1664 }
1665
1666 /* This structure is replicated for each GPIO block allocated at probe time */
1667 static struct gpio_chip at91_gpio_template = {
1668 .request = gpiochip_generic_request,
1669 .free = gpiochip_generic_free,
1670 .get_direction = at91_gpio_get_direction,
1671 .direction_input = at91_gpio_direction_input,
1672 .get = at91_gpio_get,
1673 .direction_output = at91_gpio_direction_output,
1674 .set = at91_gpio_set,
1675 .set_multiple = at91_gpio_set_multiple,
1676 .dbg_show = at91_gpio_dbg_show,
1677 .can_sleep = false,
1678 .ngpio = MAX_NB_GPIO_PER_BANK,
1679 };
1680
1681 static const struct of_device_id at91_gpio_of_match[] = {
1682 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1683 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1684 { /* sentinel */ }
1685 };
1686
1687 static int at91_gpio_probe(struct platform_device *pdev)
1688 {
1689 struct device_node *np = pdev->dev.of_node;
1690 struct resource *res;
1691 struct at91_gpio_chip *at91_chip = NULL;
1692 struct gpio_chip *chip;
1693 struct pinctrl_gpio_range *range;
1694 int ret = 0;
1695 int irq, i;
1696 int alias_idx = of_alias_get_id(np, "gpio");
1697 uint32_t ngpio;
1698 char **names;
1699
1700 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1701 if (gpio_chips[alias_idx]) {
1702 ret = -EBUSY;
1703 goto err;
1704 }
1705
1706 irq = platform_get_irq(pdev, 0);
1707 if (irq < 0) {
1708 ret = irq;
1709 goto err;
1710 }
1711
1712 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1713 if (!at91_chip) {
1714 ret = -ENOMEM;
1715 goto err;
1716 }
1717
1718 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1719 at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1720 if (IS_ERR(at91_chip->regbase)) {
1721 ret = PTR_ERR(at91_chip->regbase);
1722 goto err;
1723 }
1724
1725 at91_chip->ops = (struct at91_pinctrl_mux_ops *)
1726 of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1727 at91_chip->pioc_virq = irq;
1728 at91_chip->pioc_idx = alias_idx;
1729
1730 at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1731 if (IS_ERR(at91_chip->clock)) {
1732 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1733 ret = PTR_ERR(at91_chip->clock);
1734 goto err;
1735 }
1736
1737 ret = clk_prepare(at91_chip->clock);
1738 if (ret)
1739 goto clk_prepare_err;
1740
1741 /* enable PIO controller's clock */
1742 ret = clk_enable(at91_chip->clock);
1743 if (ret) {
1744 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1745 goto clk_enable_err;
1746 }
1747
1748 at91_chip->chip = at91_gpio_template;
1749
1750 chip = &at91_chip->chip;
1751 chip->of_node = np;
1752 chip->label = dev_name(&pdev->dev);
1753 chip->dev = &pdev->dev;
1754 chip->owner = THIS_MODULE;
1755 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1756
1757 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1758 if (ngpio >= MAX_NB_GPIO_PER_BANK)
1759 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1760 alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1761 else
1762 chip->ngpio = ngpio;
1763 }
1764
1765 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1766 GFP_KERNEL);
1767
1768 if (!names) {
1769 ret = -ENOMEM;
1770 goto clk_enable_err;
1771 }
1772
1773 for (i = 0; i < chip->ngpio; i++)
1774 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1775
1776 chip->names = (const char *const *)names;
1777
1778 range = &at91_chip->range;
1779 range->name = chip->label;
1780 range->id = alias_idx;
1781 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1782
1783 range->npins = chip->ngpio;
1784 range->gc = chip;
1785
1786 ret = gpiochip_add(chip);
1787 if (ret)
1788 goto gpiochip_add_err;
1789
1790 gpio_chips[alias_idx] = at91_chip;
1791 gpio_banks = max(gpio_banks, alias_idx + 1);
1792
1793 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1794 if (ret)
1795 goto irq_setup_err;
1796
1797 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1798
1799 return 0;
1800
1801 irq_setup_err:
1802 gpiochip_remove(chip);
1803 gpiochip_add_err:
1804 clk_disable(at91_chip->clock);
1805 clk_enable_err:
1806 clk_unprepare(at91_chip->clock);
1807 clk_prepare_err:
1808 err:
1809 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1810
1811 return ret;
1812 }
1813
1814 static struct platform_driver at91_gpio_driver = {
1815 .driver = {
1816 .name = "gpio-at91",
1817 .of_match_table = at91_gpio_of_match,
1818 },
1819 .probe = at91_gpio_probe,
1820 };
1821
1822 static struct platform_driver at91_pinctrl_driver = {
1823 .driver = {
1824 .name = "pinctrl-at91",
1825 .of_match_table = at91_pinctrl_of_match,
1826 },
1827 .probe = at91_pinctrl_probe,
1828 .remove = at91_pinctrl_remove,
1829 };
1830
1831 static int __init at91_pinctrl_init(void)
1832 {
1833 int ret;
1834
1835 ret = platform_driver_register(&at91_gpio_driver);
1836 if (ret)
1837 return ret;
1838 return platform_driver_register(&at91_pinctrl_driver);
1839 }
1840 arch_initcall(at91_pinctrl_init);
1841
1842 static void __exit at91_pinctrl_exit(void)
1843 {
1844 platform_driver_unregister(&at91_pinctrl_driver);
1845 }
1846
1847 module_exit(at91_pinctrl_exit);
1848 MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
1849 MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
1850 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support