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of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / drivers / scsi / be2iscsi / be_cmds.c
blob2778089b01a578c5954686218c69b07b368e94cd
1 /**
2 * Copyright (C) 2005 - 2015 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@avagotech.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 #include <scsi/iscsi_proto.h>
19
20 #include "be_main.h"
21 #include "be.h"
22 #include "be_mgmt.h"
23
24 int beiscsi_pci_soft_reset(struct beiscsi_hba *phba)
25 {
26 u32 sreset;
27 u8 *pci_reset_offset = 0;
28 u8 *pci_online0_offset = 0;
29 u8 *pci_online1_offset = 0;
30 u32 pconline0 = 0;
31 u32 pconline1 = 0;
32 u32 i;
33
34 pci_reset_offset = (u8 *)phba->pci_va + BE2_SOFT_RESET;
35 pci_online0_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE0;
36 pci_online1_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE1;
37 sreset = readl((void *)pci_reset_offset);
38 sreset |= BE2_SET_RESET;
39 writel(sreset, (void *)pci_reset_offset);
40
41 i = 0;
42 while (sreset & BE2_SET_RESET) {
43 if (i > 64)
44 break;
45 msleep(100);
46 sreset = readl((void *)pci_reset_offset);
47 i++;
48 }
49
50 if (sreset & BE2_SET_RESET) {
51 printk(KERN_ERR DRV_NAME
52 " Soft Reset did not deassert\n");
53 return -EIO;
54 }
55 pconline1 = BE2_MPU_IRAM_ONLINE;
56 writel(pconline0, (void *)pci_online0_offset);
57 writel(pconline1, (void *)pci_online1_offset);
58
59 sreset |= BE2_SET_RESET;
60 writel(sreset, (void *)pci_reset_offset);
61
62 i = 0;
63 while (sreset & BE2_SET_RESET) {
64 if (i > 64)
65 break;
66 msleep(1);
67 sreset = readl((void *)pci_reset_offset);
68 i++;
69 }
70 if (sreset & BE2_SET_RESET) {
71 printk(KERN_ERR DRV_NAME
72 " MPU Online Soft Reset did not deassert\n");
73 return -EIO;
74 }
75 return 0;
76 }
77
78 int be_chk_reset_complete(struct beiscsi_hba *phba)
79 {
80 unsigned int num_loop;
81 u8 *mpu_sem = 0;
82 u32 status;
83
84 num_loop = 1000;
85 mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
86 msleep(5000);
87
88 while (num_loop) {
89 status = readl((void *)mpu_sem);
90
91 if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000)
92 break;
93 msleep(60);
94 num_loop--;
95 }
96
97 if ((status & 0x80000000) || (!num_loop)) {
98 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
99 "BC_%d : Failed in be_chk_reset_complete"
100 "status = 0x%x\n", status);
101 return -EIO;
102 }
103
104 return 0;
105 }
106
107 void be_mcc_notify(struct beiscsi_hba *phba)
108 {
109 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
110 u32 val = 0;
111
112 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
113 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
114 iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
115 }
116
117 unsigned int alloc_mcc_tag(struct beiscsi_hba *phba)
118 {
119 unsigned int tag = 0;
120
121 if (phba->ctrl.mcc_tag_available) {
122 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];
123 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;
124 phba->ctrl.mcc_numtag[tag] = 0;
125 }
126 if (tag) {
127 phba->ctrl.mcc_tag_available--;
128 if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1))
129 phba->ctrl.mcc_alloc_index = 0;
130 else
131 phba->ctrl.mcc_alloc_index++;
132 }
133 return tag;
134 }
135
136 /*
137 * beiscsi_mccq_compl()- Wait for completion of MBX
138 * @phba: Driver private structure
139 * @tag: Tag for the MBX Command
140 * @wrb: the WRB used for the MBX Command
141 * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd
142 *
143 * Waits for MBX completion with the passed TAG.
144 *
145 * return
146 * Success: 0
147 * Failure: Non-Zero
148 **/
149 int beiscsi_mccq_compl(struct beiscsi_hba *phba,
150 uint32_t tag, struct be_mcc_wrb **wrb,
151 struct be_dma_mem *mbx_cmd_mem)
152 {
153 int rc = 0;
154 uint32_t mcc_tag_response;
155 uint16_t status = 0, addl_status = 0, wrb_num = 0;
156 struct be_mcc_wrb *temp_wrb;
157 struct be_cmd_req_hdr *mbx_hdr;
158 struct be_cmd_resp_hdr *mbx_resp_hdr;
159 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
160
161 if (beiscsi_error(phba)) {
162 free_mcc_tag(&phba->ctrl, tag);
163 return -EPERM;
164 }
165
166 /* Set MBX Tag state to Active */
167 spin_lock(&phba->ctrl.mbox_lock);
168 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_RUNNING;
169 spin_unlock(&phba->ctrl.mbox_lock);
170
171 /* wait for the mccq completion */
172 rc = wait_event_interruptible_timeout(
173 phba->ctrl.mcc_wait[tag],
174 phba->ctrl.mcc_numtag[tag],
175 msecs_to_jiffies(
176 BEISCSI_HOST_MBX_TIMEOUT));
177
178 if (rc <= 0) {
179 struct be_dma_mem *tag_mem;
180 /* Set MBX Tag state to timeout */
181 spin_lock(&phba->ctrl.mbox_lock);
182 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_TIMEOUT;
183 spin_unlock(&phba->ctrl.mbox_lock);
184
185 /* Store resource addr to be freed later */
186 tag_mem = &phba->ctrl.ptag_state[tag].tag_mem_state;
187 if (mbx_cmd_mem) {
188 tag_mem->size = mbx_cmd_mem->size;
189 tag_mem->va = mbx_cmd_mem->va;
190 tag_mem->dma = mbx_cmd_mem->dma;
191 } else
192 tag_mem->size = 0;
193
194 beiscsi_log(phba, KERN_ERR,
195 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
196 BEISCSI_LOG_CONFIG,
197 "BC_%d : MBX Cmd Completion timed out\n");
198 return -EBUSY;
199 } else {
200 rc = 0;
201 /* Set MBX Tag state to completed */
202 spin_lock(&phba->ctrl.mbox_lock);
203 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_COMPLETED;
204 spin_unlock(&phba->ctrl.mbox_lock);
205 }
206
207 mcc_tag_response = phba->ctrl.mcc_numtag[tag];
208 status = (mcc_tag_response & CQE_STATUS_MASK);
209 addl_status = ((mcc_tag_response & CQE_STATUS_ADDL_MASK) >>
210 CQE_STATUS_ADDL_SHIFT);
211
212 if (mbx_cmd_mem) {
213 mbx_hdr = (struct be_cmd_req_hdr *)mbx_cmd_mem->va;
214 } else {
215 wrb_num = (mcc_tag_response & CQE_STATUS_WRB_MASK) >>
216 CQE_STATUS_WRB_SHIFT;
217 temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num);
218 mbx_hdr = embedded_payload(temp_wrb);
219
220 if (wrb)
221 *wrb = temp_wrb;
222 }
223
224 if (status || addl_status) {
225 beiscsi_log(phba, KERN_WARNING,
226 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
227 BEISCSI_LOG_CONFIG,
228 "BC_%d : MBX Cmd Failed for "
229 "Subsys : %d Opcode : %d with "
230 "Status : %d and Extd_Status : %d\n",
231 mbx_hdr->subsystem,
232 mbx_hdr->opcode,
233 status, addl_status);
234
235 if (status == MCC_STATUS_INSUFFICIENT_BUFFER) {
236 mbx_resp_hdr = (struct be_cmd_resp_hdr *) mbx_hdr;
237 beiscsi_log(phba, KERN_WARNING,
238 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
239 BEISCSI_LOG_CONFIG,
240 "BC_%d : Insufficient Buffer Error "
241 "Resp_Len : %d Actual_Resp_Len : %d\n",
242 mbx_resp_hdr->response_length,
243 mbx_resp_hdr->actual_resp_len);
244
245 rc = -EAGAIN;
246 goto release_mcc_tag;
247 }
248 rc = -EIO;
249 }
250
251 release_mcc_tag:
252 /* Release the MCC entry */
253 free_mcc_tag(&phba->ctrl, tag);
254
255 return rc;
256 }
257
258 void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag)
259 {
260 spin_lock(&ctrl->mbox_lock);
261 tag = tag & 0x000000FF;
262 ctrl->mcc_tag[ctrl->mcc_free_index] = tag;
263 if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))
264 ctrl->mcc_free_index = 0;
265 else
266 ctrl->mcc_free_index++;
267 ctrl->mcc_tag_available++;
268 spin_unlock(&ctrl->mbox_lock);
269 }
270
271 bool is_link_state_evt(u32 trailer)
272 {
273 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
274 ASYNC_TRAILER_EVENT_CODE_MASK) ==
275 ASYNC_EVENT_CODE_LINK_STATE);
276 }
277
278 static bool is_iscsi_evt(u32 trailer)
279 {
280 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
281 ASYNC_TRAILER_EVENT_CODE_MASK) ==
282 ASYNC_EVENT_CODE_ISCSI;
283 }
284
285 static int iscsi_evt_type(u32 trailer)
286 {
287 return (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
288 ASYNC_TRAILER_EVENT_TYPE_MASK;
289 }
290
291 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
292 {
293 if (compl->flags != 0) {
294 compl->flags = le32_to_cpu(compl->flags);
295 WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
296 return true;
297 } else
298 return false;
299 }
300
301 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
302 {
303 compl->flags = 0;
304 }
305
306 /*
307 * be_mcc_compl_process()- Check the MBX comapletion status
308 * @ctrl: Function specific MBX data structure
309 * @compl: Completion status of MBX Command
310 *
311 * Check for the MBX completion status when BMBX method used
312 *
313 * return
314 * Success: Zero
315 * Failure: Non-Zero
316 **/
317 static int be_mcc_compl_process(struct be_ctrl_info *ctrl,
318 struct be_mcc_compl *compl)
319 {
320 u16 compl_status, extd_status;
321 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
322 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
323 struct be_cmd_req_hdr *hdr = embedded_payload(wrb);
324 struct be_cmd_resp_hdr *resp_hdr;
325
326 be_dws_le_to_cpu(compl, 4);
327
328 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
329 CQE_STATUS_COMPL_MASK;
330 if (compl_status != MCC_STATUS_SUCCESS) {
331 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
332 CQE_STATUS_EXTD_MASK;
333
334 beiscsi_log(phba, KERN_ERR,
335 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
336 "BC_%d : error in cmd completion: "
337 "Subsystem : %d Opcode : %d "
338 "status(compl/extd)=%d/%d\n",
339 hdr->subsystem, hdr->opcode,
340 compl_status, extd_status);
341
342 if (compl_status == MCC_STATUS_INSUFFICIENT_BUFFER) {
343 resp_hdr = (struct be_cmd_resp_hdr *) hdr;
344 if (resp_hdr->response_length)
345 return 0;
346 }
347 return -EBUSY;
348 }
349 return 0;
350 }
351
352 int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl,
353 struct be_mcc_compl *compl)
354 {
355 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
356 u16 compl_status, extd_status;
357 unsigned short tag;
358
359 be_dws_le_to_cpu(compl, 4);
360
361 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
362 CQE_STATUS_COMPL_MASK;
363 /* The ctrl.mcc_numtag[tag] is filled with
364 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
365 * [7:0] = compl_status
366 */
367 tag = (compl->tag0 & 0x000000FF);
368 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
369 CQE_STATUS_EXTD_MASK;
370
371 ctrl->mcc_numtag[tag] = 0x80000000;
372 ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000);
373 ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8;
374 ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF);
375
376 if (ctrl->ptag_state[tag].tag_state == MCC_TAG_STATE_RUNNING) {
377 wake_up_interruptible(&ctrl->mcc_wait[tag]);
378 } else if (ctrl->ptag_state[tag].tag_state == MCC_TAG_STATE_TIMEOUT) {
379 struct be_dma_mem *tag_mem;
380 tag_mem = &ctrl->ptag_state[tag].tag_mem_state;
381
382 beiscsi_log(phba, KERN_WARNING,
383 BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT |
384 BEISCSI_LOG_CONFIG,
385 "BC_%d : MBX Completion for timeout Command "
386 "from FW\n");
387 /* Check if memory needs to be freed */
388 if (tag_mem->size)
389 pci_free_consistent(ctrl->pdev, tag_mem->size,
390 tag_mem->va, tag_mem->dma);
391
392 /* Change tag state */
393 spin_lock(&phba->ctrl.mbox_lock);
394 ctrl->ptag_state[tag].tag_state = MCC_TAG_STATE_COMPLETED;
395 spin_unlock(&phba->ctrl.mbox_lock);
396
397 /* Free MCC Tag */
398 free_mcc_tag(ctrl, tag);
399 }
400
401 return 0;
402 }
403
404 static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba)
405 {
406 struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq;
407 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
408
409 if (be_mcc_compl_is_new(compl)) {
410 queue_tail_inc(mcc_cq);
411 return compl;
412 }
413 return NULL;
414 }
415
416 /**
417 * be2iscsi_fail_session(): Closing session with appropriate error
418 * @cls_session: ptr to session
419 *
420 * Depending on adapter state appropriate error flag is passed.
421 **/
422 void be2iscsi_fail_session(struct iscsi_cls_session *cls_session)
423 {
424 struct Scsi_Host *shost = iscsi_session_to_shost(cls_session);
425 struct beiscsi_hba *phba = iscsi_host_priv(shost);
426 uint32_t iscsi_err_flag;
427
428 if (phba->state & BE_ADAPTER_STATE_SHUTDOWN)
429 iscsi_err_flag = ISCSI_ERR_INVALID_HOST;
430 else
431 iscsi_err_flag = ISCSI_ERR_CONN_FAILED;
432
433 iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED);
434 }
435
436 void beiscsi_async_link_state_process(struct beiscsi_hba *phba,
437 struct be_async_event_link_state *evt)
438 {
439 if ((evt->port_link_status == ASYNC_EVENT_LINK_DOWN) ||
440 ((evt->port_link_status & ASYNC_EVENT_LOGICAL) &&
441 (evt->port_fault != BEISCSI_PHY_LINK_FAULT_NONE))) {
442 phba->state = BE_ADAPTER_LINK_DOWN;
443
444 beiscsi_log(phba, KERN_ERR,
445 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
446 "BC_%d : Link Down on Port %d\n",
447 evt->physical_port);
448
449 iscsi_host_for_each_session(phba->shost,
450 be2iscsi_fail_session);
451 } else if ((evt->port_link_status & ASYNC_EVENT_LINK_UP) ||
452 ((evt->port_link_status & ASYNC_EVENT_LOGICAL) &&
453 (evt->port_fault == BEISCSI_PHY_LINK_FAULT_NONE))) {
454 phba->state = BE_ADAPTER_LINK_UP | BE_ADAPTER_CHECK_BOOT;
455 phba->get_boot = BE_GET_BOOT_RETRIES;
456
457 beiscsi_log(phba, KERN_ERR,
458 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
459 "BC_%d : Link UP on Port %d\n",
460 evt->physical_port);
461 }
462 }
463
464 int beiscsi_process_mcc(struct beiscsi_hba *phba)
465 {
466 struct be_mcc_compl *compl;
467 int num = 0, status = 0;
468 struct be_ctrl_info *ctrl = &phba->ctrl;
469
470 spin_lock_bh(&phba->ctrl.mcc_cq_lock);
471 while ((compl = be_mcc_compl_get(phba))) {
472 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
473 /* Interpret flags as an async trailer */
474 if (is_link_state_evt(compl->flags))
475 /* Interpret compl as a async link evt */
476 beiscsi_async_link_state_process(phba,
477 (struct be_async_event_link_state *) compl);
478 else if (is_iscsi_evt(compl->flags)) {
479 switch (iscsi_evt_type(compl->flags)) {
480 case ASYNC_EVENT_NEW_ISCSI_TGT_DISC:
481 case ASYNC_EVENT_NEW_ISCSI_CONN:
482 case ASYNC_EVENT_NEW_TCP_CONN:
483 phba->state |= BE_ADAPTER_CHECK_BOOT;
484 phba->get_boot = BE_GET_BOOT_RETRIES;
485 beiscsi_log(phba, KERN_ERR,
486 BEISCSI_LOG_CONFIG |
487 BEISCSI_LOG_MBOX,
488 "BC_%d : Async iscsi Event,"
489 " flags handled = 0x%08x\n",
490 compl->flags);
491 break;
492 default:
493 phba->state |= BE_ADAPTER_CHECK_BOOT;
494 phba->get_boot = BE_GET_BOOT_RETRIES;
495 beiscsi_log(phba, KERN_ERR,
496 BEISCSI_LOG_CONFIG |
497 BEISCSI_LOG_MBOX,
498 "BC_%d : Unsupported Async"
499 " Event, flags = 0x%08x\n",
500 compl->flags);
501 }
502 } else
503 beiscsi_log(phba, KERN_ERR,
504 BEISCSI_LOG_CONFIG |
505 BEISCSI_LOG_MBOX,
506 "BC_%d : Unsupported Async Event, flags"
507 " = 0x%08x\n", compl->flags);
508
509 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
510 status = be_mcc_compl_process(ctrl, compl);
511 atomic_dec(&phba->ctrl.mcc_obj.q.used);
512 }
513 be_mcc_compl_use(compl);
514 num++;
515 }
516
517 if (num)
518 hwi_ring_cq_db(phba, phba->ctrl.mcc_obj.cq.id, num, 1, 0);
519
520 spin_unlock_bh(&phba->ctrl.mcc_cq_lock);
521 return status;
522 }
523
524 /*
525 * be_mcc_wait_compl()- Wait for MBX completion
526 * @phba: driver private structure
527 *
528 * Wait till no more pending mcc requests are present
529 *
530 * return
531 * Success: 0
532 * Failure: Non-Zero
533 *
534 **/
535 static int be_mcc_wait_compl(struct beiscsi_hba *phba)
536 {
537 int i, status;
538 for (i = 0; i < mcc_timeout; i++) {
539 if (beiscsi_error(phba))
540 return -EIO;
541
542 status = beiscsi_process_mcc(phba);
543 if (status)
544 return status;
545
546 if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0)
547 break;
548 udelay(100);
549 }
550 if (i == mcc_timeout) {
551 beiscsi_log(phba, KERN_ERR,
552 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
553 "BC_%d : FW Timed Out\n");
554 phba->fw_timeout = true;
555 beiscsi_ue_detect(phba);
556 return -EBUSY;
557 }
558 return 0;
559 }
560
561 /*
562 * be_mcc_notify_wait()- Notify and wait for Compl
563 * @phba: driver private structure
564 *
565 * Notify MCC requests and wait for completion
566 *
567 * return
568 * Success: 0
569 * Failure: Non-Zero
570 **/
571 int be_mcc_notify_wait(struct beiscsi_hba *phba)
572 {
573 be_mcc_notify(phba);
574 return be_mcc_wait_compl(phba);
575 }
576
577 /*
578 * be_mbox_db_ready_wait()- Check ready status
579 * @ctrl: Function specific MBX data structure
580 *
581 * Check for the ready status of FW to send BMBX
582 * commands to adapter.
583 *
584 * return
585 * Success: 0
586 * Failure: Non-Zero
587 **/
588 static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl)
589 {
590 #define BEISCSI_MBX_RDY_BIT_TIMEOUT 4000 /* 4sec */
591 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
592 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
593 unsigned long timeout;
594 bool read_flag = false;
595 int ret = 0, i;
596 u32 ready;
597 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(rdybit_check_q);
598
599 if (beiscsi_error(phba))
600 return -EIO;
601
602 timeout = jiffies + (HZ * 110);
603
604 do {
605 for (i = 0; i < BEISCSI_MBX_RDY_BIT_TIMEOUT; i++) {
606 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
607 if (ready) {
608 read_flag = true;
609 break;
610 }
611 mdelay(1);
612 }
613
614 if (!read_flag) {
615 wait_event_timeout(rdybit_check_q,
616 (read_flag != true),
617 HZ * 5);
618 }
619 } while ((time_before(jiffies, timeout)) && !read_flag);
620
621 if (!read_flag) {
622 beiscsi_log(phba, KERN_ERR,
623 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
624 "BC_%d : FW Timed Out\n");
625 phba->fw_timeout = true;
626 beiscsi_ue_detect(phba);
627 ret = -EBUSY;
628 }
629
630 return ret;
631 }
632
633 /*
634 * be_mbox_notify: Notify adapter of new BMBX command
635 * @ctrl: Function specific MBX data structure
636 *
637 * Ring doorbell to inform adapter of a BMBX command
638 * to process
639 *
640 * return
641 * Success: 0
642 * Failure: Non-Zero
643 **/
644 int be_mbox_notify(struct be_ctrl_info *ctrl)
645 {
646 int status;
647 u32 val = 0;
648 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
649 struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
650 struct be_mcc_mailbox *mbox = mbox_mem->va;
651 struct be_mcc_compl *compl = &mbox->compl;
652 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
653
654 status = be_mbox_db_ready_wait(ctrl);
655 if (status)
656 return status;
657
658 val &= ~MPU_MAILBOX_DB_RDY_MASK;
659 val |= MPU_MAILBOX_DB_HI_MASK;
660 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
661 iowrite32(val, db);
662
663 status = be_mbox_db_ready_wait(ctrl);
664 if (status)
665 return status;
666
667 val = 0;
668 val &= ~MPU_MAILBOX_DB_RDY_MASK;
669 val &= ~MPU_MAILBOX_DB_HI_MASK;
670 val |= (u32) (mbox_mem->dma >> 4) << 2;
671 iowrite32(val, db);
672
673 status = be_mbox_db_ready_wait(ctrl);
674 if (status)
675 return status;
676
677 if (be_mcc_compl_is_new(compl)) {
678 status = be_mcc_compl_process(ctrl, &mbox->compl);
679 be_mcc_compl_use(compl);
680 if (status) {
681 beiscsi_log(phba, KERN_ERR,
682 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
683 "BC_%d : After be_mcc_compl_process\n");
684
685 return status;
686 }
687 } else {
688 beiscsi_log(phba, KERN_ERR,
689 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
690 "BC_%d : Invalid Mailbox Completion\n");
691
692 return -EBUSY;
693 }
694 return 0;
695 }
696
697 /*
698 * Insert the mailbox address into the doorbell in two steps
699 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
700 */
701 static int be_mbox_notify_wait(struct beiscsi_hba *phba)
702 {
703 int status;
704 u32 val = 0;
705 void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET;
706 struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem;
707 struct be_mcc_mailbox *mbox = mbox_mem->va;
708 struct be_mcc_compl *compl = &mbox->compl;
709 struct be_ctrl_info *ctrl = &phba->ctrl;
710
711 status = be_mbox_db_ready_wait(ctrl);
712 if (status)
713 return status;
714
715 val |= MPU_MAILBOX_DB_HI_MASK;
716 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
717 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
718 iowrite32(val, db);
719
720 /* wait for ready to be set */
721 status = be_mbox_db_ready_wait(ctrl);
722 if (status != 0)
723 return status;
724
725 val = 0;
726 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
727 val |= (u32)(mbox_mem->dma >> 4) << 2;
728 iowrite32(val, db);
729
730 status = be_mbox_db_ready_wait(ctrl);
731 if (status != 0)
732 return status;
733
734 /* A cq entry has been made now */
735 if (be_mcc_compl_is_new(compl)) {
736 status = be_mcc_compl_process(ctrl, &mbox->compl);
737 be_mcc_compl_use(compl);
738 if (status)
739 return status;
740 } else {
741 beiscsi_log(phba, KERN_ERR,
742 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
743 "BC_%d : invalid mailbox completion\n");
744
745 return -EBUSY;
746 }
747 return 0;
748 }
749
750 void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
751 bool embedded, u8 sge_cnt)
752 {
753 if (embedded)
754 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
755 else
756 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
757 MCC_WRB_SGE_CNT_SHIFT;
758 wrb->payload_length = payload_len;
759 be_dws_cpu_to_le(wrb, 8);
760 }
761
762 void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
763 u8 subsystem, u8 opcode, int cmd_len)
764 {
765 req_hdr->opcode = opcode;
766 req_hdr->subsystem = subsystem;
767 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
768 req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT;
769 }
770
771 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
772 struct be_dma_mem *mem)
773 {
774 int i, buf_pages;
775 u64 dma = (u64) mem->dma;
776
777 buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
778 for (i = 0; i < buf_pages; i++) {
779 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
780 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
781 dma += PAGE_SIZE_4K;
782 }
783 }
784
785 static u32 eq_delay_to_mult(u32 usec_delay)
786 {
787 #define MAX_INTR_RATE 651042
788 const u32 round = 10;
789 u32 multiplier;
790
791 if (usec_delay == 0)
792 multiplier = 0;
793 else {
794 u32 interrupt_rate = 1000000 / usec_delay;
795 if (interrupt_rate == 0)
796 multiplier = 1023;
797 else {
798 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
799 multiplier /= interrupt_rate;
800 multiplier = (multiplier + round / 2) / round;
801 multiplier = min(multiplier, (u32) 1023);
802 }
803 }
804 return multiplier;
805 }
806
807 struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
808 {
809 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
810 }
811
812 struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba)
813 {
814 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
815 struct be_mcc_wrb *wrb;
816
817 WARN_ON(atomic_read(&mccq->used) >= mccq->len);
818 wrb = queue_head_node(mccq);
819 memset(wrb, 0, sizeof(*wrb));
820 wrb->tag0 = (mccq->head & 0x000000FF) << 16;
821 queue_head_inc(mccq);
822 atomic_inc(&mccq->used);
823 return wrb;
824 }
825
826
827 int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
828 struct be_queue_info *eq, int eq_delay)
829 {
830 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
831 struct be_cmd_req_eq_create *req = embedded_payload(wrb);
832 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
833 struct be_dma_mem *q_mem = &eq->dma_mem;
834 int status;
835
836 spin_lock(&ctrl->mbox_lock);
837 memset(wrb, 0, sizeof(*wrb));
838
839 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
840
841 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
842 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
843
844 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
845
846 AMAP_SET_BITS(struct amap_eq_context, func, req->context,
847 PCI_FUNC(ctrl->pdev->devfn));
848 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
849 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
850 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
851 __ilog2_u32(eq->len / 256));
852 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
853 eq_delay_to_mult(eq_delay));
854 be_dws_cpu_to_le(req->context, sizeof(req->context));
855
856 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
857
858 status = be_mbox_notify(ctrl);
859 if (!status) {
860 eq->id = le16_to_cpu(resp->eq_id);
861 eq->created = true;
862 }
863 spin_unlock(&ctrl->mbox_lock);
864 return status;
865 }
866
867 /**
868 * be_cmd_fw_initialize()- Initialize FW
869 * @ctrl: Pointer to function control structure
870 *
871 * Send FW initialize pattern for the function.
872 *
873 * return
874 * Success: 0
875 * Failure: Non-Zero value
876 **/
877 int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
878 {
879 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
880 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
881 int status;
882 u8 *endian_check;
883
884 spin_lock(&ctrl->mbox_lock);
885 memset(wrb, 0, sizeof(*wrb));
886
887 endian_check = (u8 *) wrb;
888 *endian_check++ = 0xFF;
889 *endian_check++ = 0x12;
890 *endian_check++ = 0x34;
891 *endian_check++ = 0xFF;
892 *endian_check++ = 0xFF;
893 *endian_check++ = 0x56;
894 *endian_check++ = 0x78;
895 *endian_check++ = 0xFF;
896 be_dws_cpu_to_le(wrb, sizeof(*wrb));
897
898 status = be_mbox_notify(ctrl);
899 if (status)
900 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
901 "BC_%d : be_cmd_fw_initialize Failed\n");
902
903 spin_unlock(&ctrl->mbox_lock);
904 return status;
905 }
906
907 /**
908 * be_cmd_fw_uninit()- Uinitialize FW
909 * @ctrl: Pointer to function control structure
910 *
911 * Send FW uninitialize pattern for the function
912 *
913 * return
914 * Success: 0
915 * Failure: Non-Zero value
916 **/
917 int be_cmd_fw_uninit(struct be_ctrl_info *ctrl)
918 {
919 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
920 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
921 int status;
922 u8 *endian_check;
923
924 spin_lock(&ctrl->mbox_lock);
925 memset(wrb, 0, sizeof(*wrb));
926
927 endian_check = (u8 *) wrb;
928 *endian_check++ = 0xFF;
929 *endian_check++ = 0xAA;
930 *endian_check++ = 0xBB;
931 *endian_check++ = 0xFF;
932 *endian_check++ = 0xFF;
933 *endian_check++ = 0xCC;
934 *endian_check++ = 0xDD;
935 *endian_check = 0xFF;
936
937 be_dws_cpu_to_le(wrb, sizeof(*wrb));
938
939 status = be_mbox_notify(ctrl);
940 if (status)
941 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
942 "BC_%d : be_cmd_fw_uninit Failed\n");
943
944 spin_unlock(&ctrl->mbox_lock);
945 return status;
946 }
947
948 int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
949 struct be_queue_info *cq, struct be_queue_info *eq,
950 bool sol_evts, bool no_delay, int coalesce_wm)
951 {
952 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
953 struct be_cmd_req_cq_create *req = embedded_payload(wrb);
954 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
955 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
956 struct be_dma_mem *q_mem = &cq->dma_mem;
957 void *ctxt = &req->context;
958 int status;
959
960 spin_lock(&ctrl->mbox_lock);
961 memset(wrb, 0, sizeof(*wrb));
962
963 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
964
965 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
966 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
967
968 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
969 if (is_chip_be2_be3r(phba)) {
970 AMAP_SET_BITS(struct amap_cq_context, coalescwm,
971 ctxt, coalesce_wm);
972 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
973 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
974 __ilog2_u32(cq->len / 256));
975 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
976 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
977 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
978 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
979 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
980 AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
981 PCI_FUNC(ctrl->pdev->devfn));
982 } else {
983 req->hdr.version = MBX_CMD_VER2;
984 req->page_size = 1;
985 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
986 ctxt, coalesce_wm);
987 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay,
988 ctxt, no_delay);
989 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
990 __ilog2_u32(cq->len / 256));
991 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
992 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
993 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
994 AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1);
995 }
996
997 be_dws_cpu_to_le(ctxt, sizeof(req->context));
998
999 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1000
1001 status = be_mbox_notify(ctrl);
1002 if (!status) {
1003 cq->id = le16_to_cpu(resp->cq_id);
1004 cq->created = true;
1005 } else
1006 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1007 "BC_%d : In be_cmd_cq_create, status=ox%08x\n",
1008 status);
1009
1010 spin_unlock(&ctrl->mbox_lock);
1011
1012 return status;
1013 }
1014
1015 static u32 be_encoded_q_len(int q_len)
1016 {
1017 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1018 if (len_encoded == 16)
1019 len_encoded = 0;
1020 return len_encoded;
1021 }
1022
1023 int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
1024 struct be_queue_info *mccq,
1025 struct be_queue_info *cq)
1026 {
1027 struct be_mcc_wrb *wrb;
1028 struct be_cmd_req_mcc_create *req;
1029 struct be_dma_mem *q_mem = &mccq->dma_mem;
1030 struct be_ctrl_info *ctrl;
1031 void *ctxt;
1032 int status;
1033
1034 spin_lock(&phba->ctrl.mbox_lock);
1035 ctrl = &phba->ctrl;
1036 wrb = wrb_from_mbox(&ctrl->mbox_mem);
1037 memset(wrb, 0, sizeof(*wrb));
1038 req = embedded_payload(wrb);
1039 ctxt = &req->context;
1040
1041 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1042
1043 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1044 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
1045
1046 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1047
1048 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
1049 PCI_FUNC(phba->pcidev->devfn));
1050 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
1051 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
1052 be_encoded_q_len(mccq->len));
1053 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
1054
1055 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1056
1057 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1058
1059 status = be_mbox_notify_wait(phba);
1060 if (!status) {
1061 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1062 mccq->id = le16_to_cpu(resp->id);
1063 mccq->created = true;
1064 }
1065 spin_unlock(&phba->ctrl.mbox_lock);
1066
1067 return status;
1068 }
1069
1070 int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
1071 int queue_type)
1072 {
1073 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1074 struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
1075 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1076 u8 subsys = 0, opcode = 0;
1077 int status;
1078
1079 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1080 "BC_%d : In beiscsi_cmd_q_destroy "
1081 "queue_type : %d\n", queue_type);
1082
1083 spin_lock(&ctrl->mbox_lock);
1084 memset(wrb, 0, sizeof(*wrb));
1085 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1086
1087 switch (queue_type) {
1088 case QTYPE_EQ:
1089 subsys = CMD_SUBSYSTEM_COMMON;
1090 opcode = OPCODE_COMMON_EQ_DESTROY;
1091 break;
1092 case QTYPE_CQ:
1093 subsys = CMD_SUBSYSTEM_COMMON;
1094 opcode = OPCODE_COMMON_CQ_DESTROY;
1095 break;
1096 case QTYPE_MCCQ:
1097 subsys = CMD_SUBSYSTEM_COMMON;
1098 opcode = OPCODE_COMMON_MCC_DESTROY;
1099 break;
1100 case QTYPE_WRBQ:
1101 subsys = CMD_SUBSYSTEM_ISCSI;
1102 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
1103 break;
1104 case QTYPE_DPDUQ:
1105 subsys = CMD_SUBSYSTEM_ISCSI;
1106 opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
1107 break;
1108 case QTYPE_SGL:
1109 subsys = CMD_SUBSYSTEM_ISCSI;
1110 opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
1111 break;
1112 default:
1113 spin_unlock(&ctrl->mbox_lock);
1114 BUG();
1115 return -ENXIO;
1116 }
1117 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
1118 if (queue_type != QTYPE_SGL)
1119 req->id = cpu_to_le16(q->id);
1120
1121 status = be_mbox_notify(ctrl);
1122
1123 spin_unlock(&ctrl->mbox_lock);
1124 return status;
1125 }
1126
1127 /**
1128 * be_cmd_create_default_pdu_queue()- Create DEFQ for the adapter
1129 * @ctrl: ptr to ctrl_info
1130 * @cq: Completion Queue
1131 * @dq: Default Queue
1132 * @lenght: ring size
1133 * @entry_size: size of each entry in DEFQ
1134 * @is_header: Header or Data DEFQ
1135 * @ulp_num: Bind to which ULP
1136 *
1137 * Create HDR/Data DEFQ for the passed ULP. Unsol PDU are posted
1138 * on this queue by the FW
1139 *
1140 * return
1141 * Success: 0
1142 * Failure: Non-Zero Value
1143 *
1144 **/
1145 int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
1146 struct be_queue_info *cq,
1147 struct be_queue_info *dq, int length,
1148 int entry_size, uint8_t is_header,
1149 uint8_t ulp_num)
1150 {
1151 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1152 struct be_defq_create_req *req = embedded_payload(wrb);
1153 struct be_dma_mem *q_mem = &dq->dma_mem;
1154 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1155 void *ctxt = &req->context;
1156 int status;
1157
1158 spin_lock(&ctrl->mbox_lock);
1159 memset(wrb, 0, sizeof(*wrb));
1160
1161 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1162
1163 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1164 OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
1165
1166 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1167 if (phba->fw_config.dual_ulp_aware) {
1168 req->ulp_num = ulp_num;
1169 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1170 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1171 }
1172
1173 if (is_chip_be2_be3r(phba)) {
1174 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1175 rx_pdid, ctxt, 0);
1176 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1177 rx_pdid_valid, ctxt, 1);
1178 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1179 pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn));
1180 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1181 ring_size, ctxt,
1182 be_encoded_q_len(length /
1183 sizeof(struct phys_addr)));
1184 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1185 default_buffer_size, ctxt, entry_size);
1186 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1187 cq_id_recv, ctxt, cq->id);
1188 } else {
1189 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1190 rx_pdid, ctxt, 0);
1191 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1192 rx_pdid_valid, ctxt, 1);
1193 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1194 ring_size, ctxt,
1195 be_encoded_q_len(length /
1196 sizeof(struct phys_addr)));
1197 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1198 default_buffer_size, ctxt, entry_size);
1199 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1200 cq_id_recv, ctxt, cq->id);
1201 }
1202
1203 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1204
1205 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1206
1207 status = be_mbox_notify(ctrl);
1208 if (!status) {
1209 struct be_ring *defq_ring;
1210 struct be_defq_create_resp *resp = embedded_payload(wrb);
1211
1212 dq->id = le16_to_cpu(resp->id);
1213 dq->created = true;
1214 if (is_header)
1215 defq_ring = &phba->phwi_ctrlr->default_pdu_hdr[ulp_num];
1216 else
1217 defq_ring = &phba->phwi_ctrlr->
1218 default_pdu_data[ulp_num];
1219
1220 defq_ring->id = dq->id;
1221
1222 if (!phba->fw_config.dual_ulp_aware) {
1223 defq_ring->ulp_num = BEISCSI_ULP0;
1224 defq_ring->doorbell_offset = DB_RXULP0_OFFSET;
1225 } else {
1226 defq_ring->ulp_num = resp->ulp_num;
1227 defq_ring->doorbell_offset = resp->doorbell_offset;
1228 }
1229 }
1230 spin_unlock(&ctrl->mbox_lock);
1231
1232 return status;
1233 }
1234
1235 /**
1236 * be_cmd_wrbq_create()- Create WRBQ
1237 * @ctrl: ptr to ctrl_info
1238 * @q_mem: memory details for the queue
1239 * @wrbq: queue info
1240 * @pwrb_context: ptr to wrb_context
1241 * @ulp_num: ULP on which the WRBQ is to be created
1242 *
1243 * Create WRBQ on the passed ULP_NUM.
1244 *
1245 **/
1246 int be_cmd_wrbq_create(struct be_ctrl_info *ctrl,
1247 struct be_dma_mem *q_mem,
1248 struct be_queue_info *wrbq,
1249 struct hwi_wrb_context *pwrb_context,
1250 uint8_t ulp_num)
1251 {
1252 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1253 struct be_wrbq_create_req *req = embedded_payload(wrb);
1254 struct be_wrbq_create_resp *resp = embedded_payload(wrb);
1255 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1256 int status;
1257
1258 spin_lock(&ctrl->mbox_lock);
1259 memset(wrb, 0, sizeof(*wrb));
1260
1261 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1262
1263 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1264 OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
1265 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1266
1267 if (phba->fw_config.dual_ulp_aware) {
1268 req->ulp_num = ulp_num;
1269 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1270 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1271 }
1272
1273 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1274
1275 status = be_mbox_notify(ctrl);
1276 if (!status) {
1277 wrbq->id = le16_to_cpu(resp->cid);
1278 wrbq->created = true;
1279
1280 pwrb_context->cid = wrbq->id;
1281 if (!phba->fw_config.dual_ulp_aware) {
1282 pwrb_context->doorbell_offset = DB_TXULP0_OFFSET;
1283 pwrb_context->ulp_num = BEISCSI_ULP0;
1284 } else {
1285 pwrb_context->ulp_num = resp->ulp_num;
1286 pwrb_context->doorbell_offset = resp->doorbell_offset;
1287 }
1288 }
1289 spin_unlock(&ctrl->mbox_lock);
1290 return status;
1291 }
1292
1293 int be_cmd_iscsi_post_template_hdr(struct be_ctrl_info *ctrl,
1294 struct be_dma_mem *q_mem)
1295 {
1296 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1297 struct be_post_template_pages_req *req = embedded_payload(wrb);
1298 int status;
1299
1300 spin_lock(&ctrl->mbox_lock);
1301
1302 memset(wrb, 0, sizeof(*wrb));
1303 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1304 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1305 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS,
1306 sizeof(*req));
1307
1308 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1309 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1310 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1311
1312 status = be_mbox_notify(ctrl);
1313 spin_unlock(&ctrl->mbox_lock);
1314 return status;
1315 }
1316
1317 int be_cmd_iscsi_remove_template_hdr(struct be_ctrl_info *ctrl)
1318 {
1319 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1320 struct be_remove_template_pages_req *req = embedded_payload(wrb);
1321 int status;
1322
1323 spin_lock(&ctrl->mbox_lock);
1324
1325 memset(wrb, 0, sizeof(*wrb));
1326 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1327 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1328 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS,
1329 sizeof(*req));
1330
1331 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1332
1333 status = be_mbox_notify(ctrl);
1334 spin_unlock(&ctrl->mbox_lock);
1335 return status;
1336 }
1337
1338 int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
1339 struct be_dma_mem *q_mem,
1340 u32 page_offset, u32 num_pages)
1341 {
1342 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1343 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
1344 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1345 int status;
1346 unsigned int curr_pages;
1347 u32 internal_page_offset = 0;
1348 u32 temp_num_pages = num_pages;
1349
1350 if (num_pages == 0xff)
1351 num_pages = 1;
1352
1353 spin_lock(&ctrl->mbox_lock);
1354 do {
1355 memset(wrb, 0, sizeof(*wrb));
1356 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1357 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1358 OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
1359 sizeof(*req));
1360 curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
1361 pages);
1362 req->num_pages = min(num_pages, curr_pages);
1363 req->page_offset = page_offset;
1364 be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
1365 q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
1366 internal_page_offset += req->num_pages;
1367 page_offset += req->num_pages;
1368 num_pages -= req->num_pages;
1369
1370 if (temp_num_pages == 0xff)
1371 req->num_pages = temp_num_pages;
1372
1373 status = be_mbox_notify(ctrl);
1374 if (status) {
1375 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1376 "BC_%d : FW CMD to map iscsi frags failed.\n");
1377
1378 goto error;
1379 }
1380 } while (num_pages > 0);
1381 error:
1382 spin_unlock(&ctrl->mbox_lock);
1383 if (status != 0)
1384 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
1385 return status;
1386 }
1387
1388 int beiscsi_cmd_reset_function(struct beiscsi_hba *phba)
1389 {
1390 struct be_ctrl_info *ctrl = &phba->ctrl;
1391 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1392 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
1393 int status;
1394
1395 spin_lock(&ctrl->mbox_lock);
1396
1397 req = embedded_payload(wrb);
1398 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1399 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1400 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1401 status = be_mbox_notify_wait(phba);
1402
1403 spin_unlock(&ctrl->mbox_lock);
1404 return status;
1405 }
1406
1407 /**
1408 * be_cmd_set_vlan()- Configure VLAN paramters on the adapter
1409 * @phba: device priv structure instance
1410 * @vlan_tag: TAG to be set
1411 *
1412 * Set the VLAN_TAG for the adapter or Disable VLAN on adapter
1413 *
1414 * returns
1415 * TAG for the MBX Cmd
1416 * **/
1417 int be_cmd_set_vlan(struct beiscsi_hba *phba,
1418 uint16_t vlan_tag)
1419 {
1420 unsigned int tag = 0;
1421 struct be_mcc_wrb *wrb;
1422 struct be_cmd_set_vlan_req *req;
1423 struct be_ctrl_info *ctrl = &phba->ctrl;
1424
1425 spin_lock(&ctrl->mbox_lock);
1426 tag = alloc_mcc_tag(phba);
1427 if (!tag) {
1428 spin_unlock(&ctrl->mbox_lock);
1429 return tag;
1430 }
1431
1432 wrb = wrb_from_mccq(phba);
1433 req = embedded_payload(wrb);
1434 wrb->tag0 |= tag;
1435 be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0);
1436 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1437 OPCODE_COMMON_ISCSI_NTWK_SET_VLAN,
1438 sizeof(*req));
1439
1440 req->interface_hndl = phba->interface_handle;
1441 req->vlan_priority = vlan_tag;
1442
1443 be_mcc_notify(phba);
1444 spin_unlock(&ctrl->mbox_lock);
1445
1446 return tag;
1447 }
Linux with added FPC-III support