drivers/video/fbdev/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #include <linux/interrupt.h>
  27
  28 #ifdef pr_fmt
  29 #undef pr_fmt
  30 #endif
  31
  32 #ifdef DSS_SUBSYS_NAME
  33 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
  34 #else
  35 #define pr_fmt(fmt) fmt
  36 #endif
  37
  38 #define DSSDBG(format, ...) \
  39         pr_debug(format, ## __VA_ARGS__)
  40
  41 #ifdef DSS_SUBSYS_NAME
  42 #define DSSERR(format, ...) \
  43         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  44         ## __VA_ARGS__)
  45 #else
  46 #define DSSERR(format, ...) \
  47         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  48 #endif
  49
  50 #ifdef DSS_SUBSYS_NAME
  51 #define DSSINFO(format, ...) \
  52         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  53         ## __VA_ARGS__)
  54 #else
  55 #define DSSINFO(format, ...) \
  56         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  57 #endif
  58
  59 #ifdef DSS_SUBSYS_NAME
  60 #define DSSWARN(format, ...) \
  61         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  62         ## __VA_ARGS__)
  63 #else
  64 #define DSSWARN(format, ...) \
  65         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  66 #endif
  67
  68 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  69    number. For example 7:0 */
  70 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  71 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  72 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  73 #define FLD_MOD(orig, val, start, end) \
  74         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  75
  76 enum dss_io_pad_mode {
  77         DSS_IO_PAD_MODE_RESET,
  78         DSS_IO_PAD_MODE_RFBI,
  79         DSS_IO_PAD_MODE_BYPASS,
  80 };
  81
  82 enum dss_hdmi_venc_clk_source_select {
  83         DSS_VENC_TV_CLK = 0,
  84         DSS_HDMI_M_PCLK = 1,
  85 };
  86
  87 enum dss_dsi_content_type {
  88         DSS_DSI_CONTENT_DCS,
  89         DSS_DSI_CONTENT_GENERIC,
  90 };
  91
  92 enum dss_writeback_channel {
  93         DSS_WB_LCD1_MGR =       0,
  94         DSS_WB_LCD2_MGR =       1,
  95         DSS_WB_TV_MGR =         2,
  96         DSS_WB_OVL0 =           3,
  97         DSS_WB_OVL1 =           4,
  98         DSS_WB_OVL2 =           5,
  99         DSS_WB_OVL3 =           6,
 100         DSS_WB_LCD3_MGR =       7,
 101 };
 102
 103 enum dss_pll_id {
 104         DSS_PLL_DSI1,
 105         DSS_PLL_DSI2,
 106         DSS_PLL_HDMI,
 107         DSS_PLL_VIDEO1,
 108         DSS_PLL_VIDEO2,
 109 };
 110
 111 struct dss_pll;
 112
 113 #define DSS_PLL_MAX_HSDIVS 4
 114
 115 /*
 116  * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
 117  * Type-B PLLs: clkout[0] refers to m2.
 118  */
 119 struct dss_pll_clock_info {
 120         /* rates that we get with dividers below */
 121         unsigned long fint;
 122         unsigned long clkdco;
 123         unsigned long clkout[DSS_PLL_MAX_HSDIVS];
 124
 125         /* dividers */
 126         u16 n;
 127         u16 m;
 128         u32 mf;
 129         u16 mX[DSS_PLL_MAX_HSDIVS];
 130         u16 sd;
 131 };
 132
 133 struct dss_pll_ops {
 134         int (*enable)(struct dss_pll *pll);
 135         void (*disable)(struct dss_pll *pll);
 136         int (*set_config)(struct dss_pll *pll,
 137                 const struct dss_pll_clock_info *cinfo);
 138 };
 139
 140 struct dss_pll_hw {
 141         unsigned n_max;
 142         unsigned m_min;
 143         unsigned m_max;
 144         unsigned mX_max;
 145
 146         unsigned long fint_min, fint_max;
 147         unsigned long clkdco_min, clkdco_low, clkdco_max;
 148
 149         u8 n_msb, n_lsb;
 150         u8 m_msb, m_lsb;
 151         u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
 152
 153         bool has_stopmode;
 154         bool has_freqsel;
 155         bool has_selfreqdco;
 156         bool has_refsel;
 157 };
 158
 159 struct dss_pll {
 160         const char *name;
 161         enum dss_pll_id id;
 162
 163         struct clk *clkin;
 164         struct regulator *regulator;
 165
 166         void __iomem *base;
 167
 168         const struct dss_pll_hw *hw;
 169
 170         const struct dss_pll_ops *ops;
 171
 172         struct dss_pll_clock_info cinfo;
 173 };
 174
 175 struct dispc_clock_info {
 176         /* rates that we get with dividers below */
 177         unsigned long lck;
 178         unsigned long pck;
 179
 180         /* dividers */
 181         u16 lck_div;
 182         u16 pck_div;
 183 };
 184
 185 struct dss_lcd_mgr_config {
 186         enum dss_io_pad_mode io_pad_mode;
 187
 188         bool stallmode;
 189         bool fifohandcheck;
 190
 191         struct dispc_clock_info clock_info;
 192
 193         int video_port_width;
 194
 195         int lcden_sig_polarity;
 196 };
 197
 198 struct seq_file;
 199 struct platform_device;
 200
 201 /* core */
 202 struct platform_device *dss_get_core_pdev(void);
 203 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
 204 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
 205 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
 206 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
 207
 208 /* display */
 209 int dss_suspend_all_devices(void);
 210 int dss_resume_all_devices(void);
 211 void dss_disable_all_devices(void);
 212
 213 int display_init_sysfs(struct platform_device *pdev);
 214 void display_uninit_sysfs(struct platform_device *pdev);
 215
 216 /* manager */
 217 int dss_init_overlay_managers(void);
 218 void dss_uninit_overlay_managers(void);
 219 int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
 220 void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
 221 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
 222                 const struct omap_overlay_manager_info *info);
 223 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
 224                 const struct omap_video_timings *timings);
 225 int dss_mgr_check(struct omap_overlay_manager *mgr,
 226                 struct omap_overlay_manager_info *info,
 227                 const struct omap_video_timings *mgr_timings,
 228                 const struct dss_lcd_mgr_config *config,
 229                 struct omap_overlay_info **overlay_infos);
 230
 231 static inline bool dss_mgr_is_lcd(enum omap_channel id)
 232 {
 233         if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
 234                         id == OMAP_DSS_CHANNEL_LCD3)
 235                 return true;
 236         else
 237                 return false;
 238 }
 239
 240 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
 241                 struct platform_device *pdev);
 242 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
 243
 244 /* overlay */
 245 void dss_init_overlays(struct platform_device *pdev);
 246 void dss_uninit_overlays(struct platform_device *pdev);
 247 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 248 int dss_ovl_simple_check(struct omap_overlay *ovl,
 249                 const struct omap_overlay_info *info);
 250 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
 251                 const struct omap_video_timings *mgr_timings);
 252 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
 253                 enum omap_color_mode mode);
 254 int dss_overlay_kobj_init(struct omap_overlay *ovl,
 255                 struct platform_device *pdev);
 256 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
 257
 258 /* DSS */
 259 int dss_init_platform_driver(void) __init;
 260 void dss_uninit_platform_driver(void);
 261
 262 int dss_runtime_get(void);
 263 void dss_runtime_put(void);
 264
 265 unsigned long dss_get_dispc_clk_rate(void);
 266 int dss_dpi_select_source(int port, enum omap_channel channel);
 267 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 268 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
 269 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 270 void dss_dump_clocks(struct seq_file *s);
 271
 272 /* DSS VIDEO PLL */
 273 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
 274         struct regulator *regulator);
 275 void dss_video_pll_uninit(struct dss_pll *pll);
 276
 277 /* dss-of */
 278 struct device_node *dss_of_port_get_parent_device(struct device_node *port);
 279 u32 dss_of_port_get_port_number(struct device_node *port);
 280
 281 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 282 void dss_debug_dump_clocks(struct seq_file *s);
 283 #endif
 284
 285 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
 286 void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
 287         enum omap_channel channel);
 288
 289 void dss_sdi_init(int datapairs);
 290 int dss_sdi_enable(void);
 291 void dss_sdi_disable(void);
 292
 293 void dss_select_dsi_clk_source(int dsi_module,
 294                 enum omap_dss_clk_source clk_src);
 295 void dss_select_lcd_clk_source(enum omap_channel channel,
 296                 enum omap_dss_clk_source clk_src);
 297 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 298 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 299 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 300
 301 void dss_set_venc_output(enum omap_dss_venc_type type);
 302 void dss_set_dac_pwrdn_bgz(bool enable);
 303
 304 int dss_set_fck_rate(unsigned long rate);
 305
 306 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
 307 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
 308                 dss_div_calc_func func, void *data);
 309
 310 /* SDI */
 311 int sdi_init_platform_driver(void) __init;
 312 void sdi_uninit_platform_driver(void);
 313
 314 #ifdef CONFIG_OMAP2_DSS_SDI
 315 int sdi_init_port(struct platform_device *pdev, struct device_node *port);
 316 void sdi_uninit_port(struct device_node *port);
 317 #else
 318 static inline int sdi_init_port(struct platform_device *pdev,
 319                 struct device_node *port)
 320 {
 321         return 0;
 322 }
 323 static inline void sdi_uninit_port(struct device_node *port)
 324 {
 325 }
 326 #endif
 327
 328 /* DSI */
 329
 330 #ifdef CONFIG_OMAP2_DSS_DSI
 331
 332 struct dentry;
 333 struct file_operations;
 334
 335 int dsi_init_platform_driver(void) __init;
 336 void dsi_uninit_platform_driver(void);
 337
 338 void dsi_dump_clocks(struct seq_file *s);
 339
 340 void dsi_irq_handler(void);
 341 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
 342
 343 #else
 344 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 345 {
 346         WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
 347         return 0;
 348 }
 349 #endif
 350
 351 /* DPI */
 352 int dpi_init_platform_driver(void) __init;
 353 void dpi_uninit_platform_driver(void);
 354
 355 #ifdef CONFIG_OMAP2_DSS_DPI
 356 int dpi_init_port(struct platform_device *pdev, struct device_node *port);
 357 void dpi_uninit_port(struct device_node *port);
 358 #else
 359 static inline int dpi_init_port(struct platform_device *pdev,
 360                 struct device_node *port)
 361 {
 362         return 0;
 363 }
 364 static inline void dpi_uninit_port(struct device_node *port)
 365 {
 366 }
 367 #endif
 368
 369 /* DISPC */
 370 int dispc_init_platform_driver(void) __init;
 371 void dispc_uninit_platform_driver(void);
 372 void dispc_dump_clocks(struct seq_file *s);
 373
 374 void dispc_enable_sidle(void);
 375 void dispc_disable_sidle(void);
 376
 377 void dispc_lcd_enable_signal(bool enable);
 378 void dispc_pck_free_enable(bool enable);
 379 void dispc_enable_fifomerge(bool enable);
 380 void dispc_enable_gamma_table(bool enable);
 381 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 382
 383 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
 384                 unsigned long pck, void *data);
 385 bool dispc_div_calc(unsigned long dispc,
 386                 unsigned long pck_min, unsigned long pck_max,
 387                 dispc_div_calc_func func, void *data);
 388
 389 bool dispc_mgr_timings_ok(enum omap_channel channel,
 390                 const struct omap_video_timings *timings);
 391 unsigned long dispc_fclk_rate(void);
 392 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 393                 struct dispc_clock_info *cinfo);
 394
 395
 396 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 397 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
 398                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
 399                 bool manual_update);
 400
 401 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 402 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 403 unsigned long dispc_core_clk_rate(void);
 404 void dispc_mgr_set_clock_div(enum omap_channel channel,
 405                 const struct dispc_clock_info *cinfo);
 406 int dispc_mgr_get_clock_div(enum omap_channel channel,
 407                 struct dispc_clock_info *cinfo);
 408 void dispc_set_tv_pclk(unsigned long pclk);
 409
 410 u32 dispc_wb_get_framedone_irq(void);
 411 bool dispc_wb_go_busy(void);
 412 void dispc_wb_go(void);
 413 void dispc_wb_enable(bool enable);
 414 bool dispc_wb_is_enabled(void);
 415 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
 416 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
 417                 bool mem_to_mem, const struct omap_video_timings *timings);
 418
 419 /* VENC */
 420 int venc_init_platform_driver(void) __init;
 421 void venc_uninit_platform_driver(void);
 422
 423 /* HDMI */
 424 int hdmi4_init_platform_driver(void) __init;
 425 void hdmi4_uninit_platform_driver(void);
 426
 427 int hdmi5_init_platform_driver(void) __init;
 428 void hdmi5_uninit_platform_driver(void);
 429
 430 /* RFBI */
 431 int rfbi_init_platform_driver(void) __init;
 432 void rfbi_uninit_platform_driver(void);
 433
 434
 435 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 436 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 437 {
 438         int b;
 439         for (b = 0; b < 32; ++b) {
 440                 if (irqstatus & (1 << b))
 441                         irq_arr[b]++;
 442         }
 443 }
 444 #endif
 445
 446 /* PLL */
 447 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
 448                 unsigned long clkdco, void *data);
 449 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
 450                 void *data);
 451
 452 int dss_pll_register(struct dss_pll *pll);
 453 void dss_pll_unregister(struct dss_pll *pll);
 454 struct dss_pll *dss_pll_find(const char *name);
 455 int dss_pll_enable(struct dss_pll *pll);
 456 void dss_pll_disable(struct dss_pll *pll);
 457 int dss_pll_set_config(struct dss_pll *pll,
 458                 const struct dss_pll_clock_info *cinfo);
 459
 460 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
 461                 unsigned long out_min, unsigned long out_max,
 462                 dss_hsdiv_calc_func func, void *data);
 463 bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
 464                 unsigned long pll_min, unsigned long pll_max,
 465                 dss_pll_calc_func func, void *data);
 466 int dss_pll_write_config_type_a(struct dss_pll *pll,
 467                 const struct dss_pll_clock_info *cinfo);
 468 int dss_pll_write_config_type_b(struct dss_pll *pll,
 469                 const struct dss_pll_clock_info *cinfo);
 470 int dss_pll_wait_reset_done(struct dss_pll *pll);
 471
 472 #endif