?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
of: MSI: Simplify irqdomain lookup
[linux/fpc-iii.git] / drivers / video / fbdev / omap2 / dss / venc.c
blobd05a54922ba6953bb686f07ba2ac4315f91aeace
1 /*
2 * linux/drivers/video/omap2/dss/venc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * VENC settings from TI's DSS driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #define DSS_SUBSYS_NAME "VENC"
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/io.h>
29 #include <linux/mutex.h>
30 #include <linux/completion.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/seq_file.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/of.h>
38 #include <linux/component.h>
39
40 #include <video/omapdss.h>
41
42 #include "dss.h"
43 #include "dss_features.h"
44
45 /* Venc registers */
46 #define VENC_REV_ID 0x00
47 #define VENC_STATUS 0x04
48 #define VENC_F_CONTROL 0x08
49 #define VENC_VIDOUT_CTRL 0x10
50 #define VENC_SYNC_CTRL 0x14
51 #define VENC_LLEN 0x1C
52 #define VENC_FLENS 0x20
53 #define VENC_HFLTR_CTRL 0x24
54 #define VENC_CC_CARR_WSS_CARR 0x28
55 #define VENC_C_PHASE 0x2C
56 #define VENC_GAIN_U 0x30
57 #define VENC_GAIN_V 0x34
58 #define VENC_GAIN_Y 0x38
59 #define VENC_BLACK_LEVEL 0x3C
60 #define VENC_BLANK_LEVEL 0x40
61 #define VENC_X_COLOR 0x44
62 #define VENC_M_CONTROL 0x48
63 #define VENC_BSTAMP_WSS_DATA 0x4C
64 #define VENC_S_CARR 0x50
65 #define VENC_LINE21 0x54
66 #define VENC_LN_SEL 0x58
67 #define VENC_L21__WC_CTL 0x5C
68 #define VENC_HTRIGGER_VTRIGGER 0x60
69 #define VENC_SAVID__EAVID 0x64
70 #define VENC_FLEN__FAL 0x68
71 #define VENC_LAL__PHASE_RESET 0x6C
72 #define VENC_HS_INT_START_STOP_X 0x70
73 #define VENC_HS_EXT_START_STOP_X 0x74
74 #define VENC_VS_INT_START_X 0x78
75 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
76 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
77 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
78 #define VENC_VS_EXT_STOP_Y 0x88
79 #define VENC_AVID_START_STOP_X 0x90
80 #define VENC_AVID_START_STOP_Y 0x94
81 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
82 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
83 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
84 #define VENC_TVDETGP_INT_START_STOP_X 0xB0
85 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
86 #define VENC_GEN_CTRL 0xB8
87 #define VENC_OUTPUT_CONTROL 0xC4
88 #define VENC_OUTPUT_TEST 0xC8
89 #define VENC_DAC_B__DAC_C 0xC8
90
91 struct venc_config {
92 u32 f_control;
93 u32 vidout_ctrl;
94 u32 sync_ctrl;
95 u32 llen;
96 u32 flens;
97 u32 hfltr_ctrl;
98 u32 cc_carr_wss_carr;
99 u32 c_phase;
100 u32 gain_u;
101 u32 gain_v;
102 u32 gain_y;
103 u32 black_level;
104 u32 blank_level;
105 u32 x_color;
106 u32 m_control;
107 u32 bstamp_wss_data;
108 u32 s_carr;
109 u32 line21;
110 u32 ln_sel;
111 u32 l21__wc_ctl;
112 u32 htrigger_vtrigger;
113 u32 savid__eavid;
114 u32 flen__fal;
115 u32 lal__phase_reset;
116 u32 hs_int_start_stop_x;
117 u32 hs_ext_start_stop_x;
118 u32 vs_int_start_x;
119 u32 vs_int_stop_x__vs_int_start_y;
120 u32 vs_int_stop_y__vs_ext_start_x;
121 u32 vs_ext_stop_x__vs_ext_start_y;
122 u32 vs_ext_stop_y;
123 u32 avid_start_stop_x;
124 u32 avid_start_stop_y;
125 u32 fid_int_start_x__fid_int_start_y;
126 u32 fid_int_offset_y__fid_ext_start_x;
127 u32 fid_ext_start_y__fid_ext_offset_y;
128 u32 tvdetgp_int_start_stop_x;
129 u32 tvdetgp_int_start_stop_y;
130 u32 gen_ctrl;
131 };
132
133 /* from TRM */
134 static const struct venc_config venc_config_pal_trm = {
135 .f_control = 0,
136 .vidout_ctrl = 1,
137 .sync_ctrl = 0x40,
138 .llen = 0x35F, /* 863 */
139 .flens = 0x270, /* 624 */
140 .hfltr_ctrl = 0,
141 .cc_carr_wss_carr = 0x2F7225ED,
142 .c_phase = 0,
143 .gain_u = 0x111,
144 .gain_v = 0x181,
145 .gain_y = 0x140,
146 .black_level = 0x3B,
147 .blank_level = 0x3B,
148 .x_color = 0x7,
149 .m_control = 0x2,
150 .bstamp_wss_data = 0x3F,
151 .s_carr = 0x2A098ACB,
152 .line21 = 0,
153 .ln_sel = 0x01290015,
154 .l21__wc_ctl = 0x0000F603,
155 .htrigger_vtrigger = 0,
156
157 .savid__eavid = 0x06A70108,
158 .flen__fal = 0x00180270,
159 .lal__phase_reset = 0x00040135,
160 .hs_int_start_stop_x = 0x00880358,
161 .hs_ext_start_stop_x = 0x000F035F,
162 .vs_int_start_x = 0x01A70000,
163 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
164 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
165 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
166 .vs_ext_stop_y = 0x00000025,
167 .avid_start_stop_x = 0x03530083,
168 .avid_start_stop_y = 0x026C002E,
169 .fid_int_start_x__fid_int_start_y = 0x0001008A,
170 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
171 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
172
173 .tvdetgp_int_start_stop_x = 0x00140001,
174 .tvdetgp_int_start_stop_y = 0x00010001,
175 .gen_ctrl = 0x00FF0000,
176 };
177
178 /* from TRM */
179 static const struct venc_config venc_config_ntsc_trm = {
180 .f_control = 0,
181 .vidout_ctrl = 1,
182 .sync_ctrl = 0x8040,
183 .llen = 0x359,
184 .flens = 0x20C,
185 .hfltr_ctrl = 0,
186 .cc_carr_wss_carr = 0x043F2631,
187 .c_phase = 0,
188 .gain_u = 0x102,
189 .gain_v = 0x16C,
190 .gain_y = 0x12F,
191 .black_level = 0x43,
192 .blank_level = 0x38,
193 .x_color = 0x7,
194 .m_control = 0x1,
195 .bstamp_wss_data = 0x38,
196 .s_carr = 0x21F07C1F,
197 .line21 = 0,
198 .ln_sel = 0x01310011,
199 .l21__wc_ctl = 0x0000F003,
200 .htrigger_vtrigger = 0,
201
202 .savid__eavid = 0x069300F4,
203 .flen__fal = 0x0016020C,
204 .lal__phase_reset = 0x00060107,
205 .hs_int_start_stop_x = 0x008E0350,
206 .hs_ext_start_stop_x = 0x000F0359,
207 .vs_int_start_x = 0x01A00000,
208 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
209 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
210 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
211 .vs_ext_stop_y = 0x00000006,
212 .avid_start_stop_x = 0x03480078,
213 .avid_start_stop_y = 0x02060024,
214 .fid_int_start_x__fid_int_start_y = 0x0001008A,
215 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
216 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
217
218 .tvdetgp_int_start_stop_x = 0x00140001,
219 .tvdetgp_int_start_stop_y = 0x00010001,
220 .gen_ctrl = 0x00F90000,
221 };
222
223 static const struct venc_config venc_config_pal_bdghi = {
224 .f_control = 0,
225 .vidout_ctrl = 0,
226 .sync_ctrl = 0,
227 .hfltr_ctrl = 0,
228 .x_color = 0,
229 .line21 = 0,
230 .ln_sel = 21,
231 .htrigger_vtrigger = 0,
232 .tvdetgp_int_start_stop_x = 0x00140001,
233 .tvdetgp_int_start_stop_y = 0x00010001,
234 .gen_ctrl = 0x00FB0000,
235
236 .llen = 864-1,
237 .flens = 625-1,
238 .cc_carr_wss_carr = 0x2F7625ED,
239 .c_phase = 0xDF,
240 .gain_u = 0x111,
241 .gain_v = 0x181,
242 .gain_y = 0x140,
243 .black_level = 0x3e,
244 .blank_level = 0x3e,
245 .m_control = 0<<2 | 1<<1,
246 .bstamp_wss_data = 0x42,
247 .s_carr = 0x2a098acb,
248 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
249 .savid__eavid = 0x06A70108,
250 .flen__fal = 23<<16 | 624<<0,
251 .lal__phase_reset = 2<<17 | 310<<0,
252 .hs_int_start_stop_x = 0x00920358,
253 .hs_ext_start_stop_x = 0x000F035F,
254 .vs_int_start_x = 0x1a7<<16,
255 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
256 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
257 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
258 .vs_ext_stop_y = 0x05,
259 .avid_start_stop_x = 0x03530082,
260 .avid_start_stop_y = 0x0270002E,
261 .fid_int_start_x__fid_int_start_y = 0x0005008A,
262 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
263 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
264 };
265
266 const struct omap_video_timings omap_dss_pal_timings = {
267 .x_res = 720,
268 .y_res = 574,
269 .pixelclock = 13500000,
270 .hsw = 64,
271 .hfp = 12,
272 .hbp = 68,
273 .vsw = 5,
274 .vfp = 5,
275 .vbp = 41,
276
277 .interlace = true,
278
279 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
280 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
281 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
282 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
283 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
284 };
285 EXPORT_SYMBOL(omap_dss_pal_timings);
286
287 const struct omap_video_timings omap_dss_ntsc_timings = {
288 .x_res = 720,
289 .y_res = 482,
290 .pixelclock = 13500000,
291 .hsw = 64,
292 .hfp = 16,
293 .hbp = 58,
294 .vsw = 6,
295 .vfp = 6,
296 .vbp = 31,
297
298 .interlace = true,
299
300 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
301 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
302 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
303 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
304 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
305 };
306 EXPORT_SYMBOL(omap_dss_ntsc_timings);
307
308 static struct {
309 struct platform_device *pdev;
310 void __iomem *base;
311 struct mutex venc_lock;
312 u32 wss_data;
313 struct regulator *vdda_dac_reg;
314
315 struct clk *tv_dac_clk;
316
317 struct omap_video_timings timings;
318 enum omap_dss_venc_type type;
319 bool invert_polarity;
320
321 struct omap_dss_device output;
322 } venc;
323
324 static inline void venc_write_reg(int idx, u32 val)
325 {
326 __raw_writel(val, venc.base + idx);
327 }
328
329 static inline u32 venc_read_reg(int idx)
330 {
331 u32 l = __raw_readl(venc.base + idx);
332 return l;
333 }
334
335 static void venc_write_config(const struct venc_config *config)
336 {
337 DSSDBG("write venc conf\n");
338
339 venc_write_reg(VENC_LLEN, config->llen);
340 venc_write_reg(VENC_FLENS, config->flens);
341 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
342 venc_write_reg(VENC_C_PHASE, config->c_phase);
343 venc_write_reg(VENC_GAIN_U, config->gain_u);
344 venc_write_reg(VENC_GAIN_V, config->gain_v);
345 venc_write_reg(VENC_GAIN_Y, config->gain_y);
346 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
347 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
348 venc_write_reg(VENC_M_CONTROL, config->m_control);
349 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
350 venc.wss_data);
351 venc_write_reg(VENC_S_CARR, config->s_carr);
352 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
353 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
354 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
355 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
356 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
357 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
358 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
359 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
360 config->vs_int_stop_x__vs_int_start_y);
361 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
362 config->vs_int_stop_y__vs_ext_start_x);
363 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
364 config->vs_ext_stop_x__vs_ext_start_y);
365 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
366 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
367 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
368 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
369 config->fid_int_start_x__fid_int_start_y);
370 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
371 config->fid_int_offset_y__fid_ext_start_x);
372 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
373 config->fid_ext_start_y__fid_ext_offset_y);
374
375 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
376 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
377 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
378 venc_write_reg(VENC_X_COLOR, config->x_color);
379 venc_write_reg(VENC_LINE21, config->line21);
380 venc_write_reg(VENC_LN_SEL, config->ln_sel);
381 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
382 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
383 config->tvdetgp_int_start_stop_x);
384 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
385 config->tvdetgp_int_start_stop_y);
386 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
387 venc_write_reg(VENC_F_CONTROL, config->f_control);
388 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
389 }
390
391 static void venc_reset(void)
392 {
393 int t = 1000;
394
395 venc_write_reg(VENC_F_CONTROL, 1<<8);
396 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
397 if (--t == 0) {
398 DSSERR("Failed to reset venc\n");
399 return;
400 }
401 }
402
403 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
404 /* the magical sleep that makes things work */
405 /* XXX more info? What bug this circumvents? */
406 msleep(20);
407 #endif
408 }
409
410 static int venc_runtime_get(void)
411 {
412 int r;
413
414 DSSDBG("venc_runtime_get\n");
415
416 r = pm_runtime_get_sync(&venc.pdev->dev);
417 WARN_ON(r < 0);
418 return r < 0 ? r : 0;
419 }
420
421 static void venc_runtime_put(void)
422 {
423 int r;
424
425 DSSDBG("venc_runtime_put\n");
426
427 r = pm_runtime_put_sync(&venc.pdev->dev);
428 WARN_ON(r < 0 && r != -ENOSYS);
429 }
430
431 static const struct venc_config *venc_timings_to_config(
432 struct omap_video_timings *timings)
433 {
434 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
435 return &venc_config_pal_trm;
436
437 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
438 return &venc_config_ntsc_trm;
439
440 BUG();
441 return NULL;
442 }
443
444 static int venc_power_on(struct omap_dss_device *dssdev)
445 {
446 struct omap_overlay_manager *mgr = venc.output.manager;
447 u32 l;
448 int r;
449
450 r = venc_runtime_get();
451 if (r)
452 goto err0;
453
454 venc_reset();
455 venc_write_config(venc_timings_to_config(&venc.timings));
456
457 dss_set_venc_output(venc.type);
458 dss_set_dac_pwrdn_bgz(1);
459
460 l = 0;
461
462 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
463 l |= 1 << 1;
464 else /* S-Video */
465 l |= (1 << 0) | (1 << 2);
466
467 if (venc.invert_polarity == false)
468 l |= 1 << 3;
469
470 venc_write_reg(VENC_OUTPUT_CONTROL, l);
471
472 dss_mgr_set_timings(mgr, &venc.timings);
473
474 r = regulator_enable(venc.vdda_dac_reg);
475 if (r)
476 goto err1;
477
478 r = dss_mgr_enable(mgr);
479 if (r)
480 goto err2;
481
482 return 0;
483
484 err2:
485 regulator_disable(venc.vdda_dac_reg);
486 err1:
487 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
488 dss_set_dac_pwrdn_bgz(0);
489
490 venc_runtime_put();
491 err0:
492 return r;
493 }
494
495 static void venc_power_off(struct omap_dss_device *dssdev)
496 {
497 struct omap_overlay_manager *mgr = venc.output.manager;
498
499 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
500 dss_set_dac_pwrdn_bgz(0);
501
502 dss_mgr_disable(mgr);
503
504 regulator_disable(venc.vdda_dac_reg);
505
506 venc_runtime_put();
507 }
508
509 static int venc_display_enable(struct omap_dss_device *dssdev)
510 {
511 struct omap_dss_device *out = &venc.output;
512 int r;
513
514 DSSDBG("venc_display_enable\n");
515
516 mutex_lock(&venc.venc_lock);
517
518 if (out == NULL || out->manager == NULL) {
519 DSSERR("Failed to enable display: no output/manager\n");
520 r = -ENODEV;
521 goto err0;
522 }
523
524 r = venc_power_on(dssdev);
525 if (r)
526 goto err0;
527
528 venc.wss_data = 0;
529
530 mutex_unlock(&venc.venc_lock);
531
532 return 0;
533 err0:
534 mutex_unlock(&venc.venc_lock);
535 return r;
536 }
537
538 static void venc_display_disable(struct omap_dss_device *dssdev)
539 {
540 DSSDBG("venc_display_disable\n");
541
542 mutex_lock(&venc.venc_lock);
543
544 venc_power_off(dssdev);
545
546 mutex_unlock(&venc.venc_lock);
547 }
548
549 static void venc_set_timings(struct omap_dss_device *dssdev,
550 struct omap_video_timings *timings)
551 {
552 DSSDBG("venc_set_timings\n");
553
554 mutex_lock(&venc.venc_lock);
555
556 /* Reset WSS data when the TV standard changes. */
557 if (memcmp(&venc.timings, timings, sizeof(*timings)))
558 venc.wss_data = 0;
559
560 venc.timings = *timings;
561
562 dispc_set_tv_pclk(13500000);
563
564 mutex_unlock(&venc.venc_lock);
565 }
566
567 static int venc_check_timings(struct omap_dss_device *dssdev,
568 struct omap_video_timings *timings)
569 {
570 DSSDBG("venc_check_timings\n");
571
572 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
573 return 0;
574
575 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
576 return 0;
577
578 return -EINVAL;
579 }
580
581 static void venc_get_timings(struct omap_dss_device *dssdev,
582 struct omap_video_timings *timings)
583 {
584 mutex_lock(&venc.venc_lock);
585
586 *timings = venc.timings;
587
588 mutex_unlock(&venc.venc_lock);
589 }
590
591 static u32 venc_get_wss(struct omap_dss_device *dssdev)
592 {
593 /* Invert due to VENC_L21_WC_CTL:INV=1 */
594 return (venc.wss_data >> 8) ^ 0xfffff;
595 }
596
597 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
598 {
599 const struct venc_config *config;
600 int r;
601
602 DSSDBG("venc_set_wss\n");
603
604 mutex_lock(&venc.venc_lock);
605
606 config = venc_timings_to_config(&venc.timings);
607
608 /* Invert due to VENC_L21_WC_CTL:INV=1 */
609 venc.wss_data = (wss ^ 0xfffff) << 8;
610
611 r = venc_runtime_get();
612 if (r)
613 goto err;
614
615 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
616 venc.wss_data);
617
618 venc_runtime_put();
619
620 err:
621 mutex_unlock(&venc.venc_lock);
622
623 return r;
624 }
625
626 static void venc_set_type(struct omap_dss_device *dssdev,
627 enum omap_dss_venc_type type)
628 {
629 mutex_lock(&venc.venc_lock);
630
631 venc.type = type;
632
633 mutex_unlock(&venc.venc_lock);
634 }
635
636 static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
637 bool invert_polarity)
638 {
639 mutex_lock(&venc.venc_lock);
640
641 venc.invert_polarity = invert_polarity;
642
643 mutex_unlock(&venc.venc_lock);
644 }
645
646 static int venc_init_regulator(void)
647 {
648 struct regulator *vdda_dac;
649
650 if (venc.vdda_dac_reg != NULL)
651 return 0;
652
653 if (venc.pdev->dev.of_node)
654 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda");
655 else
656 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");
657
658 if (IS_ERR(vdda_dac)) {
659 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
660 DSSERR("can't get VDDA_DAC regulator\n");
661 return PTR_ERR(vdda_dac);
662 }
663
664 venc.vdda_dac_reg = vdda_dac;
665
666 return 0;
667 }
668
669 static void venc_dump_regs(struct seq_file *s)
670 {
671 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
672
673 if (venc_runtime_get())
674 return;
675
676 DUMPREG(VENC_F_CONTROL);
677 DUMPREG(VENC_VIDOUT_CTRL);
678 DUMPREG(VENC_SYNC_CTRL);
679 DUMPREG(VENC_LLEN);
680 DUMPREG(VENC_FLENS);
681 DUMPREG(VENC_HFLTR_CTRL);
682 DUMPREG(VENC_CC_CARR_WSS_CARR);
683 DUMPREG(VENC_C_PHASE);
684 DUMPREG(VENC_GAIN_U);
685 DUMPREG(VENC_GAIN_V);
686 DUMPREG(VENC_GAIN_Y);
687 DUMPREG(VENC_BLACK_LEVEL);
688 DUMPREG(VENC_BLANK_LEVEL);
689 DUMPREG(VENC_X_COLOR);
690 DUMPREG(VENC_M_CONTROL);
691 DUMPREG(VENC_BSTAMP_WSS_DATA);
692 DUMPREG(VENC_S_CARR);
693 DUMPREG(VENC_LINE21);
694 DUMPREG(VENC_LN_SEL);
695 DUMPREG(VENC_L21__WC_CTL);
696 DUMPREG(VENC_HTRIGGER_VTRIGGER);
697 DUMPREG(VENC_SAVID__EAVID);
698 DUMPREG(VENC_FLEN__FAL);
699 DUMPREG(VENC_LAL__PHASE_RESET);
700 DUMPREG(VENC_HS_INT_START_STOP_X);
701 DUMPREG(VENC_HS_EXT_START_STOP_X);
702 DUMPREG(VENC_VS_INT_START_X);
703 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
704 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
705 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
706 DUMPREG(VENC_VS_EXT_STOP_Y);
707 DUMPREG(VENC_AVID_START_STOP_X);
708 DUMPREG(VENC_AVID_START_STOP_Y);
709 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
710 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
711 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
712 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
713 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
714 DUMPREG(VENC_GEN_CTRL);
715 DUMPREG(VENC_OUTPUT_CONTROL);
716 DUMPREG(VENC_OUTPUT_TEST);
717
718 venc_runtime_put();
719
720 #undef DUMPREG
721 }
722
723 static int venc_get_clocks(struct platform_device *pdev)
724 {
725 struct clk *clk;
726
727 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
728 clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
729 if (IS_ERR(clk)) {
730 DSSERR("can't get tv_dac_clk\n");
731 return PTR_ERR(clk);
732 }
733 } else {
734 clk = NULL;
735 }
736
737 venc.tv_dac_clk = clk;
738
739 return 0;
740 }
741
742 static int venc_connect(struct omap_dss_device *dssdev,
743 struct omap_dss_device *dst)
744 {
745 struct omap_overlay_manager *mgr;
746 int r;
747
748 r = venc_init_regulator();
749 if (r)
750 return r;
751
752 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
753 if (!mgr)
754 return -ENODEV;
755
756 r = dss_mgr_connect(mgr, dssdev);
757 if (r)
758 return r;
759
760 r = omapdss_output_set_device(dssdev, dst);
761 if (r) {
762 DSSERR("failed to connect output to new device: %s\n",
763 dst->name);
764 dss_mgr_disconnect(mgr, dssdev);
765 return r;
766 }
767
768 return 0;
769 }
770
771 static void venc_disconnect(struct omap_dss_device *dssdev,
772 struct omap_dss_device *dst)
773 {
774 WARN_ON(dst != dssdev->dst);
775
776 if (dst != dssdev->dst)
777 return;
778
779 omapdss_output_unset_device(dssdev);
780
781 if (dssdev->manager)
782 dss_mgr_disconnect(dssdev->manager, dssdev);
783 }
784
785 static const struct omapdss_atv_ops venc_ops = {
786 .connect = venc_connect,
787 .disconnect = venc_disconnect,
788
789 .enable = venc_display_enable,
790 .disable = venc_display_disable,
791
792 .check_timings = venc_check_timings,
793 .set_timings = venc_set_timings,
794 .get_timings = venc_get_timings,
795
796 .set_type = venc_set_type,
797 .invert_vid_out_polarity = venc_invert_vid_out_polarity,
798
799 .set_wss = venc_set_wss,
800 .get_wss = venc_get_wss,
801 };
802
803 static void venc_init_output(struct platform_device *pdev)
804 {
805 struct omap_dss_device *out = &venc.output;
806
807 out->dev = &pdev->dev;
808 out->id = OMAP_DSS_OUTPUT_VENC;
809 out->output_type = OMAP_DISPLAY_TYPE_VENC;
810 out->name = "venc.0";
811 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
812 out->ops.atv = &venc_ops;
813 out->owner = THIS_MODULE;
814
815 omapdss_register_output(out);
816 }
817
818 static void venc_uninit_output(struct platform_device *pdev)
819 {
820 struct omap_dss_device *out = &venc.output;
821
822 omapdss_unregister_output(out);
823 }
824
825 static int venc_probe_of(struct platform_device *pdev)
826 {
827 struct device_node *node = pdev->dev.of_node;
828 struct device_node *ep;
829 u32 channels;
830 int r;
831
832 ep = omapdss_of_get_first_endpoint(node);
833 if (!ep)
834 return 0;
835
836 venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
837
838 r = of_property_read_u32(ep, "ti,channels", &channels);
839 if (r) {
840 dev_err(&pdev->dev,
841 "failed to read property 'ti,channels': %d\n", r);
842 goto err;
843 }
844
845 switch (channels) {
846 case 1:
847 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
848 break;
849 case 2:
850 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
851 break;
852 default:
853 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels);
854 r = -EINVAL;
855 goto err;
856 }
857
858 of_node_put(ep);
859
860 return 0;
861 err:
862 of_node_put(ep);
863
864 return 0;
865 }
866
867 /* VENC HW IP initialisation */
868 static int venc_bind(struct device *dev, struct device *master, void *data)
869 {
870 struct platform_device *pdev = to_platform_device(dev);
871 u8 rev_id;
872 struct resource *venc_mem;
873 int r;
874
875 venc.pdev = pdev;
876
877 mutex_init(&venc.venc_lock);
878
879 venc.wss_data = 0;
880
881 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
882 if (!venc_mem) {
883 DSSERR("can't get IORESOURCE_MEM VENC\n");
884 return -EINVAL;
885 }
886
887 venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
888 resource_size(venc_mem));
889 if (!venc.base) {
890 DSSERR("can't ioremap VENC\n");
891 return -ENOMEM;
892 }
893
894 r = venc_get_clocks(pdev);
895 if (r)
896 return r;
897
898 pm_runtime_enable(&pdev->dev);
899
900 r = venc_runtime_get();
901 if (r)
902 goto err_runtime_get;
903
904 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
905 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
906
907 venc_runtime_put();
908
909 if (pdev->dev.of_node) {
910 r = venc_probe_of(pdev);
911 if (r) {
912 DSSERR("Invalid DT data\n");
913 goto err_probe_of;
914 }
915 }
916
917 dss_debugfs_create_file("venc", venc_dump_regs);
918
919 venc_init_output(pdev);
920
921 return 0;
922
923 err_probe_of:
924 err_runtime_get:
925 pm_runtime_disable(&pdev->dev);
926 return r;
927 }
928
929 static void venc_unbind(struct device *dev, struct device *master, void *data)
930 {
931 struct platform_device *pdev = to_platform_device(dev);
932
933 venc_uninit_output(pdev);
934
935 pm_runtime_disable(&pdev->dev);
936 }
937
938 static const struct component_ops venc_component_ops = {
939 .bind = venc_bind,
940 .unbind = venc_unbind,
941 };
942
943 static int venc_probe(struct platform_device *pdev)
944 {
945 return component_add(&pdev->dev, &venc_component_ops);
946 }
947
948 static int venc_remove(struct platform_device *pdev)
949 {
950 component_del(&pdev->dev, &venc_component_ops);
951 return 0;
952 }
953
954 static int venc_runtime_suspend(struct device *dev)
955 {
956 if (venc.tv_dac_clk)
957 clk_disable_unprepare(venc.tv_dac_clk);
958
959 dispc_runtime_put();
960
961 return 0;
962 }
963
964 static int venc_runtime_resume(struct device *dev)
965 {
966 int r;
967
968 r = dispc_runtime_get();
969 if (r < 0)
970 return r;
971
972 if (venc.tv_dac_clk)
973 clk_prepare_enable(venc.tv_dac_clk);
974
975 return 0;
976 }
977
978 static const struct dev_pm_ops venc_pm_ops = {
979 .runtime_suspend = venc_runtime_suspend,
980 .runtime_resume = venc_runtime_resume,
981 };
982
983 static const struct of_device_id venc_of_match[] = {
984 { .compatible = "ti,omap2-venc", },
985 { .compatible = "ti,omap3-venc", },
986 { .compatible = "ti,omap4-venc", },
987 {},
988 };
989
990 static struct platform_driver omap_venchw_driver = {
991 .probe = venc_probe,
992 .remove = venc_remove,
993 .driver = {
994 .name = "omapdss_venc",
995 .pm = &venc_pm_ops,
996 .of_match_table = venc_of_match,
997 .suppress_bind_attrs = true,
998 },
999 };
1000
1001 int __init venc_init_platform_driver(void)
1002 {
1003 return platform_driver_register(&omap_venchw_driver);
1004 }
1005
1006 void venc_uninit_platform_driver(void)
1007 {
1008 platform_driver_unregister(&omap_venchw_driver);
1009 }
Linux with added FPC-III support