include/uapi/drm/nouveau_drm.h

   1 /*
   2  * Copyright 2005 Stephane Marchesin.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #ifndef __NOUVEAU_DRM_H__
  26 #define __NOUVEAU_DRM_H__
  27
  28 #define DRM_NOUVEAU_EVENT_NVIF                                       0x80000000
  29
  30 #define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
  31 #define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
  32 #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
  33 #define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
  34 #define NOUVEAU_GEM_DOMAIN_COHERENT  (1 << 4)
  35
  36 #define NOUVEAU_GEM_TILE_COMP        0x00030000 /* nv50-only */
  37 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
  38 #define NOUVEAU_GEM_TILE_16BPP       0x00000001
  39 #define NOUVEAU_GEM_TILE_32BPP       0x00000002
  40 #define NOUVEAU_GEM_TILE_ZETA        0x00000004
  41 #define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008
  42
  43 struct drm_nouveau_gem_info {
  44         uint32_t handle;
  45         uint32_t domain;
  46         uint64_t size;
  47         uint64_t offset;
  48         uint64_t map_handle;
  49         uint32_t tile_mode;
  50         uint32_t tile_flags;
  51 };
  52
  53 struct drm_nouveau_gem_new {
  54         struct drm_nouveau_gem_info info;
  55         uint32_t channel_hint;
  56         uint32_t align;
  57 };
  58
  59 #define NOUVEAU_GEM_MAX_BUFFERS 1024
  60 struct drm_nouveau_gem_pushbuf_bo_presumed {
  61         uint32_t valid;
  62         uint32_t domain;
  63         uint64_t offset;
  64 };
  65
  66 struct drm_nouveau_gem_pushbuf_bo {
  67         uint64_t user_priv;
  68         uint32_t handle;
  69         uint32_t read_domains;
  70         uint32_t write_domains;
  71         uint32_t valid_domains;
  72         struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
  73 };
  74
  75 #define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
  76 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
  77 #define NOUVEAU_GEM_RELOC_OR   (1 << 2)
  78 #define NOUVEAU_GEM_MAX_RELOCS 1024
  79 struct drm_nouveau_gem_pushbuf_reloc {
  80         uint32_t reloc_bo_index;
  81         uint32_t reloc_bo_offset;
  82         uint32_t bo_index;
  83         uint32_t flags;
  84         uint32_t data;
  85         uint32_t vor;
  86         uint32_t tor;
  87 };
  88
  89 #define NOUVEAU_GEM_MAX_PUSH 512
  90 struct drm_nouveau_gem_pushbuf_push {
  91         uint32_t bo_index;
  92         uint32_t pad;
  93         uint64_t offset;
  94         uint64_t length;
  95 };
  96
  97 struct drm_nouveau_gem_pushbuf {
  98         uint32_t channel;
  99         uint32_t nr_buffers;
 100         uint64_t buffers;
 101         uint32_t nr_relocs;
 102         uint32_t nr_push;
 103         uint64_t relocs;
 104         uint64_t push;
 105         uint32_t suffix0;
 106         uint32_t suffix1;
 107         uint64_t vram_available;
 108         uint64_t gart_available;
 109 };
 110
 111 #define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
 112 #define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
 113 struct drm_nouveau_gem_cpu_prep {
 114         uint32_t handle;
 115         uint32_t flags;
 116 };
 117
 118 struct drm_nouveau_gem_cpu_fini {
 119         uint32_t handle;
 120 };
 121
 122 #define DRM_NOUVEAU_GETPARAM           0x00 /* deprecated */
 123 #define DRM_NOUVEAU_SETPARAM           0x01 /* deprecated */
 124 #define DRM_NOUVEAU_CHANNEL_ALLOC      0x02 /* deprecated */
 125 #define DRM_NOUVEAU_CHANNEL_FREE       0x03 /* deprecated */
 126 #define DRM_NOUVEAU_GROBJ_ALLOC        0x04 /* deprecated */
 127 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05 /* deprecated */
 128 #define DRM_NOUVEAU_GPUOBJ_FREE        0x06 /* deprecated */
 129 #define DRM_NOUVEAU_NVIF               0x07
 130 #define DRM_NOUVEAU_GEM_NEW            0x40
 131 #define DRM_NOUVEAU_GEM_PUSHBUF        0x41
 132 #define DRM_NOUVEAU_GEM_CPU_PREP       0x42
 133 #define DRM_NOUVEAU_GEM_CPU_FINI       0x43
 134 #define DRM_NOUVEAU_GEM_INFO           0x44
 135
 136 #define DRM_IOCTL_NOUVEAU_GEM_NEW            DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
 137 #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF        DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
 138 #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
 139 #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
 140 #define DRM_IOCTL_NOUVEAU_GEM_INFO           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
 141
 142 #endif /* __NOUVEAU_DRM_H__ */