tools/arch/sh/include/asm/barrier.h

   1 /*
   2  * Copied from the kernel sources:
   3  *
   4  * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
   5  * Copyright (C) 2002 Paul Mundt
   6  */
   7 #ifndef __TOOLS_LINUX_ASM_SH_BARRIER_H
   8 #define __TOOLS_LINUX_ASM_SH_BARRIER_H
   9
  10 /*
  11  * A brief note on ctrl_barrier(), the control register write barrier.
  12  *
  13  * Legacy SH cores typically require a sequence of 8 nops after
  14  * modification of a control register in order for the changes to take
  15  * effect. On newer cores (like the sh4a and sh5) this is accomplished
  16  * with icbi.
  17  *
  18  * Also note that on sh4a in the icbi case we can forego a synco for the
  19  * write barrier, as it's not necessary for control registers.
  20  *
  21  * Historically we have only done this type of barrier for the MMUCR, but
  22  * it's also necessary for the CCR, so we make it generic here instead.
  23  */
  24 #if defined(__SH4A__) || defined(__SH5__)
  25 #define mb()            __asm__ __volatile__ ("synco": : :"memory")
  26 #define rmb()           mb()
  27 #define wmb()           mb()
  28 #endif
  29
  30 #include <asm-generic/barrier.h>
  31
  32 #endif /* __TOOLS_LINUX_ASM_SH_BARRIER_H */