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powerpc/powernv: Report size of OPAL memcons log
[linux/fpc-iii.git] / drivers / net / ethernet / mellanox / mlxsw / spectrum.c
blob003093abb1707f0a6cdefe465e073c005d2ee3f9
1 /*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/pci.h>
41 #include <linux/netdevice.h>
42 #include <linux/etherdevice.h>
43 #include <linux/ethtool.h>
44 #include <linux/slab.h>
45 #include <linux/device.h>
46 #include <linux/skbuff.h>
47 #include <linux/if_vlan.h>
48 #include <linux/if_bridge.h>
49 #include <linux/workqueue.h>
50 #include <linux/jiffies.h>
51 #include <linux/bitops.h>
52 #include <linux/list.h>
53 #include <linux/notifier.h>
54 #include <linux/dcbnl.h>
55 #include <linux/inetdevice.h>
56 #include <net/switchdev.h>
57 #include <net/pkt_cls.h>
58 #include <net/tc_act/tc_mirred.h>
59 #include <net/netevent.h>
60
61 #include "spectrum.h"
62 #include "pci.h"
63 #include "core.h"
64 #include "reg.h"
65 #include "port.h"
66 #include "trap.h"
67 #include "txheader.h"
68
69 static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
70 static const char mlxsw_sp_driver_version[] = "1.0";
71
72 /* tx_hdr_version
73 * Tx header version.
74 * Must be set to 1.
75 */
76 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
77
78 /* tx_hdr_ctl
79 * Packet control type.
80 * 0 - Ethernet control (e.g. EMADs, LACP)
81 * 1 - Ethernet data
82 */
83 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
84
85 /* tx_hdr_proto
86 * Packet protocol type. Must be set to 1 (Ethernet).
87 */
88 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
89
90 /* tx_hdr_rx_is_router
91 * Packet is sent from the router. Valid for data packets only.
92 */
93 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
94
95 /* tx_hdr_fid_valid
96 * Indicates if the 'fid' field is valid and should be used for
97 * forwarding lookup. Valid for data packets only.
98 */
99 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
100
101 /* tx_hdr_swid
102 * Switch partition ID. Must be set to 0.
103 */
104 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
105
106 /* tx_hdr_control_tclass
107 * Indicates if the packet should use the control TClass and not one
108 * of the data TClasses.
109 */
110 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
111
112 /* tx_hdr_etclass
113 * Egress TClass to be used on the egress device on the egress port.
114 */
115 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
116
117 /* tx_hdr_port_mid
118 * Destination local port for unicast packets.
119 * Destination multicast ID for multicast packets.
120 *
121 * Control packets are directed to a specific egress port, while data
122 * packets are transmitted through the CPU port (0) into the switch partition,
123 * where forwarding rules are applied.
124 */
125 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
126
127 /* tx_hdr_fid
128 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
129 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
130 * Valid for data packets only.
131 */
132 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
133
134 /* tx_hdr_type
135 * 0 - Data packets
136 * 6 - Control packets
137 */
138 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
139
140 static bool mlxsw_sp_port_dev_check(const struct net_device *dev);
141
142 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
143 const struct mlxsw_tx_info *tx_info)
144 {
145 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
146
147 memset(txhdr, 0, MLXSW_TXHDR_LEN);
148
149 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
150 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
151 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
152 mlxsw_tx_hdr_swid_set(txhdr, 0);
153 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
154 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
155 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
156 }
157
158 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
159 {
160 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
161 int err;
162
163 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
164 if (err)
165 return err;
166 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
167 return 0;
168 }
169
170 static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
171 {
172 int i;
173
174 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
175 return -EIO;
176
177 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
178 MAX_SPAN);
179 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
180 sizeof(struct mlxsw_sp_span_entry),
181 GFP_KERNEL);
182 if (!mlxsw_sp->span.entries)
183 return -ENOMEM;
184
185 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
186 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
187
188 return 0;
189 }
190
191 static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
192 {
193 int i;
194
195 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
196 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
197
198 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
199 }
200 kfree(mlxsw_sp->span.entries);
201 }
202
203 static struct mlxsw_sp_span_entry *
204 mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
205 {
206 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
207 struct mlxsw_sp_span_entry *span_entry;
208 char mpat_pl[MLXSW_REG_MPAT_LEN];
209 u8 local_port = port->local_port;
210 int index;
211 int i;
212 int err;
213
214 /* find a free entry to use */
215 index = -1;
216 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
217 if (!mlxsw_sp->span.entries[i].used) {
218 index = i;
219 span_entry = &mlxsw_sp->span.entries[i];
220 break;
221 }
222 }
223 if (index < 0)
224 return NULL;
225
226 /* create a new port analayzer entry for local_port */
227 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
228 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
229 if (err)
230 return NULL;
231
232 span_entry->used = true;
233 span_entry->id = index;
234 span_entry->ref_count = 1;
235 span_entry->local_port = local_port;
236 return span_entry;
237 }
238
239 static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
240 struct mlxsw_sp_span_entry *span_entry)
241 {
242 u8 local_port = span_entry->local_port;
243 char mpat_pl[MLXSW_REG_MPAT_LEN];
244 int pa_id = span_entry->id;
245
246 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
247 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
248 span_entry->used = false;
249 }
250
251 static struct mlxsw_sp_span_entry *
252 mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
253 {
254 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
255 int i;
256
257 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
258 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
259
260 if (curr->used && curr->local_port == port->local_port)
261 return curr;
262 }
263 return NULL;
264 }
265
266 static struct mlxsw_sp_span_entry
267 *mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
268 {
269 struct mlxsw_sp_span_entry *span_entry;
270
271 span_entry = mlxsw_sp_span_entry_find(port);
272 if (span_entry) {
273 /* Already exists, just take a reference */
274 span_entry->ref_count++;
275 return span_entry;
276 }
277
278 return mlxsw_sp_span_entry_create(port);
279 }
280
281 static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
282 struct mlxsw_sp_span_entry *span_entry)
283 {
284 WARN_ON(!span_entry->ref_count);
285 if (--span_entry->ref_count == 0)
286 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
287 return 0;
288 }
289
290 static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
291 {
292 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
293 struct mlxsw_sp_span_inspected_port *p;
294 int i;
295
296 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
297 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
298
299 list_for_each_entry(p, &curr->bound_ports_list, list)
300 if (p->local_port == port->local_port &&
301 p->type == MLXSW_SP_SPAN_EGRESS)
302 return true;
303 }
304
305 return false;
306 }
307
308 static int mlxsw_sp_span_mtu_to_buffsize(int mtu)
309 {
310 return MLXSW_SP_BYTES_TO_CELLS(mtu * 5 / 2) + 1;
311 }
312
313 static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
314 {
315 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
316 char sbib_pl[MLXSW_REG_SBIB_LEN];
317 int err;
318
319 /* If port is egress mirrored, the shared buffer size should be
320 * updated according to the mtu value
321 */
322 if (mlxsw_sp_span_is_egress_mirror(port)) {
323 mlxsw_reg_sbib_pack(sbib_pl, port->local_port,
324 mlxsw_sp_span_mtu_to_buffsize(mtu));
325 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
326 if (err) {
327 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
328 return err;
329 }
330 }
331
332 return 0;
333 }
334
335 static struct mlxsw_sp_span_inspected_port *
336 mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
337 struct mlxsw_sp_span_entry *span_entry)
338 {
339 struct mlxsw_sp_span_inspected_port *p;
340
341 list_for_each_entry(p, &span_entry->bound_ports_list, list)
342 if (port->local_port == p->local_port)
343 return p;
344 return NULL;
345 }
346
347 static int
348 mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
349 struct mlxsw_sp_span_entry *span_entry,
350 enum mlxsw_sp_span_type type)
351 {
352 struct mlxsw_sp_span_inspected_port *inspected_port;
353 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
354 char mpar_pl[MLXSW_REG_MPAR_LEN];
355 char sbib_pl[MLXSW_REG_SBIB_LEN];
356 int pa_id = span_entry->id;
357 int err;
358
359 /* if it is an egress SPAN, bind a shared buffer to it */
360 if (type == MLXSW_SP_SPAN_EGRESS) {
361 mlxsw_reg_sbib_pack(sbib_pl, port->local_port,
362 mlxsw_sp_span_mtu_to_buffsize(port->dev->mtu));
363 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
364 if (err) {
365 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
366 return err;
367 }
368 }
369
370 /* bind the port to the SPAN entry */
371 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
372 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
373 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
374 if (err)
375 goto err_mpar_reg_write;
376
377 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
378 if (!inspected_port) {
379 err = -ENOMEM;
380 goto err_inspected_port_alloc;
381 }
382 inspected_port->local_port = port->local_port;
383 inspected_port->type = type;
384 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
385
386 return 0;
387
388 err_mpar_reg_write:
389 err_inspected_port_alloc:
390 if (type == MLXSW_SP_SPAN_EGRESS) {
391 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
392 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
393 }
394 return err;
395 }
396
397 static void
398 mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
399 struct mlxsw_sp_span_entry *span_entry,
400 enum mlxsw_sp_span_type type)
401 {
402 struct mlxsw_sp_span_inspected_port *inspected_port;
403 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
404 char mpar_pl[MLXSW_REG_MPAR_LEN];
405 char sbib_pl[MLXSW_REG_SBIB_LEN];
406 int pa_id = span_entry->id;
407
408 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
409 if (!inspected_port)
410 return;
411
412 /* remove the inspected port */
413 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
414 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
415 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
416
417 /* remove the SBIB buffer if it was egress SPAN */
418 if (type == MLXSW_SP_SPAN_EGRESS) {
419 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
420 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
421 }
422
423 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
424
425 list_del(&inspected_port->list);
426 kfree(inspected_port);
427 }
428
429 static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
430 struct mlxsw_sp_port *to,
431 enum mlxsw_sp_span_type type)
432 {
433 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
434 struct mlxsw_sp_span_entry *span_entry;
435 int err;
436
437 span_entry = mlxsw_sp_span_entry_get(to);
438 if (!span_entry)
439 return -ENOENT;
440
441 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
442 span_entry->id);
443
444 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
445 if (err)
446 goto err_port_bind;
447
448 return 0;
449
450 err_port_bind:
451 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
452 return err;
453 }
454
455 static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
456 struct mlxsw_sp_port *to,
457 enum mlxsw_sp_span_type type)
458 {
459 struct mlxsw_sp_span_entry *span_entry;
460
461 span_entry = mlxsw_sp_span_entry_find(to);
462 if (!span_entry) {
463 netdev_err(from->dev, "no span entry found\n");
464 return;
465 }
466
467 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
468 span_entry->id);
469 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
470 }
471
472 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
473 bool is_up)
474 {
475 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
476 char paos_pl[MLXSW_REG_PAOS_LEN];
477
478 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
479 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
480 MLXSW_PORT_ADMIN_STATUS_DOWN);
481 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
482 }
483
484 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
485 unsigned char *addr)
486 {
487 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
488 char ppad_pl[MLXSW_REG_PPAD_LEN];
489
490 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
491 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
492 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
493 }
494
495 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
496 {
497 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
498 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
499
500 ether_addr_copy(addr, mlxsw_sp->base_mac);
501 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
502 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
503 }
504
505 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
506 {
507 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
508 char pmtu_pl[MLXSW_REG_PMTU_LEN];
509 int max_mtu;
510 int err;
511
512 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
513 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
514 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
515 if (err)
516 return err;
517 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
518
519 if (mtu > max_mtu)
520 return -EINVAL;
521
522 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
523 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
524 }
525
526 static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
527 u8 swid)
528 {
529 char pspa_pl[MLXSW_REG_PSPA_LEN];
530
531 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
532 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
533 }
534
535 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
536 {
537 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
538
539 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
540 swid);
541 }
542
543 static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
544 bool enable)
545 {
546 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
547 char svpe_pl[MLXSW_REG_SVPE_LEN];
548
549 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
550 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
551 }
552
553 int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
554 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
555 u16 vid)
556 {
557 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
558 char svfa_pl[MLXSW_REG_SVFA_LEN];
559
560 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
561 fid, vid);
562 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
563 }
564
565 int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
566 u16 vid_begin, u16 vid_end,
567 bool learn_enable)
568 {
569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
570 char *spvmlr_pl;
571 int err;
572
573 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
574 if (!spvmlr_pl)
575 return -ENOMEM;
576 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid_begin,
577 vid_end, learn_enable);
578 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
579 kfree(spvmlr_pl);
580 return err;
581 }
582
583 static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
584 u16 vid, bool learn_enable)
585 {
586 return __mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, vid,
587 learn_enable);
588 }
589
590 static int
591 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
592 {
593 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
594 char sspr_pl[MLXSW_REG_SSPR_LEN];
595
596 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
598 }
599
600 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
601 u8 local_port, u8 *p_module,
602 u8 *p_width, u8 *p_lane)
603 {
604 char pmlp_pl[MLXSW_REG_PMLP_LEN];
605 int err;
606
607 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
608 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
609 if (err)
610 return err;
611 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
612 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
613 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
614 return 0;
615 }
616
617 static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
618 u8 module, u8 width, u8 lane)
619 {
620 char pmlp_pl[MLXSW_REG_PMLP_LEN];
621 int i;
622
623 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
624 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
625 for (i = 0; i < width; i++) {
626 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
627 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
628 }
629
630 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
631 }
632
633 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
634 {
635 char pmlp_pl[MLXSW_REG_PMLP_LEN];
636
637 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
638 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
639 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
640 }
641
642 static int mlxsw_sp_port_open(struct net_device *dev)
643 {
644 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
645 int err;
646
647 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
648 if (err)
649 return err;
650 netif_start_queue(dev);
651 return 0;
652 }
653
654 static int mlxsw_sp_port_stop(struct net_device *dev)
655 {
656 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
657
658 netif_stop_queue(dev);
659 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
660 }
661
662 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
663 struct net_device *dev)
664 {
665 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
666 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
667 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
668 const struct mlxsw_tx_info tx_info = {
669 .local_port = mlxsw_sp_port->local_port,
670 .is_emad = false,
671 };
672 u64 len;
673 int err;
674
675 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
676 return NETDEV_TX_BUSY;
677
678 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
679 struct sk_buff *skb_orig = skb;
680
681 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
682 if (!skb) {
683 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
684 dev_kfree_skb_any(skb_orig);
685 return NETDEV_TX_OK;
686 }
687 dev_consume_skb_any(skb_orig);
688 }
689
690 if (eth_skb_pad(skb)) {
691 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
692 return NETDEV_TX_OK;
693 }
694
695 mlxsw_sp_txhdr_construct(skb, &tx_info);
696 /* TX header is consumed by HW on the way so we shouldn't count its
697 * bytes as being sent.
698 */
699 len = skb->len - MLXSW_TXHDR_LEN;
700
701 /* Due to a race we might fail here because of a full queue. In that
702 * unlikely case we simply drop the packet.
703 */
704 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
705
706 if (!err) {
707 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
708 u64_stats_update_begin(&pcpu_stats->syncp);
709 pcpu_stats->tx_packets++;
710 pcpu_stats->tx_bytes += len;
711 u64_stats_update_end(&pcpu_stats->syncp);
712 } else {
713 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
714 dev_kfree_skb_any(skb);
715 }
716 return NETDEV_TX_OK;
717 }
718
719 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
720 {
721 }
722
723 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
724 {
725 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
726 struct sockaddr *addr = p;
727 int err;
728
729 if (!is_valid_ether_addr(addr->sa_data))
730 return -EADDRNOTAVAIL;
731
732 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
733 if (err)
734 return err;
735 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
736 return 0;
737 }
738
739 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
740 bool pause_en, bool pfc_en, u16 delay)
741 {
742 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
743
744 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
745 MLXSW_SP_PAUSE_DELAY;
746
747 if (pause_en || pfc_en)
748 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
749 pg_size + delay, pg_size);
750 else
751 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
752 }
753
754 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
755 u8 *prio_tc, bool pause_en,
756 struct ieee_pfc *my_pfc)
757 {
758 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
759 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
760 u16 delay = !!my_pfc ? my_pfc->delay : 0;
761 char pbmc_pl[MLXSW_REG_PBMC_LEN];
762 int i, j, err;
763
764 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
765 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
766 if (err)
767 return err;
768
769 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
770 bool configure = false;
771 bool pfc = false;
772
773 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
774 if (prio_tc[j] == i) {
775 pfc = pfc_en & BIT(j);
776 configure = true;
777 break;
778 }
779 }
780
781 if (!configure)
782 continue;
783 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
784 }
785
786 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
787 }
788
789 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
790 int mtu, bool pause_en)
791 {
792 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
793 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
794 struct ieee_pfc *my_pfc;
795 u8 *prio_tc;
796
797 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
798 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
799
800 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
801 pause_en, my_pfc);
802 }
803
804 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
805 {
806 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
807 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
808 int err;
809
810 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
811 if (err)
812 return err;
813 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
814 if (err)
815 goto err_span_port_mtu_update;
816 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
817 if (err)
818 goto err_port_mtu_set;
819 dev->mtu = mtu;
820 return 0;
821
822 err_port_mtu_set:
823 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
824 err_span_port_mtu_update:
825 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
826 return err;
827 }
828
829 static int
830 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
831 struct rtnl_link_stats64 *stats)
832 {
833 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
834 struct mlxsw_sp_port_pcpu_stats *p;
835 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
836 u32 tx_dropped = 0;
837 unsigned int start;
838 int i;
839
840 for_each_possible_cpu(i) {
841 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
842 do {
843 start = u64_stats_fetch_begin_irq(&p->syncp);
844 rx_packets = p->rx_packets;
845 rx_bytes = p->rx_bytes;
846 tx_packets = p->tx_packets;
847 tx_bytes = p->tx_bytes;
848 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
849
850 stats->rx_packets += rx_packets;
851 stats->rx_bytes += rx_bytes;
852 stats->tx_packets += tx_packets;
853 stats->tx_bytes += tx_bytes;
854 /* tx_dropped is u32, updated without syncp protection. */
855 tx_dropped += p->tx_dropped;
856 }
857 stats->tx_dropped = tx_dropped;
858 return 0;
859 }
860
861 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
862 {
863 switch (attr_id) {
864 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
865 return true;
866 }
867
868 return false;
869 }
870
871 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
872 void *sp)
873 {
874 switch (attr_id) {
875 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
876 return mlxsw_sp_port_get_sw_stats64(dev, sp);
877 }
878
879 return -EINVAL;
880 }
881
882 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
883 int prio, char *ppcnt_pl)
884 {
885 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
886 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
887
888 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
889 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
890 }
891
892 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
893 struct rtnl_link_stats64 *stats)
894 {
895 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
896 int err;
897
898 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
899 0, ppcnt_pl);
900 if (err)
901 goto out;
902
903 stats->tx_packets =
904 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
905 stats->rx_packets =
906 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
907 stats->tx_bytes =
908 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
909 stats->rx_bytes =
910 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
911 stats->multicast =
912 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
913
914 stats->rx_crc_errors =
915 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
916 stats->rx_frame_errors =
917 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
918
919 stats->rx_length_errors = (
920 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
921 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
922 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
923
924 stats->rx_errors = (stats->rx_crc_errors +
925 stats->rx_frame_errors + stats->rx_length_errors);
926
927 out:
928 return err;
929 }
930
931 static void update_stats_cache(struct work_struct *work)
932 {
933 struct mlxsw_sp_port *mlxsw_sp_port =
934 container_of(work, struct mlxsw_sp_port,
935 hw_stats.update_dw.work);
936
937 if (!netif_carrier_ok(mlxsw_sp_port->dev))
938 goto out;
939
940 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
941 mlxsw_sp_port->hw_stats.cache);
942
943 out:
944 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
945 MLXSW_HW_STATS_UPDATE_TIME);
946 }
947
948 /* Return the stats from a cache that is updated periodically,
949 * as this function might get called in an atomic context.
950 */
951 static struct rtnl_link_stats64 *
952 mlxsw_sp_port_get_stats64(struct net_device *dev,
953 struct rtnl_link_stats64 *stats)
954 {
955 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
956
957 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
958
959 return stats;
960 }
961
962 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
963 u16 vid_end, bool is_member, bool untagged)
964 {
965 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
966 char *spvm_pl;
967 int err;
968
969 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
970 if (!spvm_pl)
971 return -ENOMEM;
972
973 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
974 vid_end, is_member, untagged);
975 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
976 kfree(spvm_pl);
977 return err;
978 }
979
980 static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
981 {
982 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
983 u16 vid, last_visited_vid;
984 int err;
985
986 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
987 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
988 vid);
989 if (err) {
990 last_visited_vid = vid;
991 goto err_port_vid_to_fid_set;
992 }
993 }
994
995 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
996 if (err) {
997 last_visited_vid = VLAN_N_VID;
998 goto err_port_vid_to_fid_set;
999 }
1000
1001 return 0;
1002
1003 err_port_vid_to_fid_set:
1004 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
1005 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
1006 vid);
1007 return err;
1008 }
1009
1010 static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
1011 {
1012 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1013 u16 vid;
1014 int err;
1015
1016 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1017 if (err)
1018 return err;
1019
1020 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1021 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
1022 vid, vid);
1023 if (err)
1024 return err;
1025 }
1026
1027 return 0;
1028 }
1029
1030 static struct mlxsw_sp_port *
1031 mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1032 {
1033 struct mlxsw_sp_port *mlxsw_sp_vport;
1034
1035 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
1036 if (!mlxsw_sp_vport)
1037 return NULL;
1038
1039 /* dev will be set correctly after the VLAN device is linked
1040 * with the real device. In case of bridge SELF invocation, dev
1041 * will remain as is.
1042 */
1043 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
1044 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1045 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
1046 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
1047 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
1048 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
1049 mlxsw_sp_vport->vport.vid = vid;
1050
1051 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
1052
1053 return mlxsw_sp_vport;
1054 }
1055
1056 static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
1057 {
1058 list_del(&mlxsw_sp_vport->vport.list);
1059 kfree(mlxsw_sp_vport);
1060 }
1061
1062 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1063 __be16 __always_unused proto, u16 vid)
1064 {
1065 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1066 struct mlxsw_sp_port *mlxsw_sp_vport;
1067 bool untagged = vid == 1;
1068 int err;
1069
1070 /* VLAN 0 is added to HW filter when device goes up, but it is
1071 * reserved in our case, so simply return.
1072 */
1073 if (!vid)
1074 return 0;
1075
1076 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid))
1077 return 0;
1078
1079 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
1080 if (!mlxsw_sp_vport)
1081 return -ENOMEM;
1082
1083 /* When adding the first VLAN interface on a bridged port we need to
1084 * transition all the active 802.1Q bridge VLANs to use explicit
1085 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
1086 */
1087 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
1088 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
1089 if (err)
1090 goto err_port_vp_mode_trans;
1091 }
1092
1093 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
1094 if (err)
1095 goto err_port_add_vid;
1096
1097 return 0;
1098
1099 err_port_add_vid:
1100 if (list_is_singular(&mlxsw_sp_port->vports_list))
1101 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1102 err_port_vp_mode_trans:
1103 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1104 return err;
1105 }
1106
1107 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1108 __be16 __always_unused proto, u16 vid)
1109 {
1110 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1111 struct mlxsw_sp_port *mlxsw_sp_vport;
1112 struct mlxsw_sp_fid *f;
1113
1114 /* VLAN 0 is removed from HW filter when device goes down, but
1115 * it is reserved in our case, so simply return.
1116 */
1117 if (!vid)
1118 return 0;
1119
1120 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
1121 if (WARN_ON(!mlxsw_sp_vport))
1122 return 0;
1123
1124 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
1125
1126 /* Drop FID reference. If this was the last reference the
1127 * resources will be freed.
1128 */
1129 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
1130 if (f && !WARN_ON(!f->leave))
1131 f->leave(mlxsw_sp_vport);
1132
1133 /* When removing the last VLAN interface on a bridged port we need to
1134 * transition all active 802.1Q bridge VLANs to use VID to FID
1135 * mappings and set port's mode to VLAN mode.
1136 */
1137 if (list_is_singular(&mlxsw_sp_port->vports_list))
1138 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
1139
1140 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1141
1142 return 0;
1143 }
1144
1145 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1146 size_t len)
1147 {
1148 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1149 u8 module = mlxsw_sp_port->mapping.module;
1150 u8 width = mlxsw_sp_port->mapping.width;
1151 u8 lane = mlxsw_sp_port->mapping.lane;
1152 int err;
1153
1154 if (!mlxsw_sp_port->split)
1155 err = snprintf(name, len, "p%d", module + 1);
1156 else
1157 err = snprintf(name, len, "p%ds%d", module + 1,
1158 lane / width);
1159
1160 if (err >= len)
1161 return -EINVAL;
1162
1163 return 0;
1164 }
1165
1166 static struct mlxsw_sp_port_mall_tc_entry *
1167 mlxsw_sp_port_mirror_entry_find(struct mlxsw_sp_port *port,
1168 unsigned long cookie) {
1169 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1170
1171 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1172 if (mall_tc_entry->cookie == cookie)
1173 return mall_tc_entry;
1174
1175 return NULL;
1176 }
1177
1178 static int
1179 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1180 struct tc_cls_matchall_offload *cls,
1181 const struct tc_action *a,
1182 bool ingress)
1183 {
1184 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1185 struct net *net = dev_net(mlxsw_sp_port->dev);
1186 enum mlxsw_sp_span_type span_type;
1187 struct mlxsw_sp_port *to_port;
1188 struct net_device *to_dev;
1189 int ifindex;
1190 int err;
1191
1192 ifindex = tcf_mirred_ifindex(a);
1193 to_dev = __dev_get_by_index(net, ifindex);
1194 if (!to_dev) {
1195 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1196 return -EINVAL;
1197 }
1198
1199 if (!mlxsw_sp_port_dev_check(to_dev)) {
1200 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
1201 return -ENOTSUPP;
1202 }
1203 to_port = netdev_priv(to_dev);
1204
1205 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1206 if (!mall_tc_entry)
1207 return -ENOMEM;
1208
1209 mall_tc_entry->cookie = cls->cookie;
1210 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1211 mall_tc_entry->mirror.to_local_port = to_port->local_port;
1212 mall_tc_entry->mirror.ingress = ingress;
1213 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1214
1215 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1216 err = mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1217 if (err)
1218 goto err_mirror_add;
1219 return 0;
1220
1221 err_mirror_add:
1222 list_del(&mall_tc_entry->list);
1223 kfree(mall_tc_entry);
1224 return err;
1225 }
1226
1227 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1228 __be16 protocol,
1229 struct tc_cls_matchall_offload *cls,
1230 bool ingress)
1231 {
1232 const struct tc_action *a;
1233 LIST_HEAD(actions);
1234 int err;
1235
1236 if (!tc_single_action(cls->exts)) {
1237 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1238 return -ENOTSUPP;
1239 }
1240
1241 tcf_exts_to_list(cls->exts, &actions);
1242 list_for_each_entry(a, &actions, list) {
1243 if (!is_tcf_mirred_egress_mirror(a) ||
1244 protocol != htons(ETH_P_ALL)) {
1245 return -ENOTSUPP;
1246 }
1247
1248 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port, cls,
1249 a, ingress);
1250 if (err)
1251 return err;
1252 }
1253
1254 return 0;
1255 }
1256
1257 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1258 struct tc_cls_matchall_offload *cls)
1259 {
1260 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1261 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1262 enum mlxsw_sp_span_type span_type;
1263 struct mlxsw_sp_port *to_port;
1264
1265 mall_tc_entry = mlxsw_sp_port_mirror_entry_find(mlxsw_sp_port,
1266 cls->cookie);
1267 if (!mall_tc_entry) {
1268 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1269 return;
1270 }
1271
1272 switch (mall_tc_entry->type) {
1273 case MLXSW_SP_PORT_MALL_MIRROR:
1274 to_port = mlxsw_sp->ports[mall_tc_entry->mirror.to_local_port];
1275 span_type = mall_tc_entry->mirror.ingress ?
1276 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1277
1278 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
1279 break;
1280 default:
1281 WARN_ON(1);
1282 }
1283
1284 list_del(&mall_tc_entry->list);
1285 kfree(mall_tc_entry);
1286 }
1287
1288 static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1289 __be16 proto, struct tc_to_netdev *tc)
1290 {
1291 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1292 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1293
1294 if (tc->type == TC_SETUP_MATCHALL) {
1295 switch (tc->cls_mall->command) {
1296 case TC_CLSMATCHALL_REPLACE:
1297 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1298 proto,
1299 tc->cls_mall,
1300 ingress);
1301 case TC_CLSMATCHALL_DESTROY:
1302 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1303 tc->cls_mall);
1304 return 0;
1305 default:
1306 return -EINVAL;
1307 }
1308 }
1309
1310 return -ENOTSUPP;
1311 }
1312
1313 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1314 .ndo_open = mlxsw_sp_port_open,
1315 .ndo_stop = mlxsw_sp_port_stop,
1316 .ndo_start_xmit = mlxsw_sp_port_xmit,
1317 .ndo_setup_tc = mlxsw_sp_setup_tc,
1318 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
1319 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1320 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1321 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
1322 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1323 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
1324 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1325 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1326 .ndo_neigh_construct = mlxsw_sp_router_neigh_construct,
1327 .ndo_neigh_destroy = mlxsw_sp_router_neigh_destroy,
1328 .ndo_fdb_add = switchdev_port_fdb_add,
1329 .ndo_fdb_del = switchdev_port_fdb_del,
1330 .ndo_fdb_dump = switchdev_port_fdb_dump,
1331 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1332 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1333 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
1334 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
1335 };
1336
1337 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1338 struct ethtool_drvinfo *drvinfo)
1339 {
1340 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1341 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1342
1343 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1344 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1345 sizeof(drvinfo->version));
1346 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1347 "%d.%d.%d",
1348 mlxsw_sp->bus_info->fw_rev.major,
1349 mlxsw_sp->bus_info->fw_rev.minor,
1350 mlxsw_sp->bus_info->fw_rev.subminor);
1351 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1352 sizeof(drvinfo->bus_info));
1353 }
1354
1355 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1356 struct ethtool_pauseparam *pause)
1357 {
1358 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1359
1360 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1361 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1362 }
1363
1364 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1365 struct ethtool_pauseparam *pause)
1366 {
1367 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1368
1369 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1370 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1371 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1372
1373 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1374 pfcc_pl);
1375 }
1376
1377 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1378 struct ethtool_pauseparam *pause)
1379 {
1380 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1381 bool pause_en = pause->tx_pause || pause->rx_pause;
1382 int err;
1383
1384 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1385 netdev_err(dev, "PFC already enabled on port\n");
1386 return -EINVAL;
1387 }
1388
1389 if (pause->autoneg) {
1390 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1391 return -EINVAL;
1392 }
1393
1394 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1395 if (err) {
1396 netdev_err(dev, "Failed to configure port's headroom\n");
1397 return err;
1398 }
1399
1400 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1401 if (err) {
1402 netdev_err(dev, "Failed to set PAUSE parameters\n");
1403 goto err_port_pause_configure;
1404 }
1405
1406 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1407 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1408
1409 return 0;
1410
1411 err_port_pause_configure:
1412 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1413 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1414 return err;
1415 }
1416
1417 struct mlxsw_sp_port_hw_stats {
1418 char str[ETH_GSTRING_LEN];
1419 u64 (*getter)(const char *payload);
1420 };
1421
1422 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1423 {
1424 .str = "a_frames_transmitted_ok",
1425 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1426 },
1427 {
1428 .str = "a_frames_received_ok",
1429 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1430 },
1431 {
1432 .str = "a_frame_check_sequence_errors",
1433 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1434 },
1435 {
1436 .str = "a_alignment_errors",
1437 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1438 },
1439 {
1440 .str = "a_octets_transmitted_ok",
1441 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1442 },
1443 {
1444 .str = "a_octets_received_ok",
1445 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1446 },
1447 {
1448 .str = "a_multicast_frames_xmitted_ok",
1449 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1450 },
1451 {
1452 .str = "a_broadcast_frames_xmitted_ok",
1453 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1454 },
1455 {
1456 .str = "a_multicast_frames_received_ok",
1457 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1458 },
1459 {
1460 .str = "a_broadcast_frames_received_ok",
1461 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1462 },
1463 {
1464 .str = "a_in_range_length_errors",
1465 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1466 },
1467 {
1468 .str = "a_out_of_range_length_field",
1469 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1470 },
1471 {
1472 .str = "a_frame_too_long_errors",
1473 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1474 },
1475 {
1476 .str = "a_symbol_error_during_carrier",
1477 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1478 },
1479 {
1480 .str = "a_mac_control_frames_transmitted",
1481 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1482 },
1483 {
1484 .str = "a_mac_control_frames_received",
1485 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1486 },
1487 {
1488 .str = "a_unsupported_opcodes_received",
1489 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1490 },
1491 {
1492 .str = "a_pause_mac_ctrl_frames_received",
1493 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1494 },
1495 {
1496 .str = "a_pause_mac_ctrl_frames_xmitted",
1497 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1498 },
1499 };
1500
1501 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1502
1503 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1504 {
1505 .str = "rx_octets_prio",
1506 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1507 },
1508 {
1509 .str = "rx_frames_prio",
1510 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1511 },
1512 {
1513 .str = "tx_octets_prio",
1514 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1515 },
1516 {
1517 .str = "tx_frames_prio",
1518 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1519 },
1520 {
1521 .str = "rx_pause_prio",
1522 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1523 },
1524 {
1525 .str = "rx_pause_duration_prio",
1526 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1527 },
1528 {
1529 .str = "tx_pause_prio",
1530 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1531 },
1532 {
1533 .str = "tx_pause_duration_prio",
1534 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1535 },
1536 };
1537
1538 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1539
1540 static u64 mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get(const char *ppcnt_pl)
1541 {
1542 u64 transmit_queue = mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1543
1544 return MLXSW_SP_CELLS_TO_BYTES(transmit_queue);
1545 }
1546
1547 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1548 {
1549 .str = "tc_transmit_queue_tc",
1550 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_bytes_get,
1551 },
1552 {
1553 .str = "tc_no_buffer_discard_uc_tc",
1554 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1555 },
1556 };
1557
1558 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1559
1560 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
1561 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1562 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
1563 IEEE_8021QAZ_MAX_TCS)
1564
1565 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1566 {
1567 int i;
1568
1569 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1570 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1571 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1572 *p += ETH_GSTRING_LEN;
1573 }
1574 }
1575
1576 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1577 {
1578 int i;
1579
1580 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1581 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1582 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1583 *p += ETH_GSTRING_LEN;
1584 }
1585 }
1586
1587 static void mlxsw_sp_port_get_strings(struct net_device *dev,
1588 u32 stringset, u8 *data)
1589 {
1590 u8 *p = data;
1591 int i;
1592
1593 switch (stringset) {
1594 case ETH_SS_STATS:
1595 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1596 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1597 ETH_GSTRING_LEN);
1598 p += ETH_GSTRING_LEN;
1599 }
1600
1601 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1602 mlxsw_sp_port_get_prio_strings(&p, i);
1603
1604 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
1605 mlxsw_sp_port_get_tc_strings(&p, i);
1606
1607 break;
1608 }
1609 }
1610
1611 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1612 enum ethtool_phys_id_state state)
1613 {
1614 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1615 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1616 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1617 bool active;
1618
1619 switch (state) {
1620 case ETHTOOL_ID_ACTIVE:
1621 active = true;
1622 break;
1623 case ETHTOOL_ID_INACTIVE:
1624 active = false;
1625 break;
1626 default:
1627 return -EOPNOTSUPP;
1628 }
1629
1630 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1631 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1632 }
1633
1634 static int
1635 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
1636 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
1637 {
1638 switch (grp) {
1639 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
1640 *p_hw_stats = mlxsw_sp_port_hw_stats;
1641 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
1642 break;
1643 case MLXSW_REG_PPCNT_PRIO_CNT:
1644 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
1645 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1646 break;
1647 case MLXSW_REG_PPCNT_TC_CNT:
1648 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
1649 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
1650 break;
1651 default:
1652 WARN_ON(1);
1653 return -ENOTSUPP;
1654 }
1655 return 0;
1656 }
1657
1658 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
1659 enum mlxsw_reg_ppcnt_grp grp, int prio,
1660 u64 *data, int data_index)
1661 {
1662 struct mlxsw_sp_port_hw_stats *hw_stats;
1663 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1664 int i, len;
1665 int err;
1666
1667 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
1668 if (err)
1669 return;
1670 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
1671 for (i = 0; i < len; i++)
1672 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
1673 }
1674
1675 static void mlxsw_sp_port_get_stats(struct net_device *dev,
1676 struct ethtool_stats *stats, u64 *data)
1677 {
1678 int i, data_index = 0;
1679
1680 /* IEEE 802.3 Counters */
1681 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
1682 data, data_index);
1683 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
1684
1685 /* Per-Priority Counters */
1686 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1687 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
1688 data, data_index);
1689 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
1690 }
1691
1692 /* Per-TC Counters */
1693 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1694 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
1695 data, data_index);
1696 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
1697 }
1698 }
1699
1700 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1701 {
1702 switch (sset) {
1703 case ETH_SS_STATS:
1704 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
1705 default:
1706 return -EOPNOTSUPP;
1707 }
1708 }
1709
1710 struct mlxsw_sp_port_link_mode {
1711 enum ethtool_link_mode_bit_indices mask_ethtool;
1712 u32 mask;
1713 u32 speed;
1714 };
1715
1716 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1717 {
1718 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1719 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1720 .speed = SPEED_100,
1721 },
1722 {
1723 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1724 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1725 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1726 .speed = SPEED_1000,
1727 },
1728 {
1729 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1730 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1731 .speed = SPEED_10000,
1732 },
1733 {
1734 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1735 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1736 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1737 .speed = SPEED_10000,
1738 },
1739 {
1740 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1741 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1742 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1743 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1744 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1745 .speed = SPEED_10000,
1746 },
1747 {
1748 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1749 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
1750 .speed = SPEED_20000,
1751 },
1752 {
1753 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1754 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1755 .speed = SPEED_40000,
1756 },
1757 {
1758 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1759 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1760 .speed = SPEED_40000,
1761 },
1762 {
1763 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1764 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1765 .speed = SPEED_40000,
1766 },
1767 {
1768 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1769 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1770 .speed = SPEED_40000,
1771 },
1772 {
1773 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
1774 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1775 .speed = SPEED_25000,
1776 },
1777 {
1778 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
1779 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1780 .speed = SPEED_25000,
1781 },
1782 {
1783 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1784 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1785 .speed = SPEED_25000,
1786 },
1787 {
1788 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1789 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1790 .speed = SPEED_25000,
1791 },
1792 {
1793 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
1794 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1795 .speed = SPEED_50000,
1796 },
1797 {
1798 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1799 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1800 .speed = SPEED_50000,
1801 },
1802 {
1803 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
1804 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1805 .speed = SPEED_50000,
1806 },
1807 {
1808 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1809 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
1810 .speed = SPEED_56000,
1811 },
1812 {
1813 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1814 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
1815 .speed = SPEED_56000,
1816 },
1817 {
1818 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1819 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
1820 .speed = SPEED_56000,
1821 },
1822 {
1823 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1824 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
1825 .speed = SPEED_56000,
1826 },
1827 {
1828 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
1829 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1830 .speed = SPEED_100000,
1831 },
1832 {
1833 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
1834 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1835 .speed = SPEED_100000,
1836 },
1837 {
1838 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
1839 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1840 .speed = SPEED_100000,
1841 },
1842 {
1843 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1844 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1845 .speed = SPEED_100000,
1846 },
1847 };
1848
1849 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1850
1851 static void
1852 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
1853 struct ethtool_link_ksettings *cmd)
1854 {
1855 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1856 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1857 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1858 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1859 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1860 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1861 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
1862
1863 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1864 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1865 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1866 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1867 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1868 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
1869 }
1870
1871 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
1872 {
1873 int i;
1874
1875 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1876 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1877 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
1878 mode);
1879 }
1880 }
1881
1882 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1883 struct ethtool_link_ksettings *cmd)
1884 {
1885 u32 speed = SPEED_UNKNOWN;
1886 u8 duplex = DUPLEX_UNKNOWN;
1887 int i;
1888
1889 if (!carrier_ok)
1890 goto out;
1891
1892 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1893 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1894 speed = mlxsw_sp_port_link_mode[i].speed;
1895 duplex = DUPLEX_FULL;
1896 break;
1897 }
1898 }
1899 out:
1900 cmd->base.speed = speed;
1901 cmd->base.duplex = duplex;
1902 }
1903
1904 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1905 {
1906 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1907 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1908 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1909 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1910 return PORT_FIBRE;
1911
1912 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1913 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1914 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1915 return PORT_DA;
1916
1917 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1918 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1919 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1920 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1921 return PORT_NONE;
1922
1923 return PORT_OTHER;
1924 }
1925
1926 static u32
1927 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
1928 {
1929 u32 ptys_proto = 0;
1930 int i;
1931
1932 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1933 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
1934 cmd->link_modes.advertising))
1935 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1936 }
1937 return ptys_proto;
1938 }
1939
1940 static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1941 {
1942 u32 ptys_proto = 0;
1943 int i;
1944
1945 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1946 if (speed == mlxsw_sp_port_link_mode[i].speed)
1947 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1948 }
1949 return ptys_proto;
1950 }
1951
1952 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1953 {
1954 u32 ptys_proto = 0;
1955 int i;
1956
1957 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1958 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1959 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1960 }
1961 return ptys_proto;
1962 }
1963
1964 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
1965 struct ethtool_link_ksettings *cmd)
1966 {
1967 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
1968 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
1969 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
1970
1971 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
1972 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
1973 }
1974
1975 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
1976 struct ethtool_link_ksettings *cmd)
1977 {
1978 if (!autoneg)
1979 return;
1980
1981 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
1982 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
1983 }
1984
1985 static void
1986 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
1987 struct ethtool_link_ksettings *cmd)
1988 {
1989 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
1990 return;
1991
1992 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
1993 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
1994 }
1995
1996 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
1997 struct ethtool_link_ksettings *cmd)
1998 {
1999 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2000 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2001 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2002 char ptys_pl[MLXSW_REG_PTYS_LEN];
2003 u8 autoneg_status;
2004 bool autoneg;
2005 int err;
2006
2007 autoneg = mlxsw_sp_port->link.autoneg;
2008 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
2009 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2010 if (err)
2011 return err;
2012 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2013 &eth_proto_oper);
2014
2015 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2016
2017 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2018
2019 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2020 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2021 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2022
2023 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2024 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2025 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2026 cmd);
2027
2028 return 0;
2029 }
2030
2031 static int
2032 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2033 const struct ethtool_link_ksettings *cmd)
2034 {
2035 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2036 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2037 char ptys_pl[MLXSW_REG_PTYS_LEN];
2038 u32 eth_proto_cap, eth_proto_new;
2039 bool autoneg;
2040 int err;
2041
2042 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
2043 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2044 if (err)
2045 return err;
2046 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
2047
2048 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2049 eth_proto_new = autoneg ?
2050 mlxsw_sp_to_ptys_advert_link(cmd) :
2051 mlxsw_sp_to_ptys_speed(cmd->base.speed);
2052
2053 eth_proto_new = eth_proto_new & eth_proto_cap;
2054 if (!eth_proto_new) {
2055 netdev_err(dev, "No supported speed requested\n");
2056 return -EINVAL;
2057 }
2058
2059 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2060 eth_proto_new);
2061 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2062 if (err)
2063 return err;
2064
2065 if (!netif_running(dev))
2066 return 0;
2067
2068 mlxsw_sp_port->link.autoneg = autoneg;
2069
2070 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2071 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
2072
2073 return 0;
2074 }
2075
2076 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2077 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2078 .get_link = ethtool_op_get_link,
2079 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2080 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
2081 .get_strings = mlxsw_sp_port_get_strings,
2082 .set_phys_id = mlxsw_sp_port_set_phys_id,
2083 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2084 .get_sset_count = mlxsw_sp_port_get_sset_count,
2085 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2086 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
2087 };
2088
2089 static int
2090 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2091 {
2092 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2093 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2094 char ptys_pl[MLXSW_REG_PTYS_LEN];
2095 u32 eth_proto_admin;
2096
2097 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
2098 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2099 eth_proto_admin);
2100 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2101 }
2102
2103 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2104 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2105 bool dwrr, u8 dwrr_weight)
2106 {
2107 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2108 char qeec_pl[MLXSW_REG_QEEC_LEN];
2109
2110 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2111 next_index);
2112 mlxsw_reg_qeec_de_set(qeec_pl, true);
2113 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2114 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2115 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2116 }
2117
2118 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2119 enum mlxsw_reg_qeec_hr hr, u8 index,
2120 u8 next_index, u32 maxrate)
2121 {
2122 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2123 char qeec_pl[MLXSW_REG_QEEC_LEN];
2124
2125 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2126 next_index);
2127 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2128 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2129 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2130 }
2131
2132 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2133 u8 switch_prio, u8 tclass)
2134 {
2135 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2136 char qtct_pl[MLXSW_REG_QTCT_LEN];
2137
2138 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2139 tclass);
2140 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2141 }
2142
2143 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2144 {
2145 int err, i;
2146
2147 /* Setup the elements hierarcy, so that each TC is linked to
2148 * one subgroup, which are all member in the same group.
2149 */
2150 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2151 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2152 0);
2153 if (err)
2154 return err;
2155 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2156 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2157 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2158 0, false, 0);
2159 if (err)
2160 return err;
2161 }
2162 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2163 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2164 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2165 false, 0);
2166 if (err)
2167 return err;
2168 }
2169
2170 /* Make sure the max shaper is disabled in all hierarcies that
2171 * support it.
2172 */
2173 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2174 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2175 MLXSW_REG_QEEC_MAS_DIS);
2176 if (err)
2177 return err;
2178 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2179 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2180 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2181 i, 0,
2182 MLXSW_REG_QEEC_MAS_DIS);
2183 if (err)
2184 return err;
2185 }
2186 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2187 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2188 MLXSW_REG_QEEC_HIERARCY_TC,
2189 i, i,
2190 MLXSW_REG_QEEC_MAS_DIS);
2191 if (err)
2192 return err;
2193 }
2194
2195 /* Map all priorities to traffic class 0. */
2196 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2197 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2198 if (err)
2199 return err;
2200 }
2201
2202 return 0;
2203 }
2204
2205 static int mlxsw_sp_port_pvid_vport_create(struct mlxsw_sp_port *mlxsw_sp_port)
2206 {
2207 mlxsw_sp_port->pvid = 1;
2208
2209 return mlxsw_sp_port_add_vid(mlxsw_sp_port->dev, 0, 1);
2210 }
2211
2212 static int mlxsw_sp_port_pvid_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_port)
2213 {
2214 return mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
2215 }
2216
2217 static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2218 bool split, u8 module, u8 width, u8 lane)
2219 {
2220 struct mlxsw_sp_port *mlxsw_sp_port;
2221 struct net_device *dev;
2222 size_t bytes;
2223 int err;
2224
2225 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2226 if (!dev)
2227 return -ENOMEM;
2228 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
2229 mlxsw_sp_port = netdev_priv(dev);
2230 mlxsw_sp_port->dev = dev;
2231 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2232 mlxsw_sp_port->local_port = local_port;
2233 mlxsw_sp_port->split = split;
2234 mlxsw_sp_port->mapping.module = module;
2235 mlxsw_sp_port->mapping.width = width;
2236 mlxsw_sp_port->mapping.lane = lane;
2237 mlxsw_sp_port->link.autoneg = 1;
2238 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
2239 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
2240 if (!mlxsw_sp_port->active_vlans) {
2241 err = -ENOMEM;
2242 goto err_port_active_vlans_alloc;
2243 }
2244 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
2245 if (!mlxsw_sp_port->untagged_vlans) {
2246 err = -ENOMEM;
2247 goto err_port_untagged_vlans_alloc;
2248 }
2249 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
2250 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
2251
2252 mlxsw_sp_port->pcpu_stats =
2253 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2254 if (!mlxsw_sp_port->pcpu_stats) {
2255 err = -ENOMEM;
2256 goto err_alloc_stats;
2257 }
2258
2259 mlxsw_sp_port->hw_stats.cache =
2260 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2261
2262 if (!mlxsw_sp_port->hw_stats.cache) {
2263 err = -ENOMEM;
2264 goto err_alloc_hw_stats;
2265 }
2266 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2267 &update_stats_cache);
2268
2269 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2270 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2271
2272 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2273 if (err) {
2274 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2275 mlxsw_sp_port->local_port);
2276 goto err_port_swid_set;
2277 }
2278
2279 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2280 if (err) {
2281 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2282 mlxsw_sp_port->local_port);
2283 goto err_dev_addr_init;
2284 }
2285
2286 netif_carrier_off(dev);
2287
2288 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
2289 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2290 dev->hw_features |= NETIF_F_HW_TC;
2291
2292 dev->min_mtu = 0;
2293 dev->max_mtu = ETH_MAX_MTU;
2294
2295 /* Each packet needs to have a Tx header (metadata) on top all other
2296 * headers.
2297 */
2298 dev->needed_headroom = MLXSW_TXHDR_LEN;
2299
2300 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2301 if (err) {
2302 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2303 mlxsw_sp_port->local_port);
2304 goto err_port_system_port_mapping_set;
2305 }
2306
2307 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2308 if (err) {
2309 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2310 mlxsw_sp_port->local_port);
2311 goto err_port_speed_by_width_set;
2312 }
2313
2314 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2315 if (err) {
2316 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2317 mlxsw_sp_port->local_port);
2318 goto err_port_mtu_set;
2319 }
2320
2321 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2322 if (err)
2323 goto err_port_admin_status_set;
2324
2325 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2326 if (err) {
2327 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2328 mlxsw_sp_port->local_port);
2329 goto err_port_buffers_init;
2330 }
2331
2332 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2333 if (err) {
2334 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2335 mlxsw_sp_port->local_port);
2336 goto err_port_ets_init;
2337 }
2338
2339 /* ETS and buffers must be initialized before DCB. */
2340 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2341 if (err) {
2342 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2343 mlxsw_sp_port->local_port);
2344 goto err_port_dcb_init;
2345 }
2346
2347 err = mlxsw_sp_port_pvid_vport_create(mlxsw_sp_port);
2348 if (err) {
2349 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create PVID vPort\n",
2350 mlxsw_sp_port->local_port);
2351 goto err_port_pvid_vport_create;
2352 }
2353
2354 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
2355 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
2356 err = register_netdev(dev);
2357 if (err) {
2358 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2359 mlxsw_sp_port->local_port);
2360 goto err_register_netdev;
2361 }
2362
2363 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2364 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2365 module);
2366 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
2367 return 0;
2368
2369 err_register_netdev:
2370 mlxsw_sp->ports[local_port] = NULL;
2371 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
2372 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2373 err_port_pvid_vport_create:
2374 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
2375 err_port_dcb_init:
2376 err_port_ets_init:
2377 err_port_buffers_init:
2378 err_port_admin_status_set:
2379 err_port_mtu_set:
2380 err_port_speed_by_width_set:
2381 err_port_system_port_mapping_set:
2382 err_dev_addr_init:
2383 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2384 err_port_swid_set:
2385 kfree(mlxsw_sp_port->hw_stats.cache);
2386 err_alloc_hw_stats:
2387 free_percpu(mlxsw_sp_port->pcpu_stats);
2388 err_alloc_stats:
2389 kfree(mlxsw_sp_port->untagged_vlans);
2390 err_port_untagged_vlans_alloc:
2391 kfree(mlxsw_sp_port->active_vlans);
2392 err_port_active_vlans_alloc:
2393 free_netdev(dev);
2394 return err;
2395 }
2396
2397 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2398 bool split, u8 module, u8 width, u8 lane)
2399 {
2400 int err;
2401
2402 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2403 if (err) {
2404 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2405 local_port);
2406 return err;
2407 }
2408 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split,
2409 module, width, lane);
2410 if (err)
2411 goto err_port_create;
2412 return 0;
2413
2414 err_port_create:
2415 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2416 return err;
2417 }
2418
2419 static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2420 {
2421 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2422
2423 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
2424 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
2425 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
2426 mlxsw_sp->ports[local_port] = NULL;
2427 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
2428 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2429 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
2430 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2431 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
2432 free_percpu(mlxsw_sp_port->pcpu_stats);
2433 kfree(mlxsw_sp_port->hw_stats.cache);
2434 kfree(mlxsw_sp_port->untagged_vlans);
2435 kfree(mlxsw_sp_port->active_vlans);
2436 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
2437 free_netdev(mlxsw_sp_port->dev);
2438 }
2439
2440 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2441 {
2442 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2443 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2444 }
2445
2446 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2447 {
2448 return mlxsw_sp->ports[local_port] != NULL;
2449 }
2450
2451 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2452 {
2453 int i;
2454
2455 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
2456 if (mlxsw_sp_port_created(mlxsw_sp, i))
2457 mlxsw_sp_port_remove(mlxsw_sp, i);
2458 kfree(mlxsw_sp->ports);
2459 }
2460
2461 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2462 {
2463 u8 module, width, lane;
2464 size_t alloc_size;
2465 int i;
2466 int err;
2467
2468 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
2469 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2470 if (!mlxsw_sp->ports)
2471 return -ENOMEM;
2472
2473 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
2474 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
2475 &width, &lane);
2476 if (err)
2477 goto err_port_module_info_get;
2478 if (!width)
2479 continue;
2480 mlxsw_sp->port_to_module[i] = module;
2481 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
2482 module, width, lane);
2483 if (err)
2484 goto err_port_create;
2485 }
2486 return 0;
2487
2488 err_port_create:
2489 err_port_module_info_get:
2490 for (i--; i >= 1; i--)
2491 if (mlxsw_sp_port_created(mlxsw_sp, i))
2492 mlxsw_sp_port_remove(mlxsw_sp, i);
2493 kfree(mlxsw_sp->ports);
2494 return err;
2495 }
2496
2497 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
2498 {
2499 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
2500
2501 return local_port - offset;
2502 }
2503
2504 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
2505 u8 module, unsigned int count)
2506 {
2507 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
2508 int err, i;
2509
2510 for (i = 0; i < count; i++) {
2511 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
2512 width, i * width);
2513 if (err)
2514 goto err_port_module_map;
2515 }
2516
2517 for (i = 0; i < count; i++) {
2518 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
2519 if (err)
2520 goto err_port_swid_set;
2521 }
2522
2523 for (i = 0; i < count; i++) {
2524 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
2525 module, width, i * width);
2526 if (err)
2527 goto err_port_create;
2528 }
2529
2530 return 0;
2531
2532 err_port_create:
2533 for (i--; i >= 0; i--)
2534 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2535 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2536 i = count;
2537 err_port_swid_set:
2538 for (i--; i >= 0; i--)
2539 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
2540 MLXSW_PORT_SWID_DISABLED_PORT);
2541 i = count;
2542 err_port_module_map:
2543 for (i--; i >= 0; i--)
2544 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
2545 return err;
2546 }
2547
2548 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2549 u8 base_port, unsigned int count)
2550 {
2551 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
2552 int i;
2553
2554 /* Split by four means we need to re-create two ports, otherwise
2555 * only one.
2556 */
2557 count = count / 2;
2558
2559 for (i = 0; i < count; i++) {
2560 local_port = base_port + i * 2;
2561 module = mlxsw_sp->port_to_module[local_port];
2562
2563 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
2564 0);
2565 }
2566
2567 for (i = 0; i < count; i++)
2568 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
2569
2570 for (i = 0; i < count; i++) {
2571 local_port = base_port + i * 2;
2572 module = mlxsw_sp->port_to_module[local_port];
2573
2574 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
2575 width, 0);
2576 }
2577 }
2578
2579 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2580 unsigned int count)
2581 {
2582 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2583 struct mlxsw_sp_port *mlxsw_sp_port;
2584 u8 module, cur_width, base_port;
2585 int i;
2586 int err;
2587
2588 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2589 if (!mlxsw_sp_port) {
2590 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2591 local_port);
2592 return -EINVAL;
2593 }
2594
2595 module = mlxsw_sp_port->mapping.module;
2596 cur_width = mlxsw_sp_port->mapping.width;
2597
2598 if (count != 2 && count != 4) {
2599 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2600 return -EINVAL;
2601 }
2602
2603 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2604 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2605 return -EINVAL;
2606 }
2607
2608 /* Make sure we have enough slave (even) ports for the split. */
2609 if (count == 2) {
2610 base_port = local_port;
2611 if (mlxsw_sp->ports[base_port + 1]) {
2612 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2613 return -EINVAL;
2614 }
2615 } else {
2616 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2617 if (mlxsw_sp->ports[base_port + 1] ||
2618 mlxsw_sp->ports[base_port + 3]) {
2619 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2620 return -EINVAL;
2621 }
2622 }
2623
2624 for (i = 0; i < count; i++)
2625 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2626 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2627
2628 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2629 if (err) {
2630 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2631 goto err_port_split_create;
2632 }
2633
2634 return 0;
2635
2636 err_port_split_create:
2637 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
2638 return err;
2639 }
2640
2641 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
2642 {
2643 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2644 struct mlxsw_sp_port *mlxsw_sp_port;
2645 u8 cur_width, base_port;
2646 unsigned int count;
2647 int i;
2648
2649 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2650 if (!mlxsw_sp_port) {
2651 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2652 local_port);
2653 return -EINVAL;
2654 }
2655
2656 if (!mlxsw_sp_port->split) {
2657 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2658 return -EINVAL;
2659 }
2660
2661 cur_width = mlxsw_sp_port->mapping.width;
2662 count = cur_width == 1 ? 4 : 2;
2663
2664 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2665
2666 /* Determine which ports to remove. */
2667 if (count == 2 && local_port >= base_port + 2)
2668 base_port = base_port + 2;
2669
2670 for (i = 0; i < count; i++)
2671 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2672 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2673
2674 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
2675
2676 return 0;
2677 }
2678
2679 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2680 char *pude_pl, void *priv)
2681 {
2682 struct mlxsw_sp *mlxsw_sp = priv;
2683 struct mlxsw_sp_port *mlxsw_sp_port;
2684 enum mlxsw_reg_pude_oper_status status;
2685 u8 local_port;
2686
2687 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2688 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2689 if (!mlxsw_sp_port)
2690 return;
2691
2692 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2693 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2694 netdev_info(mlxsw_sp_port->dev, "link up\n");
2695 netif_carrier_on(mlxsw_sp_port->dev);
2696 } else {
2697 netdev_info(mlxsw_sp_port->dev, "link down\n");
2698 netif_carrier_off(mlxsw_sp_port->dev);
2699 }
2700 }
2701
2702 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
2703 u8 local_port, void *priv)
2704 {
2705 struct mlxsw_sp *mlxsw_sp = priv;
2706 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2707 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2708
2709 if (unlikely(!mlxsw_sp_port)) {
2710 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2711 local_port);
2712 return;
2713 }
2714
2715 skb->dev = mlxsw_sp_port->dev;
2716
2717 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2718 u64_stats_update_begin(&pcpu_stats->syncp);
2719 pcpu_stats->rx_packets++;
2720 pcpu_stats->rx_bytes += skb->len;
2721 u64_stats_update_end(&pcpu_stats->syncp);
2722
2723 skb->protocol = eth_type_trans(skb, skb->dev);
2724 netif_receive_skb(skb);
2725 }
2726
2727 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
2728 void *priv)
2729 {
2730 skb->offload_fwd_mark = 1;
2731 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
2732 }
2733
2734 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
2735 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
2736 _is_ctrl, SP_##_trap_group, DISCARD)
2737
2738 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
2739 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
2740 _is_ctrl, SP_##_trap_group, DISCARD)
2741
2742 #define MLXSW_SP_EVENTL(_func, _trap_id) \
2743 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
2744
2745 static const struct mlxsw_listener mlxsw_sp_listener[] = {
2746 /* Events */
2747 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
2748 /* L2 traps */
2749 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
2750 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
2751 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
2752 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
2753 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
2754 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
2755 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
2756 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
2757 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
2758 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
2759 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
2760 /* L3 traps */
2761 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2762 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2763 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
2764 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
2765 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
2766 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
2767 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
2768 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
2769 };
2770
2771 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
2772 {
2773 char qpcr_pl[MLXSW_REG_QPCR_LEN];
2774 enum mlxsw_reg_qpcr_ir_units ir_units;
2775 int max_cpu_policers;
2776 bool is_bytes;
2777 u8 burst_size;
2778 u32 rate;
2779 int i, err;
2780
2781 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
2782 return -EIO;
2783
2784 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2785
2786 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
2787 for (i = 0; i < max_cpu_policers; i++) {
2788 is_bytes = false;
2789 switch (i) {
2790 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
2791 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
2792 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
2793 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
2794 rate = 128;
2795 burst_size = 7;
2796 break;
2797 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
2798 rate = 16 * 1024;
2799 burst_size = 10;
2800 break;
2801 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
2802 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
2803 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
2804 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
2805 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2806 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
2807 rate = 1024;
2808 burst_size = 7;
2809 break;
2810 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
2811 is_bytes = true;
2812 rate = 4 * 1024;
2813 burst_size = 4;
2814 break;
2815 default:
2816 continue;
2817 }
2818
2819 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
2820 burst_size);
2821 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
2822 if (err)
2823 return err;
2824 }
2825
2826 return 0;
2827 }
2828
2829 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
2830 {
2831 char htgt_pl[MLXSW_REG_HTGT_LEN];
2832 enum mlxsw_reg_htgt_trap_group i;
2833 int max_cpu_policers;
2834 int max_trap_groups;
2835 u8 priority, tc;
2836 u16 policer_id;
2837 int err;
2838
2839 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
2840 return -EIO;
2841
2842 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
2843 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2844
2845 for (i = 0; i < max_trap_groups; i++) {
2846 policer_id = i;
2847 switch (i) {
2848 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
2849 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
2850 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
2851 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
2852 priority = 5;
2853 tc = 5;
2854 break;
2855 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
2856 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
2857 priority = 4;
2858 tc = 4;
2859 break;
2860 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
2861 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
2862 priority = 3;
2863 tc = 3;
2864 break;
2865 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
2866 priority = 2;
2867 tc = 2;
2868 break;
2869 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
2870 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2871 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
2872 priority = 1;
2873 tc = 1;
2874 break;
2875 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
2876 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
2877 tc = MLXSW_REG_HTGT_DEFAULT_TC;
2878 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
2879 break;
2880 default:
2881 continue;
2882 }
2883
2884 if (max_cpu_policers <= policer_id &&
2885 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
2886 return -EIO;
2887
2888 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
2889 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
2890 if (err)
2891 return err;
2892 }
2893
2894 return 0;
2895 }
2896
2897 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2898 {
2899 int i;
2900 int err;
2901
2902 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
2903 if (err)
2904 return err;
2905
2906 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
2907 if (err)
2908 return err;
2909
2910 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
2911 err = mlxsw_core_trap_register(mlxsw_sp->core,
2912 &mlxsw_sp_listener[i],
2913 mlxsw_sp);
2914 if (err)
2915 goto err_listener_register;
2916
2917 }
2918 return 0;
2919
2920 err_listener_register:
2921 for (i--; i >= 0; i--) {
2922 mlxsw_core_trap_unregister(mlxsw_sp->core,
2923 &mlxsw_sp_listener[i],
2924 mlxsw_sp);
2925 }
2926 return err;
2927 }
2928
2929 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2930 {
2931 int i;
2932
2933 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
2934 mlxsw_core_trap_unregister(mlxsw_sp->core,
2935 &mlxsw_sp_listener[i],
2936 mlxsw_sp);
2937 }
2938 }
2939
2940 static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2941 enum mlxsw_reg_sfgc_type type,
2942 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2943 {
2944 enum mlxsw_flood_table_type table_type;
2945 enum mlxsw_sp_flood_table flood_table;
2946 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2947
2948 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
2949 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
2950 else
2951 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
2952
2953 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2954 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2955 else
2956 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
2957
2958 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2959 flood_table);
2960 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2961 }
2962
2963 static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2964 {
2965 int type, err;
2966
2967 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2968 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2969 continue;
2970
2971 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2972 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2973 if (err)
2974 return err;
2975
2976 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2977 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2978 if (err)
2979 return err;
2980 }
2981
2982 return 0;
2983 }
2984
2985 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2986 {
2987 char slcr_pl[MLXSW_REG_SLCR_LEN];
2988 int err;
2989
2990 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2991 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2992 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2993 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2994 MLXSW_REG_SLCR_LAG_HASH_SIP |
2995 MLXSW_REG_SLCR_LAG_HASH_DIP |
2996 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2997 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2998 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2999 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3000 if (err)
3001 return err;
3002
3003 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3004 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
3005 return -EIO;
3006
3007 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
3008 sizeof(struct mlxsw_sp_upper),
3009 GFP_KERNEL);
3010 if (!mlxsw_sp->lags)
3011 return -ENOMEM;
3012
3013 return 0;
3014 }
3015
3016 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3017 {
3018 kfree(mlxsw_sp->lags);
3019 }
3020
3021 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3022 {
3023 char htgt_pl[MLXSW_REG_HTGT_LEN];
3024
3025 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3026 MLXSW_REG_HTGT_INVALID_POLICER,
3027 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3028 MLXSW_REG_HTGT_DEFAULT_TC);
3029 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3030 }
3031
3032 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3033 const struct mlxsw_bus_info *mlxsw_bus_info)
3034 {
3035 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3036 int err;
3037
3038 mlxsw_sp->core = mlxsw_core;
3039 mlxsw_sp->bus_info = mlxsw_bus_info;
3040 INIT_LIST_HEAD(&mlxsw_sp->fids);
3041 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
3042 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
3043
3044 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3045 if (err) {
3046 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3047 return err;
3048 }
3049
3050 err = mlxsw_sp_traps_init(mlxsw_sp);
3051 if (err) {
3052 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3053 return err;
3054 }
3055
3056 err = mlxsw_sp_flood_init(mlxsw_sp);
3057 if (err) {
3058 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
3059 goto err_flood_init;
3060 }
3061
3062 err = mlxsw_sp_buffers_init(mlxsw_sp);
3063 if (err) {
3064 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3065 goto err_buffers_init;
3066 }
3067
3068 err = mlxsw_sp_lag_init(mlxsw_sp);
3069 if (err) {
3070 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3071 goto err_lag_init;
3072 }
3073
3074 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3075 if (err) {
3076 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3077 goto err_switchdev_init;
3078 }
3079
3080 err = mlxsw_sp_router_init(mlxsw_sp);
3081 if (err) {
3082 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3083 goto err_router_init;
3084 }
3085
3086 err = mlxsw_sp_span_init(mlxsw_sp);
3087 if (err) {
3088 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3089 goto err_span_init;
3090 }
3091
3092 err = mlxsw_sp_ports_create(mlxsw_sp);
3093 if (err) {
3094 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3095 goto err_ports_create;
3096 }
3097
3098 return 0;
3099
3100 err_ports_create:
3101 mlxsw_sp_span_fini(mlxsw_sp);
3102 err_span_init:
3103 mlxsw_sp_router_fini(mlxsw_sp);
3104 err_router_init:
3105 mlxsw_sp_switchdev_fini(mlxsw_sp);
3106 err_switchdev_init:
3107 mlxsw_sp_lag_fini(mlxsw_sp);
3108 err_lag_init:
3109 mlxsw_sp_buffers_fini(mlxsw_sp);
3110 err_buffers_init:
3111 err_flood_init:
3112 mlxsw_sp_traps_fini(mlxsw_sp);
3113 return err;
3114 }
3115
3116 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3117 {
3118 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3119
3120 mlxsw_sp_ports_remove(mlxsw_sp);
3121 mlxsw_sp_span_fini(mlxsw_sp);
3122 mlxsw_sp_router_fini(mlxsw_sp);
3123 mlxsw_sp_switchdev_fini(mlxsw_sp);
3124 mlxsw_sp_lag_fini(mlxsw_sp);
3125 mlxsw_sp_buffers_fini(mlxsw_sp);
3126 mlxsw_sp_traps_fini(mlxsw_sp);
3127 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
3128 WARN_ON(!list_empty(&mlxsw_sp->fids));
3129 }
3130
3131 static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3132 .used_max_vepa_channels = 1,
3133 .max_vepa_channels = 0,
3134 .used_max_mid = 1,
3135 .max_mid = MLXSW_SP_MID_MAX,
3136 .used_max_pgt = 1,
3137 .max_pgt = 0,
3138 .used_flood_tables = 1,
3139 .used_flood_mode = 1,
3140 .flood_mode = 3,
3141 .max_fid_offset_flood_tables = 2,
3142 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3143 .max_fid_flood_tables = 2,
3144 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
3145 .used_max_ib_mc = 1,
3146 .max_ib_mc = 0,
3147 .used_max_pkey = 1,
3148 .max_pkey = 0,
3149 .used_kvd_split_data = 1,
3150 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3151 .kvd_hash_single_parts = 2,
3152 .kvd_hash_double_parts = 1,
3153 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
3154 .swid_config = {
3155 {
3156 .used_type = 1,
3157 .type = MLXSW_PORT_SWID_TYPE_ETH,
3158 }
3159 },
3160 .resource_query_enable = 1,
3161 };
3162
3163 static struct mlxsw_driver mlxsw_sp_driver = {
3164 .kind = mlxsw_sp_driver_name,
3165 .priv_size = sizeof(struct mlxsw_sp),
3166 .init = mlxsw_sp_init,
3167 .fini = mlxsw_sp_fini,
3168 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
3169 .port_split = mlxsw_sp_port_split,
3170 .port_unsplit = mlxsw_sp_port_unsplit,
3171 .sb_pool_get = mlxsw_sp_sb_pool_get,
3172 .sb_pool_set = mlxsw_sp_sb_pool_set,
3173 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3174 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3175 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3176 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3177 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3178 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3179 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3180 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3181 .txhdr_construct = mlxsw_sp_txhdr_construct,
3182 .txhdr_len = MLXSW_TXHDR_LEN,
3183 .profile = &mlxsw_sp_config_profile,
3184 };
3185
3186 static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
3187 {
3188 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3189 }
3190
3191 static int mlxsw_lower_dev_walk(struct net_device *lower_dev, void *data)
3192 {
3193 struct mlxsw_sp_port **port = data;
3194 int ret = 0;
3195
3196 if (mlxsw_sp_port_dev_check(lower_dev)) {
3197 *port = netdev_priv(lower_dev);
3198 ret = 1;
3199 }
3200
3201 return ret;
3202 }
3203
3204 static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3205 {
3206 struct mlxsw_sp_port *port;
3207
3208 if (mlxsw_sp_port_dev_check(dev))
3209 return netdev_priv(dev);
3210
3211 port = NULL;
3212 netdev_walk_all_lower_dev(dev, mlxsw_lower_dev_walk, &port);
3213
3214 return port;
3215 }
3216
3217 static struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
3218 {
3219 struct mlxsw_sp_port *mlxsw_sp_port;
3220
3221 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3222 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3223 }
3224
3225 static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3226 {
3227 struct mlxsw_sp_port *port;
3228
3229 if (mlxsw_sp_port_dev_check(dev))
3230 return netdev_priv(dev);
3231
3232 port = NULL;
3233 netdev_walk_all_lower_dev_rcu(dev, mlxsw_lower_dev_walk, &port);
3234
3235 return port;
3236 }
3237
3238 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3239 {
3240 struct mlxsw_sp_port *mlxsw_sp_port;
3241
3242 rcu_read_lock();
3243 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3244 if (mlxsw_sp_port)
3245 dev_hold(mlxsw_sp_port->dev);
3246 rcu_read_unlock();
3247 return mlxsw_sp_port;
3248 }
3249
3250 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3251 {
3252 dev_put(mlxsw_sp_port->dev);
3253 }
3254
3255 static bool mlxsw_sp_rif_should_config(struct mlxsw_sp_rif *r,
3256 unsigned long event)
3257 {
3258 switch (event) {
3259 case NETDEV_UP:
3260 if (!r)
3261 return true;
3262 r->ref_count++;
3263 return false;
3264 case NETDEV_DOWN:
3265 if (r && --r->ref_count == 0)
3266 return true;
3267 /* It is possible we already removed the RIF ourselves
3268 * if it was assigned to a netdev that is now a bridge
3269 * or LAG slave.
3270 */
3271 return false;
3272 }
3273
3274 return false;
3275 }
3276
3277 static int mlxsw_sp_avail_rif_get(struct mlxsw_sp *mlxsw_sp)
3278 {
3279 int i;
3280
3281 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++)
3282 if (!mlxsw_sp->rifs[i])
3283 return i;
3284
3285 return MLXSW_SP_INVALID_RIF;
3286 }
3287
3288 static void mlxsw_sp_vport_rif_sp_attr_get(struct mlxsw_sp_port *mlxsw_sp_vport,
3289 bool *p_lagged, u16 *p_system_port)
3290 {
3291 u8 local_port = mlxsw_sp_vport->local_port;
3292
3293 *p_lagged = mlxsw_sp_vport->lagged;
3294 *p_system_port = *p_lagged ? mlxsw_sp_vport->lag_id : local_port;
3295 }
3296
3297 static int mlxsw_sp_vport_rif_sp_op(struct mlxsw_sp_port *mlxsw_sp_vport,
3298 struct net_device *l3_dev, u16 rif,
3299 bool create)
3300 {
3301 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3302 bool lagged = mlxsw_sp_vport->lagged;
3303 char ritr_pl[MLXSW_REG_RITR_LEN];
3304 u16 system_port;
3305
3306 mlxsw_reg_ritr_pack(ritr_pl, create, MLXSW_REG_RITR_SP_IF, rif,
3307 l3_dev->mtu, l3_dev->dev_addr);
3308
3309 mlxsw_sp_vport_rif_sp_attr_get(mlxsw_sp_vport, &lagged, &system_port);
3310 mlxsw_reg_ritr_sp_if_pack(ritr_pl, lagged, system_port,
3311 mlxsw_sp_vport_vid_get(mlxsw_sp_vport));
3312
3313 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3314 }
3315
3316 static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
3317
3318 static struct mlxsw_sp_fid *
3319 mlxsw_sp_rfid_alloc(u16 fid, struct net_device *l3_dev)
3320 {
3321 struct mlxsw_sp_fid *f;
3322
3323 f = kzalloc(sizeof(*f), GFP_KERNEL);
3324 if (!f)
3325 return NULL;
3326
3327 f->leave = mlxsw_sp_vport_rif_sp_leave;
3328 f->ref_count = 0;
3329 f->dev = l3_dev;
3330 f->fid = fid;
3331
3332 return f;
3333 }
3334
3335 static struct mlxsw_sp_rif *
3336 mlxsw_sp_rif_alloc(u16 rif, struct net_device *l3_dev, struct mlxsw_sp_fid *f)
3337 {
3338 struct mlxsw_sp_rif *r;
3339
3340 r = kzalloc(sizeof(*r), GFP_KERNEL);
3341 if (!r)
3342 return NULL;
3343
3344 ether_addr_copy(r->addr, l3_dev->dev_addr);
3345 r->mtu = l3_dev->mtu;
3346 r->ref_count = 1;
3347 r->dev = l3_dev;
3348 r->rif = rif;
3349 r->f = f;
3350
3351 return r;
3352 }
3353
3354 static struct mlxsw_sp_rif *
3355 mlxsw_sp_vport_rif_sp_create(struct mlxsw_sp_port *mlxsw_sp_vport,
3356 struct net_device *l3_dev)
3357 {
3358 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3359 struct mlxsw_sp_fid *f;
3360 struct mlxsw_sp_rif *r;
3361 u16 fid, rif;
3362 int err;
3363
3364 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
3365 if (rif == MLXSW_SP_INVALID_RIF)
3366 return ERR_PTR(-ERANGE);
3367
3368 err = mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, true);
3369 if (err)
3370 return ERR_PTR(err);
3371
3372 fid = mlxsw_sp_rif_sp_to_fid(rif);
3373 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, true);
3374 if (err)
3375 goto err_rif_fdb_op;
3376
3377 f = mlxsw_sp_rfid_alloc(fid, l3_dev);
3378 if (!f) {
3379 err = -ENOMEM;
3380 goto err_rfid_alloc;
3381 }
3382
3383 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
3384 if (!r) {
3385 err = -ENOMEM;
3386 goto err_rif_alloc;
3387 }
3388
3389 f->r = r;
3390 mlxsw_sp->rifs[rif] = r;
3391
3392 return r;
3393
3394 err_rif_alloc:
3395 kfree(f);
3396 err_rfid_alloc:
3397 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
3398 err_rif_fdb_op:
3399 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
3400 return ERR_PTR(err);
3401 }
3402
3403 static void mlxsw_sp_vport_rif_sp_destroy(struct mlxsw_sp_port *mlxsw_sp_vport,
3404 struct mlxsw_sp_rif *r)
3405 {
3406 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3407 struct net_device *l3_dev = r->dev;
3408 struct mlxsw_sp_fid *f = r->f;
3409 u16 fid = f->fid;
3410 u16 rif = r->rif;
3411
3412 mlxsw_sp->rifs[rif] = NULL;
3413 f->r = NULL;
3414
3415 kfree(r);
3416
3417 kfree(f);
3418
3419 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, fid, false);
3420
3421 mlxsw_sp_vport_rif_sp_op(mlxsw_sp_vport, l3_dev, rif, false);
3422 }
3423
3424 static int mlxsw_sp_vport_rif_sp_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3425 struct net_device *l3_dev)
3426 {
3427 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3428 struct mlxsw_sp_rif *r;
3429
3430 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, l3_dev);
3431 if (!r) {
3432 r = mlxsw_sp_vport_rif_sp_create(mlxsw_sp_vport, l3_dev);
3433 if (IS_ERR(r))
3434 return PTR_ERR(r);
3435 }
3436
3437 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, r->f);
3438 r->f->ref_count++;
3439
3440 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", r->f->fid);
3441
3442 return 0;
3443 }
3444
3445 static void mlxsw_sp_vport_rif_sp_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3446 {
3447 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
3448
3449 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
3450
3451 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
3452 if (--f->ref_count == 0)
3453 mlxsw_sp_vport_rif_sp_destroy(mlxsw_sp_vport, f->r);
3454 }
3455
3456 static int mlxsw_sp_inetaddr_vport_event(struct net_device *l3_dev,
3457 struct net_device *port_dev,
3458 unsigned long event, u16 vid)
3459 {
3460 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(port_dev);
3461 struct mlxsw_sp_port *mlxsw_sp_vport;
3462
3463 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3464 if (WARN_ON(!mlxsw_sp_vport))
3465 return -EINVAL;
3466
3467 switch (event) {
3468 case NETDEV_UP:
3469 return mlxsw_sp_vport_rif_sp_join(mlxsw_sp_vport, l3_dev);
3470 case NETDEV_DOWN:
3471 mlxsw_sp_vport_rif_sp_leave(mlxsw_sp_vport);
3472 break;
3473 }
3474
3475 return 0;
3476 }
3477
3478 static int mlxsw_sp_inetaddr_port_event(struct net_device *port_dev,
3479 unsigned long event)
3480 {
3481 if (netif_is_bridge_port(port_dev) || netif_is_lag_port(port_dev))
3482 return 0;
3483
3484 return mlxsw_sp_inetaddr_vport_event(port_dev, port_dev, event, 1);
3485 }
3486
3487 static int __mlxsw_sp_inetaddr_lag_event(struct net_device *l3_dev,
3488 struct net_device *lag_dev,
3489 unsigned long event, u16 vid)
3490 {
3491 struct net_device *port_dev;
3492 struct list_head *iter;
3493 int err;
3494
3495 netdev_for_each_lower_dev(lag_dev, port_dev, iter) {
3496 if (mlxsw_sp_port_dev_check(port_dev)) {
3497 err = mlxsw_sp_inetaddr_vport_event(l3_dev, port_dev,
3498 event, vid);
3499 if (err)
3500 return err;
3501 }
3502 }
3503
3504 return 0;
3505 }
3506
3507 static int mlxsw_sp_inetaddr_lag_event(struct net_device *lag_dev,
3508 unsigned long event)
3509 {
3510 if (netif_is_bridge_port(lag_dev))
3511 return 0;
3512
3513 return __mlxsw_sp_inetaddr_lag_event(lag_dev, lag_dev, event, 1);
3514 }
3515
3516 static struct mlxsw_sp_fid *mlxsw_sp_bridge_fid_get(struct mlxsw_sp *mlxsw_sp,
3517 struct net_device *l3_dev)
3518 {
3519 u16 fid;
3520
3521 if (is_vlan_dev(l3_dev))
3522 fid = vlan_dev_vlan_id(l3_dev);
3523 else if (mlxsw_sp->master_bridge.dev == l3_dev)
3524 fid = 1;
3525 else
3526 return mlxsw_sp_vfid_find(mlxsw_sp, l3_dev);
3527
3528 return mlxsw_sp_fid_find(mlxsw_sp, fid);
3529 }
3530
3531 static enum mlxsw_flood_table_type mlxsw_sp_flood_table_type_get(u16 fid)
3532 {
3533 return mlxsw_sp_fid_is_vfid(fid) ? MLXSW_REG_SFGC_TABLE_TYPE_FID :
3534 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
3535 }
3536
3537 static u16 mlxsw_sp_flood_table_index_get(u16 fid)
3538 {
3539 return mlxsw_sp_fid_is_vfid(fid) ? mlxsw_sp_fid_to_vfid(fid) : fid;
3540 }
3541
3542 static int mlxsw_sp_router_port_flood_set(struct mlxsw_sp *mlxsw_sp, u16 fid,
3543 bool set)
3544 {
3545 enum mlxsw_flood_table_type table_type;
3546 char *sftr_pl;
3547 u16 index;
3548 int err;
3549
3550 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
3551 if (!sftr_pl)
3552 return -ENOMEM;
3553
3554 table_type = mlxsw_sp_flood_table_type_get(fid);
3555 index = mlxsw_sp_flood_table_index_get(fid);
3556 mlxsw_reg_sftr_pack(sftr_pl, MLXSW_SP_FLOOD_TABLE_BM, index, table_type,
3557 1, MLXSW_PORT_ROUTER_PORT, set);
3558 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sftr), sftr_pl);
3559
3560 kfree(sftr_pl);
3561 return err;
3562 }
3563
3564 static enum mlxsw_reg_ritr_if_type mlxsw_sp_rif_type_get(u16 fid)
3565 {
3566 if (mlxsw_sp_fid_is_vfid(fid))
3567 return MLXSW_REG_RITR_FID_IF;
3568 else
3569 return MLXSW_REG_RITR_VLAN_IF;
3570 }
3571
3572 static int mlxsw_sp_rif_bridge_op(struct mlxsw_sp *mlxsw_sp,
3573 struct net_device *l3_dev,
3574 u16 fid, u16 rif,
3575 bool create)
3576 {
3577 enum mlxsw_reg_ritr_if_type rif_type;
3578 char ritr_pl[MLXSW_REG_RITR_LEN];
3579
3580 rif_type = mlxsw_sp_rif_type_get(fid);
3581 mlxsw_reg_ritr_pack(ritr_pl, create, rif_type, rif, l3_dev->mtu,
3582 l3_dev->dev_addr);
3583 mlxsw_reg_ritr_fid_set(ritr_pl, rif_type, fid);
3584
3585 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3586 }
3587
3588 static int mlxsw_sp_rif_bridge_create(struct mlxsw_sp *mlxsw_sp,
3589 struct net_device *l3_dev,
3590 struct mlxsw_sp_fid *f)
3591 {
3592 struct mlxsw_sp_rif *r;
3593 u16 rif;
3594 int err;
3595
3596 rif = mlxsw_sp_avail_rif_get(mlxsw_sp);
3597 if (rif == MLXSW_SP_INVALID_RIF)
3598 return -ERANGE;
3599
3600 err = mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, true);
3601 if (err)
3602 return err;
3603
3604 err = mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, true);
3605 if (err)
3606 goto err_rif_bridge_op;
3607
3608 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, true);
3609 if (err)
3610 goto err_rif_fdb_op;
3611
3612 r = mlxsw_sp_rif_alloc(rif, l3_dev, f);
3613 if (!r) {
3614 err = -ENOMEM;
3615 goto err_rif_alloc;
3616 }
3617
3618 f->r = r;
3619 mlxsw_sp->rifs[rif] = r;
3620
3621 netdev_dbg(l3_dev, "RIF=%d created\n", rif);
3622
3623 return 0;
3624
3625 err_rif_alloc:
3626 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
3627 err_rif_fdb_op:
3628 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
3629 err_rif_bridge_op:
3630 mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, false);
3631 return err;
3632 }
3633
3634 void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp *mlxsw_sp,
3635 struct mlxsw_sp_rif *r)
3636 {
3637 struct net_device *l3_dev = r->dev;
3638 struct mlxsw_sp_fid *f = r->f;
3639 u16 rif = r->rif;
3640
3641 mlxsw_sp->rifs[rif] = NULL;
3642 f->r = NULL;
3643
3644 kfree(r);
3645
3646 mlxsw_sp_rif_fdb_op(mlxsw_sp, l3_dev->dev_addr, f->fid, false);
3647
3648 mlxsw_sp_rif_bridge_op(mlxsw_sp, l3_dev, f->fid, rif, false);
3649
3650 mlxsw_sp_router_port_flood_set(mlxsw_sp, f->fid, false);
3651
3652 netdev_dbg(l3_dev, "RIF=%d destroyed\n", rif);
3653 }
3654
3655 static int mlxsw_sp_inetaddr_bridge_event(struct net_device *l3_dev,
3656 struct net_device *br_dev,
3657 unsigned long event)
3658 {
3659 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(l3_dev);
3660 struct mlxsw_sp_fid *f;
3661
3662 /* FID can either be an actual FID if the L3 device is the
3663 * VLAN-aware bridge or a VLAN device on top. Otherwise, the
3664 * L3 device is a VLAN-unaware bridge and we get a vFID.
3665 */
3666 f = mlxsw_sp_bridge_fid_get(mlxsw_sp, l3_dev);
3667 if (WARN_ON(!f))
3668 return -EINVAL;
3669
3670 switch (event) {
3671 case NETDEV_UP:
3672 return mlxsw_sp_rif_bridge_create(mlxsw_sp, l3_dev, f);
3673 case NETDEV_DOWN:
3674 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
3675 break;
3676 }
3677
3678 return 0;
3679 }
3680
3681 static int mlxsw_sp_inetaddr_vlan_event(struct net_device *vlan_dev,
3682 unsigned long event)
3683 {
3684 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3685 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
3686 u16 vid = vlan_dev_vlan_id(vlan_dev);
3687
3688 if (mlxsw_sp_port_dev_check(real_dev))
3689 return mlxsw_sp_inetaddr_vport_event(vlan_dev, real_dev, event,
3690 vid);
3691 else if (netif_is_lag_master(real_dev))
3692 return __mlxsw_sp_inetaddr_lag_event(vlan_dev, real_dev, event,
3693 vid);
3694 else if (netif_is_bridge_master(real_dev) &&
3695 mlxsw_sp->master_bridge.dev == real_dev)
3696 return mlxsw_sp_inetaddr_bridge_event(vlan_dev, real_dev,
3697 event);
3698
3699 return 0;
3700 }
3701
3702 static int mlxsw_sp_inetaddr_event(struct notifier_block *unused,
3703 unsigned long event, void *ptr)
3704 {
3705 struct in_ifaddr *ifa = (struct in_ifaddr *) ptr;
3706 struct net_device *dev = ifa->ifa_dev->dev;
3707 struct mlxsw_sp *mlxsw_sp;
3708 struct mlxsw_sp_rif *r;
3709 int err = 0;
3710
3711 mlxsw_sp = mlxsw_sp_lower_get(dev);
3712 if (!mlxsw_sp)
3713 goto out;
3714
3715 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
3716 if (!mlxsw_sp_rif_should_config(r, event))
3717 goto out;
3718
3719 if (mlxsw_sp_port_dev_check(dev))
3720 err = mlxsw_sp_inetaddr_port_event(dev, event);
3721 else if (netif_is_lag_master(dev))
3722 err = mlxsw_sp_inetaddr_lag_event(dev, event);
3723 else if (netif_is_bridge_master(dev))
3724 err = mlxsw_sp_inetaddr_bridge_event(dev, dev, event);
3725 else if (is_vlan_dev(dev))
3726 err = mlxsw_sp_inetaddr_vlan_event(dev, event);
3727
3728 out:
3729 return notifier_from_errno(err);
3730 }
3731
3732 static int mlxsw_sp_rif_edit(struct mlxsw_sp *mlxsw_sp, u16 rif,
3733 const char *mac, int mtu)
3734 {
3735 char ritr_pl[MLXSW_REG_RITR_LEN];
3736 int err;
3737
3738 mlxsw_reg_ritr_rif_pack(ritr_pl, rif);
3739 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3740 if (err)
3741 return err;
3742
3743 mlxsw_reg_ritr_mtu_set(ritr_pl, mtu);
3744 mlxsw_reg_ritr_if_mac_memcpy_to(ritr_pl, mac);
3745 mlxsw_reg_ritr_op_set(ritr_pl, MLXSW_REG_RITR_RIF_CREATE);
3746 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
3747 }
3748
3749 static int mlxsw_sp_netdevice_router_port_event(struct net_device *dev)
3750 {
3751 struct mlxsw_sp *mlxsw_sp;
3752 struct mlxsw_sp_rif *r;
3753 int err;
3754
3755 mlxsw_sp = mlxsw_sp_lower_get(dev);
3756 if (!mlxsw_sp)
3757 return 0;
3758
3759 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
3760 if (!r)
3761 return 0;
3762
3763 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, false);
3764 if (err)
3765 return err;
3766
3767 err = mlxsw_sp_rif_edit(mlxsw_sp, r->rif, dev->dev_addr, dev->mtu);
3768 if (err)
3769 goto err_rif_edit;
3770
3771 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, dev->dev_addr, r->f->fid, true);
3772 if (err)
3773 goto err_rif_fdb_op;
3774
3775 ether_addr_copy(r->addr, dev->dev_addr);
3776 r->mtu = dev->mtu;
3777
3778 netdev_dbg(dev, "Updated RIF=%d\n", r->rif);
3779
3780 return 0;
3781
3782 err_rif_fdb_op:
3783 mlxsw_sp_rif_edit(mlxsw_sp, r->rif, r->addr, r->mtu);
3784 err_rif_edit:
3785 mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, true);
3786 return err;
3787 }
3788
3789 static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3790 u16 fid)
3791 {
3792 if (mlxsw_sp_fid_is_vfid(fid))
3793 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3794 else
3795 return test_bit(fid, lag_port->active_vlans);
3796 }
3797
3798 static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3799 u16 fid)
3800 {
3801 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3802 u8 local_port = mlxsw_sp_port->local_port;
3803 u16 lag_id = mlxsw_sp_port->lag_id;
3804 u64 max_lag_members;
3805 int i, count = 0;
3806
3807 if (!mlxsw_sp_port->lagged)
3808 return true;
3809
3810 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3811 MAX_LAG_MEMBERS);
3812 for (i = 0; i < max_lag_members; i++) {
3813 struct mlxsw_sp_port *lag_port;
3814
3815 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3816 if (!lag_port || lag_port->local_port == local_port)
3817 continue;
3818 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3819 count++;
3820 }
3821
3822 return !count;
3823 }
3824
3825 static int
3826 mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3827 u16 fid)
3828 {
3829 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3830 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3831
3832 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3833 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3834 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3835 mlxsw_sp_port->local_port);
3836
3837 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3838 mlxsw_sp_port->local_port, fid);
3839
3840 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3841 }
3842
3843 static int
3844 mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3845 u16 fid)
3846 {
3847 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3848 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3849
3850 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3851 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3852 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3853
3854 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3855 mlxsw_sp_port->lag_id, fid);
3856
3857 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3858 }
3859
3860 int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
3861 {
3862 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3863 return 0;
3864
3865 if (mlxsw_sp_port->lagged)
3866 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
3867 fid);
3868 else
3869 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
3870 }
3871
3872 static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3873 {
3874 struct mlxsw_sp_fid *f, *tmp;
3875
3876 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3877 if (--f->ref_count == 0)
3878 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3879 else
3880 WARN_ON_ONCE(1);
3881 }
3882
3883 static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3884 struct net_device *br_dev)
3885 {
3886 return !mlxsw_sp->master_bridge.dev ||
3887 mlxsw_sp->master_bridge.dev == br_dev;
3888 }
3889
3890 static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
3891 struct net_device *br_dev)
3892 {
3893 mlxsw_sp->master_bridge.dev = br_dev;
3894 mlxsw_sp->master_bridge.ref_count++;
3895 }
3896
3897 static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
3898 {
3899 if (--mlxsw_sp->master_bridge.ref_count == 0) {
3900 mlxsw_sp->master_bridge.dev = NULL;
3901 /* It's possible upper VLAN devices are still holding
3902 * references to underlying FIDs. Drop the reference
3903 * and release the resources if it was the last one.
3904 * If it wasn't, then something bad happened.
3905 */
3906 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
3907 }
3908 }
3909
3910 static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
3911 struct net_device *br_dev)
3912 {
3913 struct net_device *dev = mlxsw_sp_port->dev;
3914 int err;
3915
3916 /* When port is not bridged untagged packets are tagged with
3917 * PVID=VID=1, thereby creating an implicit VLAN interface in
3918 * the device. Remove it and let bridge code take care of its
3919 * own VLANs.
3920 */
3921 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
3922 if (err)
3923 return err;
3924
3925 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
3926
3927 mlxsw_sp_port->learning = 1;
3928 mlxsw_sp_port->learning_sync = 1;
3929 mlxsw_sp_port->uc_flood = 1;
3930 mlxsw_sp_port->bridged = 1;
3931
3932 return 0;
3933 }
3934
3935 static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
3936 {
3937 struct net_device *dev = mlxsw_sp_port->dev;
3938
3939 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
3940
3941 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
3942
3943 mlxsw_sp_port->learning = 0;
3944 mlxsw_sp_port->learning_sync = 0;
3945 mlxsw_sp_port->uc_flood = 0;
3946 mlxsw_sp_port->bridged = 0;
3947
3948 /* Add implicit VLAN interface in the device, so that untagged
3949 * packets will be classified to the default vFID.
3950 */
3951 mlxsw_sp_port_add_vid(dev, 0, 1);
3952 }
3953
3954 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3955 {
3956 char sldr_pl[MLXSW_REG_SLDR_LEN];
3957
3958 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3959 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3960 }
3961
3962 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3963 {
3964 char sldr_pl[MLXSW_REG_SLDR_LEN];
3965
3966 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3967 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3968 }
3969
3970 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3971 u16 lag_id, u8 port_index)
3972 {
3973 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3974 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3975
3976 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3977 lag_id, port_index);
3978 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3979 }
3980
3981 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3982 u16 lag_id)
3983 {
3984 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3985 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3986
3987 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3988 lag_id);
3989 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3990 }
3991
3992 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3993 u16 lag_id)
3994 {
3995 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3996 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3997
3998 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3999 lag_id);
4000 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4001 }
4002
4003 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4004 u16 lag_id)
4005 {
4006 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4007 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4008
4009 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4010 lag_id);
4011 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4012 }
4013
4014 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4015 struct net_device *lag_dev,
4016 u16 *p_lag_id)
4017 {
4018 struct mlxsw_sp_upper *lag;
4019 int free_lag_id = -1;
4020 u64 max_lag;
4021 int i;
4022
4023 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4024 for (i = 0; i < max_lag; i++) {
4025 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4026 if (lag->ref_count) {
4027 if (lag->dev == lag_dev) {
4028 *p_lag_id = i;
4029 return 0;
4030 }
4031 } else if (free_lag_id < 0) {
4032 free_lag_id = i;
4033 }
4034 }
4035 if (free_lag_id < 0)
4036 return -EBUSY;
4037 *p_lag_id = free_lag_id;
4038 return 0;
4039 }
4040
4041 static bool
4042 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4043 struct net_device *lag_dev,
4044 struct netdev_lag_upper_info *lag_upper_info)
4045 {
4046 u16 lag_id;
4047
4048 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
4049 return false;
4050 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
4051 return false;
4052 return true;
4053 }
4054
4055 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4056 u16 lag_id, u8 *p_port_index)
4057 {
4058 u64 max_lag_members;
4059 int i;
4060
4061 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4062 MAX_LAG_MEMBERS);
4063 for (i = 0; i < max_lag_members; i++) {
4064 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4065 *p_port_index = i;
4066 return 0;
4067 }
4068 }
4069 return -EBUSY;
4070 }
4071
4072 static void
4073 mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4074 u16 lag_id)
4075 {
4076 struct mlxsw_sp_port *mlxsw_sp_vport;
4077 struct mlxsw_sp_fid *f;
4078
4079 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4080 if (WARN_ON(!mlxsw_sp_vport))
4081 return;
4082
4083 /* If vPort is assigned a RIF, then leave it since it's no
4084 * longer valid.
4085 */
4086 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4087 if (f)
4088 f->leave(mlxsw_sp_vport);
4089
4090 mlxsw_sp_vport->lag_id = lag_id;
4091 mlxsw_sp_vport->lagged = 1;
4092 }
4093
4094 static void
4095 mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4096 {
4097 struct mlxsw_sp_port *mlxsw_sp_vport;
4098 struct mlxsw_sp_fid *f;
4099
4100 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4101 if (WARN_ON(!mlxsw_sp_vport))
4102 return;
4103
4104 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4105 if (f)
4106 f->leave(mlxsw_sp_vport);
4107
4108 mlxsw_sp_vport->lagged = 0;
4109 }
4110
4111 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4112 struct net_device *lag_dev)
4113 {
4114 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4115 struct mlxsw_sp_upper *lag;
4116 u16 lag_id;
4117 u8 port_index;
4118 int err;
4119
4120 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4121 if (err)
4122 return err;
4123 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4124 if (!lag->ref_count) {
4125 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4126 if (err)
4127 return err;
4128 lag->dev = lag_dev;
4129 }
4130
4131 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4132 if (err)
4133 return err;
4134 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4135 if (err)
4136 goto err_col_port_add;
4137 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4138 if (err)
4139 goto err_col_port_enable;
4140
4141 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4142 mlxsw_sp_port->local_port);
4143 mlxsw_sp_port->lag_id = lag_id;
4144 mlxsw_sp_port->lagged = 1;
4145 lag->ref_count++;
4146
4147 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_id);
4148
4149 return 0;
4150
4151 err_col_port_enable:
4152 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4153 err_col_port_add:
4154 if (!lag->ref_count)
4155 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4156 return err;
4157 }
4158
4159 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4160 struct net_device *lag_dev)
4161 {
4162 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4163 u16 lag_id = mlxsw_sp_port->lag_id;
4164 struct mlxsw_sp_upper *lag;
4165
4166 if (!mlxsw_sp_port->lagged)
4167 return;
4168 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4169 WARN_ON(lag->ref_count == 0);
4170
4171 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4172 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4173
4174 if (mlxsw_sp_port->bridged) {
4175 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
4176 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
4177 }
4178
4179 if (lag->ref_count == 1)
4180 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
4181
4182 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4183 mlxsw_sp_port->local_port);
4184 mlxsw_sp_port->lagged = 0;
4185 lag->ref_count--;
4186
4187 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
4188 }
4189
4190 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4191 u16 lag_id)
4192 {
4193 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4194 char sldr_pl[MLXSW_REG_SLDR_LEN];
4195
4196 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4197 mlxsw_sp_port->local_port);
4198 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4199 }
4200
4201 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4202 u16 lag_id)
4203 {
4204 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4205 char sldr_pl[MLXSW_REG_SLDR_LEN];
4206
4207 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4208 mlxsw_sp_port->local_port);
4209 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4210 }
4211
4212 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4213 bool lag_tx_enabled)
4214 {
4215 if (lag_tx_enabled)
4216 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4217 mlxsw_sp_port->lag_id);
4218 else
4219 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4220 mlxsw_sp_port->lag_id);
4221 }
4222
4223 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4224 struct netdev_lag_lower_state_info *info)
4225 {
4226 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4227 }
4228
4229 static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
4230 struct net_device *vlan_dev)
4231 {
4232 struct mlxsw_sp_port *mlxsw_sp_vport;
4233 u16 vid = vlan_dev_vlan_id(vlan_dev);
4234
4235 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4236 if (WARN_ON(!mlxsw_sp_vport))
4237 return -EINVAL;
4238
4239 mlxsw_sp_vport->dev = vlan_dev;
4240
4241 return 0;
4242 }
4243
4244 static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
4245 struct net_device *vlan_dev)
4246 {
4247 struct mlxsw_sp_port *mlxsw_sp_vport;
4248 u16 vid = vlan_dev_vlan_id(vlan_dev);
4249
4250 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4251 if (WARN_ON(!mlxsw_sp_vport))
4252 return;
4253
4254 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
4255 }
4256
4257 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
4258 unsigned long event, void *ptr)
4259 {
4260 struct netdev_notifier_changeupper_info *info;
4261 struct mlxsw_sp_port *mlxsw_sp_port;
4262 struct net_device *upper_dev;
4263 struct mlxsw_sp *mlxsw_sp;
4264 int err = 0;
4265
4266 mlxsw_sp_port = netdev_priv(dev);
4267 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4268 info = ptr;
4269
4270 switch (event) {
4271 case NETDEV_PRECHANGEUPPER:
4272 upper_dev = info->upper_dev;
4273 if (!is_vlan_dev(upper_dev) &&
4274 !netif_is_lag_master(upper_dev) &&
4275 !netif_is_bridge_master(upper_dev))
4276 return -EINVAL;
4277 if (!info->linking)
4278 break;
4279 /* HW limitation forbids to put ports to multiple bridges. */
4280 if (netif_is_bridge_master(upper_dev) &&
4281 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
4282 return -EINVAL;
4283 if (netif_is_lag_master(upper_dev) &&
4284 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4285 info->upper_info))
4286 return -EINVAL;
4287 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4288 return -EINVAL;
4289 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4290 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4291 return -EINVAL;
4292 break;
4293 case NETDEV_CHANGEUPPER:
4294 upper_dev = info->upper_dev;
4295 if (is_vlan_dev(upper_dev)) {
4296 if (info->linking)
4297 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
4298 upper_dev);
4299 else
4300 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
4301 upper_dev);
4302 } else if (netif_is_bridge_master(upper_dev)) {
4303 if (info->linking)
4304 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4305 upper_dev);
4306 else
4307 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
4308 } else if (netif_is_lag_master(upper_dev)) {
4309 if (info->linking)
4310 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4311 upper_dev);
4312 else
4313 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4314 upper_dev);
4315 } else {
4316 err = -EINVAL;
4317 WARN_ON(1);
4318 }
4319 break;
4320 }
4321
4322 return err;
4323 }
4324
4325 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4326 unsigned long event, void *ptr)
4327 {
4328 struct netdev_notifier_changelowerstate_info *info;
4329 struct mlxsw_sp_port *mlxsw_sp_port;
4330 int err;
4331
4332 mlxsw_sp_port = netdev_priv(dev);
4333 info = ptr;
4334
4335 switch (event) {
4336 case NETDEV_CHANGELOWERSTATE:
4337 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4338 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4339 info->lower_state_info);
4340 if (err)
4341 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4342 }
4343 break;
4344 }
4345
4346 return 0;
4347 }
4348
4349 static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
4350 unsigned long event, void *ptr)
4351 {
4352 switch (event) {
4353 case NETDEV_PRECHANGEUPPER:
4354 case NETDEV_CHANGEUPPER:
4355 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
4356 case NETDEV_CHANGELOWERSTATE:
4357 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
4358 }
4359
4360 return 0;
4361 }
4362
4363 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4364 unsigned long event, void *ptr)
4365 {
4366 struct net_device *dev;
4367 struct list_head *iter;
4368 int ret;
4369
4370 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4371 if (mlxsw_sp_port_dev_check(dev)) {
4372 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4373 if (ret)
4374 return ret;
4375 }
4376 }
4377
4378 return 0;
4379 }
4380
4381 static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
4382 struct net_device *vlan_dev)
4383 {
4384 u16 fid = vlan_dev_vlan_id(vlan_dev);
4385 struct mlxsw_sp_fid *f;
4386
4387 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4388 if (!f) {
4389 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
4390 if (IS_ERR(f))
4391 return PTR_ERR(f);
4392 }
4393
4394 f->ref_count++;
4395
4396 return 0;
4397 }
4398
4399 static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
4400 struct net_device *vlan_dev)
4401 {
4402 u16 fid = vlan_dev_vlan_id(vlan_dev);
4403 struct mlxsw_sp_fid *f;
4404
4405 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4406 if (f && f->r)
4407 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
4408 if (f && --f->ref_count == 0)
4409 mlxsw_sp_fid_destroy(mlxsw_sp, f);
4410 }
4411
4412 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4413 unsigned long event, void *ptr)
4414 {
4415 struct netdev_notifier_changeupper_info *info;
4416 struct net_device *upper_dev;
4417 struct mlxsw_sp *mlxsw_sp;
4418 int err;
4419
4420 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4421 if (!mlxsw_sp)
4422 return 0;
4423 if (br_dev != mlxsw_sp->master_bridge.dev)
4424 return 0;
4425
4426 info = ptr;
4427
4428 switch (event) {
4429 case NETDEV_CHANGEUPPER:
4430 upper_dev = info->upper_dev;
4431 if (!is_vlan_dev(upper_dev))
4432 break;
4433 if (info->linking) {
4434 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
4435 upper_dev);
4436 if (err)
4437 return err;
4438 } else {
4439 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp, upper_dev);
4440 }
4441 break;
4442 }
4443
4444 return 0;
4445 }
4446
4447 static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
4448 {
4449 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
4450 MLXSW_SP_VFID_MAX);
4451 }
4452
4453 static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
4454 {
4455 char sfmr_pl[MLXSW_REG_SFMR_LEN];
4456
4457 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
4458 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
4459 }
4460
4461 static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
4462
4463 static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
4464 struct net_device *br_dev)
4465 {
4466 struct device *dev = mlxsw_sp->bus_info->dev;
4467 struct mlxsw_sp_fid *f;
4468 u16 vfid, fid;
4469 int err;
4470
4471 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
4472 if (vfid == MLXSW_SP_VFID_MAX) {
4473 dev_err(dev, "No available vFIDs\n");
4474 return ERR_PTR(-ERANGE);
4475 }
4476
4477 fid = mlxsw_sp_vfid_to_fid(vfid);
4478 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
4479 if (err) {
4480 dev_err(dev, "Failed to create FID=%d\n", fid);
4481 return ERR_PTR(err);
4482 }
4483
4484 f = kzalloc(sizeof(*f), GFP_KERNEL);
4485 if (!f)
4486 goto err_allocate_vfid;
4487
4488 f->leave = mlxsw_sp_vport_vfid_leave;
4489 f->fid = fid;
4490 f->dev = br_dev;
4491
4492 list_add(&f->list, &mlxsw_sp->vfids.list);
4493 set_bit(vfid, mlxsw_sp->vfids.mapped);
4494
4495 return f;
4496
4497 err_allocate_vfid:
4498 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
4499 return ERR_PTR(-ENOMEM);
4500 }
4501
4502 static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
4503 struct mlxsw_sp_fid *f)
4504 {
4505 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
4506 u16 fid = f->fid;
4507
4508 clear_bit(vfid, mlxsw_sp->vfids.mapped);
4509 list_del(&f->list);
4510
4511 if (f->r)
4512 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->r);
4513
4514 kfree(f);
4515
4516 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
4517 }
4518
4519 static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
4520 bool valid)
4521 {
4522 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
4523 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4524
4525 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
4526 vid);
4527 }
4528
4529 static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4530 struct net_device *br_dev)
4531 {
4532 struct mlxsw_sp_fid *f;
4533 int err;
4534
4535 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
4536 if (!f) {
4537 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
4538 if (IS_ERR(f))
4539 return PTR_ERR(f);
4540 }
4541
4542 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
4543 if (err)
4544 goto err_vport_flood_set;
4545
4546 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
4547 if (err)
4548 goto err_vport_fid_map;
4549
4550 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
4551 f->ref_count++;
4552
4553 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
4554
4555 return 0;
4556
4557 err_vport_fid_map:
4558 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4559 err_vport_flood_set:
4560 if (!f->ref_count)
4561 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
4562 return err;
4563 }
4564
4565 static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
4566 {
4567 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4568
4569 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
4570
4571 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
4572
4573 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4574
4575 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
4576
4577 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
4578 if (--f->ref_count == 0)
4579 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
4580 }
4581
4582 static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4583 struct net_device *br_dev)
4584 {
4585 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4586 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4587 struct net_device *dev = mlxsw_sp_vport->dev;
4588 int err;
4589
4590 if (f && !WARN_ON(!f->leave))
4591 f->leave(mlxsw_sp_vport);
4592
4593 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
4594 if (err) {
4595 netdev_err(dev, "Failed to join vFID\n");
4596 return err;
4597 }
4598
4599 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
4600 if (err) {
4601 netdev_err(dev, "Failed to enable learning\n");
4602 goto err_port_vid_learning_set;
4603 }
4604
4605 mlxsw_sp_vport->learning = 1;
4606 mlxsw_sp_vport->learning_sync = 1;
4607 mlxsw_sp_vport->uc_flood = 1;
4608 mlxsw_sp_vport->bridged = 1;
4609
4610 return 0;
4611
4612 err_port_vid_learning_set:
4613 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
4614 return err;
4615 }
4616
4617 static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
4618 {
4619 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4620
4621 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
4622
4623 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
4624
4625 mlxsw_sp_vport->learning = 0;
4626 mlxsw_sp_vport->learning_sync = 0;
4627 mlxsw_sp_vport->uc_flood = 0;
4628 mlxsw_sp_vport->bridged = 0;
4629 }
4630
4631 static bool
4632 mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
4633 const struct net_device *br_dev)
4634 {
4635 struct mlxsw_sp_port *mlxsw_sp_vport;
4636
4637 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
4638 vport.list) {
4639 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
4640
4641 if (dev && dev == br_dev)
4642 return false;
4643 }
4644
4645 return true;
4646 }
4647
4648 static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
4649 unsigned long event, void *ptr,
4650 u16 vid)
4651 {
4652 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4653 struct netdev_notifier_changeupper_info *info = ptr;
4654 struct mlxsw_sp_port *mlxsw_sp_vport;
4655 struct net_device *upper_dev;
4656 int err = 0;
4657
4658 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4659
4660 switch (event) {
4661 case NETDEV_PRECHANGEUPPER:
4662 upper_dev = info->upper_dev;
4663 if (!netif_is_bridge_master(upper_dev))
4664 return -EINVAL;
4665 if (!info->linking)
4666 break;
4667 /* We can't have multiple VLAN interfaces configured on
4668 * the same port and being members in the same bridge.
4669 */
4670 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
4671 upper_dev))
4672 return -EINVAL;
4673 break;
4674 case NETDEV_CHANGEUPPER:
4675 upper_dev = info->upper_dev;
4676 if (info->linking) {
4677 if (WARN_ON(!mlxsw_sp_vport))
4678 return -EINVAL;
4679 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
4680 upper_dev);
4681 } else {
4682 if (!mlxsw_sp_vport)
4683 return 0;
4684 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
4685 }
4686 }
4687
4688 return err;
4689 }
4690
4691 static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
4692 unsigned long event, void *ptr,
4693 u16 vid)
4694 {
4695 struct net_device *dev;
4696 struct list_head *iter;
4697 int ret;
4698
4699 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4700 if (mlxsw_sp_port_dev_check(dev)) {
4701 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
4702 vid);
4703 if (ret)
4704 return ret;
4705 }
4706 }
4707
4708 return 0;
4709 }
4710
4711 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4712 unsigned long event, void *ptr)
4713 {
4714 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4715 u16 vid = vlan_dev_vlan_id(vlan_dev);
4716
4717 if (mlxsw_sp_port_dev_check(real_dev))
4718 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
4719 vid);
4720 else if (netif_is_lag_master(real_dev))
4721 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
4722 vid);
4723
4724 return 0;
4725 }
4726
4727 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4728 unsigned long event, void *ptr)
4729 {
4730 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4731 int err = 0;
4732
4733 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4734 err = mlxsw_sp_netdevice_router_port_event(dev);
4735 else if (mlxsw_sp_port_dev_check(dev))
4736 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4737 else if (netif_is_lag_master(dev))
4738 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4739 else if (netif_is_bridge_master(dev))
4740 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
4741 else if (is_vlan_dev(dev))
4742 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
4743
4744 return notifier_from_errno(err);
4745 }
4746
4747 static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4748 .notifier_call = mlxsw_sp_netdevice_event,
4749 };
4750
4751 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4752 .notifier_call = mlxsw_sp_inetaddr_event,
4753 .priority = 10, /* Must be called before FIB notifier block */
4754 };
4755
4756 static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4757 .notifier_call = mlxsw_sp_router_netevent_event,
4758 };
4759
4760 static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4761 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4762 {0, },
4763 };
4764
4765 static struct pci_driver mlxsw_sp_pci_driver = {
4766 .name = mlxsw_sp_driver_name,
4767 .id_table = mlxsw_sp_pci_id_table,
4768 };
4769
4770 static int __init mlxsw_sp_module_init(void)
4771 {
4772 int err;
4773
4774 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4775 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4776 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4777
4778 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4779 if (err)
4780 goto err_core_driver_register;
4781
4782 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4783 if (err)
4784 goto err_pci_driver_register;
4785
4786 return 0;
4787
4788 err_pci_driver_register:
4789 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
4790 err_core_driver_register:
4791 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4792 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4793 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4794 return err;
4795 }
4796
4797 static void __exit mlxsw_sp_module_exit(void)
4798 {
4799 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
4800 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
4801 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4802 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4803 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4804 }
4805
4806 module_init(mlxsw_sp_module_init);
4807 module_exit(mlxsw_sp_module_exit);
4808
4809 MODULE_LICENSE("Dual BSD/GPL");
4810 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4811 MODULE_DESCRIPTION("Mellanox Spectrum driver");
4812 MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Linux with added FPC-III support