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powerpc/powernv: Report size of OPAL memcons log
[linux/fpc-iii.git] / drivers / net / ethernet / renesas / ravb_main.c
blob89ac1e3f617599238d35fa444ff66c20abd48dc6
1 /* Renesas Ethernet AVB device driver
2 *
3 * Copyright (C) 2014-2015 Renesas Electronics Corporation
4 * Copyright (C) 2015 Renesas Solutions Corp.
5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
6 *
7 * Based on the SuperH Ethernet driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License version 2,
11 * as published by the Free Software Foundation.
12 */
13
14 #include <linux/cache.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/etherdevice.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/spinlock.h>
34
35 #include <asm/div64.h>
36
37 #include "ravb.h"
38
39 #define RAVB_DEF_MSG_ENABLE \
40 (NETIF_MSG_LINK | \
41 NETIF_MSG_TIMER | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR)
44
45 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
46 "ch0", /* RAVB_BE */
47 "ch1", /* RAVB_NC */
48 };
49
50 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
51 "ch18", /* RAVB_BE */
52 "ch19", /* RAVB_NC */
53 };
54
55 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
56 u32 set)
57 {
58 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
59 }
60
61 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
62 {
63 int i;
64
65 for (i = 0; i < 10000; i++) {
66 if ((ravb_read(ndev, reg) & mask) == value)
67 return 0;
68 udelay(10);
69 }
70 return -ETIMEDOUT;
71 }
72
73 static int ravb_config(struct net_device *ndev)
74 {
75 int error;
76
77 /* Set config mode */
78 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
79 /* Check if the operating mode is changed to the config mode */
80 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
81 if (error)
82 netdev_err(ndev, "failed to switch device to config mode\n");
83
84 return error;
85 }
86
87 static void ravb_set_duplex(struct net_device *ndev)
88 {
89 struct ravb_private *priv = netdev_priv(ndev);
90
91 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0);
92 }
93
94 static void ravb_set_rate(struct net_device *ndev)
95 {
96 struct ravb_private *priv = netdev_priv(ndev);
97
98 switch (priv->speed) {
99 case 100: /* 100BASE */
100 ravb_write(ndev, GECMR_SPEED_100, GECMR);
101 break;
102 case 1000: /* 1000BASE */
103 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
104 break;
105 }
106 }
107
108 static void ravb_set_buffer_align(struct sk_buff *skb)
109 {
110 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
111
112 if (reserve)
113 skb_reserve(skb, RAVB_ALIGN - reserve);
114 }
115
116 /* Get MAC address from the MAC address registers
117 *
118 * Ethernet AVB device doesn't have ROM for MAC address.
119 * This function gets the MAC address that was used by a bootloader.
120 */
121 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
122 {
123 if (mac) {
124 ether_addr_copy(ndev->dev_addr, mac);
125 } else {
126 u32 mahr = ravb_read(ndev, MAHR);
127 u32 malr = ravb_read(ndev, MALR);
128
129 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
130 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
131 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
132 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
133 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
134 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
135 }
136 }
137
138 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
139 {
140 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
141 mdiobb);
142
143 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
144 }
145
146 /* MDC pin control */
147 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
148 {
149 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
150 }
151
152 /* Data I/O pin control */
153 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
154 {
155 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
156 }
157
158 /* Set data bit */
159 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
160 {
161 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
162 }
163
164 /* Get data bit */
165 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
166 {
167 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
168 mdiobb);
169
170 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
171 }
172
173 /* MDIO bus control struct */
174 static struct mdiobb_ops bb_ops = {
175 .owner = THIS_MODULE,
176 .set_mdc = ravb_set_mdc,
177 .set_mdio_dir = ravb_set_mdio_dir,
178 .set_mdio_data = ravb_set_mdio_data,
179 .get_mdio_data = ravb_get_mdio_data,
180 };
181
182 /* Free skb's and DMA buffers for Ethernet AVB */
183 static void ravb_ring_free(struct net_device *ndev, int q)
184 {
185 struct ravb_private *priv = netdev_priv(ndev);
186 int ring_size;
187 int i;
188
189 /* Free RX skb ringbuffer */
190 if (priv->rx_skb[q]) {
191 for (i = 0; i < priv->num_rx_ring[q]; i++)
192 dev_kfree_skb(priv->rx_skb[q][i]);
193 }
194 kfree(priv->rx_skb[q]);
195 priv->rx_skb[q] = NULL;
196
197 /* Free TX skb ringbuffer */
198 if (priv->tx_skb[q]) {
199 for (i = 0; i < priv->num_tx_ring[q]; i++)
200 dev_kfree_skb(priv->tx_skb[q][i]);
201 }
202 kfree(priv->tx_skb[q]);
203 priv->tx_skb[q] = NULL;
204
205 /* Free aligned TX buffers */
206 kfree(priv->tx_align[q]);
207 priv->tx_align[q] = NULL;
208
209 if (priv->rx_ring[q]) {
210 ring_size = sizeof(struct ravb_ex_rx_desc) *
211 (priv->num_rx_ring[q] + 1);
212 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
213 priv->rx_desc_dma[q]);
214 priv->rx_ring[q] = NULL;
215 }
216
217 if (priv->tx_ring[q]) {
218 ring_size = sizeof(struct ravb_tx_desc) *
219 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
220 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
221 priv->tx_desc_dma[q]);
222 priv->tx_ring[q] = NULL;
223 }
224 }
225
226 /* Format skb and descriptor buffer for Ethernet AVB */
227 static void ravb_ring_format(struct net_device *ndev, int q)
228 {
229 struct ravb_private *priv = netdev_priv(ndev);
230 struct ravb_ex_rx_desc *rx_desc;
231 struct ravb_tx_desc *tx_desc;
232 struct ravb_desc *desc;
233 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
234 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
235 NUM_TX_DESC;
236 dma_addr_t dma_addr;
237 int i;
238
239 priv->cur_rx[q] = 0;
240 priv->cur_tx[q] = 0;
241 priv->dirty_rx[q] = 0;
242 priv->dirty_tx[q] = 0;
243
244 memset(priv->rx_ring[q], 0, rx_ring_size);
245 /* Build RX ring buffer */
246 for (i = 0; i < priv->num_rx_ring[q]; i++) {
247 /* RX descriptor */
248 rx_desc = &priv->rx_ring[q][i];
249 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
250 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
251 PKT_BUF_SZ,
252 DMA_FROM_DEVICE);
253 /* We just set the data size to 0 for a failed mapping which
254 * should prevent DMA from happening...
255 */
256 if (dma_mapping_error(ndev->dev.parent, dma_addr))
257 rx_desc->ds_cc = cpu_to_le16(0);
258 rx_desc->dptr = cpu_to_le32(dma_addr);
259 rx_desc->die_dt = DT_FEMPTY;
260 }
261 rx_desc = &priv->rx_ring[q][i];
262 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
263 rx_desc->die_dt = DT_LINKFIX; /* type */
264
265 memset(priv->tx_ring[q], 0, tx_ring_size);
266 /* Build TX ring buffer */
267 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
268 i++, tx_desc++) {
269 tx_desc->die_dt = DT_EEMPTY;
270 tx_desc++;
271 tx_desc->die_dt = DT_EEMPTY;
272 }
273 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
274 tx_desc->die_dt = DT_LINKFIX; /* type */
275
276 /* RX descriptor base address for best effort */
277 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
278 desc->die_dt = DT_LINKFIX; /* type */
279 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
280
281 /* TX descriptor base address for best effort */
282 desc = &priv->desc_bat[q];
283 desc->die_dt = DT_LINKFIX; /* type */
284 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
285 }
286
287 /* Init skb and descriptor buffer for Ethernet AVB */
288 static int ravb_ring_init(struct net_device *ndev, int q)
289 {
290 struct ravb_private *priv = netdev_priv(ndev);
291 struct sk_buff *skb;
292 int ring_size;
293 int i;
294
295 /* Allocate RX and TX skb rings */
296 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
297 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
298 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
299 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
300 if (!priv->rx_skb[q] || !priv->tx_skb[q])
301 goto error;
302
303 for (i = 0; i < priv->num_rx_ring[q]; i++) {
304 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1);
305 if (!skb)
306 goto error;
307 ravb_set_buffer_align(skb);
308 priv->rx_skb[q][i] = skb;
309 }
310
311 /* Allocate rings for the aligned buffers */
312 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
313 DPTR_ALIGN - 1, GFP_KERNEL);
314 if (!priv->tx_align[q])
315 goto error;
316
317 /* Allocate all RX descriptors. */
318 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
319 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
320 &priv->rx_desc_dma[q],
321 GFP_KERNEL);
322 if (!priv->rx_ring[q])
323 goto error;
324
325 priv->dirty_rx[q] = 0;
326
327 /* Allocate all TX descriptors. */
328 ring_size = sizeof(struct ravb_tx_desc) *
329 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
330 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
331 &priv->tx_desc_dma[q],
332 GFP_KERNEL);
333 if (!priv->tx_ring[q])
334 goto error;
335
336 return 0;
337
338 error:
339 ravb_ring_free(ndev, q);
340
341 return -ENOMEM;
342 }
343
344 /* E-MAC init function */
345 static void ravb_emac_init(struct net_device *ndev)
346 {
347 struct ravb_private *priv = netdev_priv(ndev);
348
349 /* Receive frame limit set register */
350 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
351
352 /* PAUSE prohibition */
353 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |
354 ECMR_TE | ECMR_RE, ECMR);
355
356 ravb_set_rate(ndev);
357
358 /* Set MAC address */
359 ravb_write(ndev,
360 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
361 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
362 ravb_write(ndev,
363 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
364
365 /* E-MAC status register clear */
366 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
367
368 /* E-MAC interrupt enable register */
369 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
370 }
371
372 /* Device init function for Ethernet AVB */
373 static int ravb_dmac_init(struct net_device *ndev)
374 {
375 struct ravb_private *priv = netdev_priv(ndev);
376 int error;
377
378 /* Set CONFIG mode */
379 error = ravb_config(ndev);
380 if (error)
381 return error;
382
383 error = ravb_ring_init(ndev, RAVB_BE);
384 if (error)
385 return error;
386 error = ravb_ring_init(ndev, RAVB_NC);
387 if (error) {
388 ravb_ring_free(ndev, RAVB_BE);
389 return error;
390 }
391
392 /* Descriptor format */
393 ravb_ring_format(ndev, RAVB_BE);
394 ravb_ring_format(ndev, RAVB_NC);
395
396 #if defined(__LITTLE_ENDIAN)
397 ravb_modify(ndev, CCC, CCC_BOC, 0);
398 #else
399 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
400 #endif
401
402 /* Set AVB RX */
403 ravb_write(ndev,
404 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
405
406 /* Set FIFO size */
407 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
408
409 /* Timestamp enable */
410 ravb_write(ndev, TCCR_TFEN, TCCR);
411
412 /* Interrupt init: */
413 if (priv->chip_id == RCAR_GEN3) {
414 /* Clear DIL.DPLx */
415 ravb_write(ndev, 0, DIL);
416 /* Set queue specific interrupt */
417 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
418 }
419 /* Frame receive */
420 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
421 /* Disable FIFO full warning */
422 ravb_write(ndev, 0, RIC1);
423 /* Receive FIFO full error, descriptor empty */
424 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
425 /* Frame transmitted, timestamp FIFO updated */
426 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
427
428 /* Setting the control will start the AVB-DMAC process. */
429 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
430
431 return 0;
432 }
433
434 /* Free TX skb function for AVB-IP */
435 static int ravb_tx_free(struct net_device *ndev, int q)
436 {
437 struct ravb_private *priv = netdev_priv(ndev);
438 struct net_device_stats *stats = &priv->stats[q];
439 struct ravb_tx_desc *desc;
440 int free_num = 0;
441 int entry;
442 u32 size;
443
444 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
445 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
446 NUM_TX_DESC);
447 desc = &priv->tx_ring[q][entry];
448 if (desc->die_dt != DT_FEMPTY)
449 break;
450 /* Descriptor type must be checked before all other reads */
451 dma_rmb();
452 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
453 /* Free the original skb. */
454 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
455 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
456 size, DMA_TO_DEVICE);
457 /* Last packet descriptor? */
458 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
459 entry /= NUM_TX_DESC;
460 dev_kfree_skb_any(priv->tx_skb[q][entry]);
461 priv->tx_skb[q][entry] = NULL;
462 stats->tx_packets++;
463 }
464 free_num++;
465 }
466 stats->tx_bytes += size;
467 desc->die_dt = DT_EEMPTY;
468 }
469 return free_num;
470 }
471
472 static void ravb_get_tx_tstamp(struct net_device *ndev)
473 {
474 struct ravb_private *priv = netdev_priv(ndev);
475 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
476 struct skb_shared_hwtstamps shhwtstamps;
477 struct sk_buff *skb;
478 struct timespec64 ts;
479 u16 tag, tfa_tag;
480 int count;
481 u32 tfa2;
482
483 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
484 while (count--) {
485 tfa2 = ravb_read(ndev, TFA2);
486 tfa_tag = (tfa2 & TFA2_TST) >> 16;
487 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
488 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
489 ravb_read(ndev, TFA1);
490 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
491 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
492 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
493 list) {
494 skb = ts_skb->skb;
495 tag = ts_skb->tag;
496 list_del(&ts_skb->list);
497 kfree(ts_skb);
498 if (tag == tfa_tag) {
499 skb_tstamp_tx(skb, &shhwtstamps);
500 break;
501 }
502 }
503 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
504 }
505 }
506
507 /* Packet receive function for Ethernet AVB */
508 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
509 {
510 struct ravb_private *priv = netdev_priv(ndev);
511 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
512 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
513 priv->cur_rx[q];
514 struct net_device_stats *stats = &priv->stats[q];
515 struct ravb_ex_rx_desc *desc;
516 struct sk_buff *skb;
517 dma_addr_t dma_addr;
518 struct timespec64 ts;
519 u8 desc_status;
520 u16 pkt_len;
521 int limit;
522
523 boguscnt = min(boguscnt, *quota);
524 limit = boguscnt;
525 desc = &priv->rx_ring[q][entry];
526 while (desc->die_dt != DT_FEMPTY) {
527 /* Descriptor type must be checked before all other reads */
528 dma_rmb();
529 desc_status = desc->msc;
530 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
531
532 if (--boguscnt < 0)
533 break;
534
535 /* We use 0-byte descriptors to mark the DMA mapping errors */
536 if (!pkt_len)
537 continue;
538
539 if (desc_status & MSC_MC)
540 stats->multicast++;
541
542 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
543 MSC_CEEF)) {
544 stats->rx_errors++;
545 if (desc_status & MSC_CRC)
546 stats->rx_crc_errors++;
547 if (desc_status & MSC_RFE)
548 stats->rx_frame_errors++;
549 if (desc_status & (MSC_RTLF | MSC_RTSF))
550 stats->rx_length_errors++;
551 if (desc_status & MSC_CEEF)
552 stats->rx_missed_errors++;
553 } else {
554 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
555
556 skb = priv->rx_skb[q][entry];
557 priv->rx_skb[q][entry] = NULL;
558 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
559 PKT_BUF_SZ,
560 DMA_FROM_DEVICE);
561 get_ts &= (q == RAVB_NC) ?
562 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
563 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
564 if (get_ts) {
565 struct skb_shared_hwtstamps *shhwtstamps;
566
567 shhwtstamps = skb_hwtstamps(skb);
568 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
569 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
570 32) | le32_to_cpu(desc->ts_sl);
571 ts.tv_nsec = le32_to_cpu(desc->ts_n);
572 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
573 }
574 skb_put(skb, pkt_len);
575 skb->protocol = eth_type_trans(skb, ndev);
576 napi_gro_receive(&priv->napi[q], skb);
577 stats->rx_packets++;
578 stats->rx_bytes += pkt_len;
579 }
580
581 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
582 desc = &priv->rx_ring[q][entry];
583 }
584
585 /* Refill the RX ring buffers. */
586 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
587 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
588 desc = &priv->rx_ring[q][entry];
589 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ);
590
591 if (!priv->rx_skb[q][entry]) {
592 skb = netdev_alloc_skb(ndev,
593 PKT_BUF_SZ + RAVB_ALIGN - 1);
594 if (!skb)
595 break; /* Better luck next round. */
596 ravb_set_buffer_align(skb);
597 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
598 le16_to_cpu(desc->ds_cc),
599 DMA_FROM_DEVICE);
600 skb_checksum_none_assert(skb);
601 /* We just set the data size to 0 for a failed mapping
602 * which should prevent DMA from happening...
603 */
604 if (dma_mapping_error(ndev->dev.parent, dma_addr))
605 desc->ds_cc = cpu_to_le16(0);
606 desc->dptr = cpu_to_le32(dma_addr);
607 priv->rx_skb[q][entry] = skb;
608 }
609 /* Descriptor type must be set after all the above writes */
610 dma_wmb();
611 desc->die_dt = DT_FEMPTY;
612 }
613
614 *quota -= limit - (++boguscnt);
615
616 return boguscnt <= 0;
617 }
618
619 static void ravb_rcv_snd_disable(struct net_device *ndev)
620 {
621 /* Disable TX and RX */
622 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
623 }
624
625 static void ravb_rcv_snd_enable(struct net_device *ndev)
626 {
627 /* Enable TX and RX */
628 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
629 }
630
631 /* function for waiting dma process finished */
632 static int ravb_stop_dma(struct net_device *ndev)
633 {
634 int error;
635
636 /* Wait for stopping the hardware TX process */
637 error = ravb_wait(ndev, TCCR,
638 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
639 if (error)
640 return error;
641
642 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
643 0);
644 if (error)
645 return error;
646
647 /* Stop the E-MAC's RX/TX processes. */
648 ravb_rcv_snd_disable(ndev);
649
650 /* Wait for stopping the RX DMA process */
651 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
652 if (error)
653 return error;
654
655 /* Stop AVB-DMAC process */
656 return ravb_config(ndev);
657 }
658
659 /* E-MAC interrupt handler */
660 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
661 {
662 struct ravb_private *priv = netdev_priv(ndev);
663 u32 ecsr, psr;
664
665 ecsr = ravb_read(ndev, ECSR);
666 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
667 if (ecsr & ECSR_ICD)
668 ndev->stats.tx_carrier_errors++;
669 if (ecsr & ECSR_LCHNG) {
670 /* Link changed */
671 if (priv->no_avb_link)
672 return;
673 psr = ravb_read(ndev, PSR);
674 if (priv->avb_link_active_low)
675 psr ^= PSR_LMON;
676 if (!(psr & PSR_LMON)) {
677 /* DIsable RX and TX */
678 ravb_rcv_snd_disable(ndev);
679 } else {
680 /* Enable RX and TX */
681 ravb_rcv_snd_enable(ndev);
682 }
683 }
684 }
685
686 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
687 {
688 struct net_device *ndev = dev_id;
689 struct ravb_private *priv = netdev_priv(ndev);
690
691 spin_lock(&priv->lock);
692 ravb_emac_interrupt_unlocked(ndev);
693 mmiowb();
694 spin_unlock(&priv->lock);
695 return IRQ_HANDLED;
696 }
697
698 /* Error interrupt handler */
699 static void ravb_error_interrupt(struct net_device *ndev)
700 {
701 struct ravb_private *priv = netdev_priv(ndev);
702 u32 eis, ris2;
703
704 eis = ravb_read(ndev, EIS);
705 ravb_write(ndev, ~EIS_QFS, EIS);
706 if (eis & EIS_QFS) {
707 ris2 = ravb_read(ndev, RIS2);
708 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2);
709
710 /* Receive Descriptor Empty int */
711 if (ris2 & RIS2_QFF0)
712 priv->stats[RAVB_BE].rx_over_errors++;
713
714 /* Receive Descriptor Empty int */
715 if (ris2 & RIS2_QFF1)
716 priv->stats[RAVB_NC].rx_over_errors++;
717
718 /* Receive FIFO Overflow int */
719 if (ris2 & RIS2_RFFF)
720 priv->rx_fifo_errors++;
721 }
722 }
723
724 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
725 {
726 struct ravb_private *priv = netdev_priv(ndev);
727 u32 ris0 = ravb_read(ndev, RIS0);
728 u32 ric0 = ravb_read(ndev, RIC0);
729 u32 tis = ravb_read(ndev, TIS);
730 u32 tic = ravb_read(ndev, TIC);
731
732 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
733 if (napi_schedule_prep(&priv->napi[q])) {
734 /* Mask RX and TX interrupts */
735 if (priv->chip_id == RCAR_GEN2) {
736 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
737 ravb_write(ndev, tic & ~BIT(q), TIC);
738 } else {
739 ravb_write(ndev, BIT(q), RID0);
740 ravb_write(ndev, BIT(q), TID);
741 }
742 __napi_schedule(&priv->napi[q]);
743 } else {
744 netdev_warn(ndev,
745 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
746 ris0, ric0);
747 netdev_warn(ndev,
748 " tx status 0x%08x, tx mask 0x%08x.\n",
749 tis, tic);
750 }
751 return true;
752 }
753 return false;
754 }
755
756 static bool ravb_timestamp_interrupt(struct net_device *ndev)
757 {
758 u32 tis = ravb_read(ndev, TIS);
759
760 if (tis & TIS_TFUF) {
761 ravb_write(ndev, ~TIS_TFUF, TIS);
762 ravb_get_tx_tstamp(ndev);
763 return true;
764 }
765 return false;
766 }
767
768 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
769 {
770 struct net_device *ndev = dev_id;
771 struct ravb_private *priv = netdev_priv(ndev);
772 irqreturn_t result = IRQ_NONE;
773 u32 iss;
774
775 spin_lock(&priv->lock);
776 /* Get interrupt status */
777 iss = ravb_read(ndev, ISS);
778
779 /* Received and transmitted interrupts */
780 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
781 int q;
782
783 /* Timestamp updated */
784 if (ravb_timestamp_interrupt(ndev))
785 result = IRQ_HANDLED;
786
787 /* Network control and best effort queue RX/TX */
788 for (q = RAVB_NC; q >= RAVB_BE; q--) {
789 if (ravb_queue_interrupt(ndev, q))
790 result = IRQ_HANDLED;
791 }
792 }
793
794 /* E-MAC status summary */
795 if (iss & ISS_MS) {
796 ravb_emac_interrupt_unlocked(ndev);
797 result = IRQ_HANDLED;
798 }
799
800 /* Error status summary */
801 if (iss & ISS_ES) {
802 ravb_error_interrupt(ndev);
803 result = IRQ_HANDLED;
804 }
805
806 /* gPTP interrupt status summary */
807 if (iss & ISS_CGIS) {
808 ravb_ptp_interrupt(ndev);
809 result = IRQ_HANDLED;
810 }
811
812 mmiowb();
813 spin_unlock(&priv->lock);
814 return result;
815 }
816
817 /* Timestamp/Error/gPTP interrupt handler */
818 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
819 {
820 struct net_device *ndev = dev_id;
821 struct ravb_private *priv = netdev_priv(ndev);
822 irqreturn_t result = IRQ_NONE;
823 u32 iss;
824
825 spin_lock(&priv->lock);
826 /* Get interrupt status */
827 iss = ravb_read(ndev, ISS);
828
829 /* Timestamp updated */
830 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
831 result = IRQ_HANDLED;
832
833 /* Error status summary */
834 if (iss & ISS_ES) {
835 ravb_error_interrupt(ndev);
836 result = IRQ_HANDLED;
837 }
838
839 /* gPTP interrupt status summary */
840 if (iss & ISS_CGIS) {
841 ravb_ptp_interrupt(ndev);
842 result = IRQ_HANDLED;
843 }
844
845 mmiowb();
846 spin_unlock(&priv->lock);
847 return result;
848 }
849
850 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
851 {
852 struct net_device *ndev = dev_id;
853 struct ravb_private *priv = netdev_priv(ndev);
854 irqreturn_t result = IRQ_NONE;
855
856 spin_lock(&priv->lock);
857
858 /* Network control/Best effort queue RX/TX */
859 if (ravb_queue_interrupt(ndev, q))
860 result = IRQ_HANDLED;
861
862 mmiowb();
863 spin_unlock(&priv->lock);
864 return result;
865 }
866
867 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
868 {
869 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
870 }
871
872 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
873 {
874 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
875 }
876
877 static int ravb_poll(struct napi_struct *napi, int budget)
878 {
879 struct net_device *ndev = napi->dev;
880 struct ravb_private *priv = netdev_priv(ndev);
881 unsigned long flags;
882 int q = napi - priv->napi;
883 int mask = BIT(q);
884 int quota = budget;
885 u32 ris0, tis;
886
887 for (;;) {
888 tis = ravb_read(ndev, TIS);
889 ris0 = ravb_read(ndev, RIS0);
890 if (!((ris0 & mask) || (tis & mask)))
891 break;
892
893 /* Processing RX Descriptor Ring */
894 if (ris0 & mask) {
895 /* Clear RX interrupt */
896 ravb_write(ndev, ~mask, RIS0);
897 if (ravb_rx(ndev, &quota, q))
898 goto out;
899 }
900 /* Processing TX Descriptor Ring */
901 if (tis & mask) {
902 spin_lock_irqsave(&priv->lock, flags);
903 /* Clear TX interrupt */
904 ravb_write(ndev, ~mask, TIS);
905 ravb_tx_free(ndev, q);
906 netif_wake_subqueue(ndev, q);
907 mmiowb();
908 spin_unlock_irqrestore(&priv->lock, flags);
909 }
910 }
911
912 napi_complete(napi);
913
914 /* Re-enable RX/TX interrupts */
915 spin_lock_irqsave(&priv->lock, flags);
916 if (priv->chip_id == RCAR_GEN2) {
917 ravb_modify(ndev, RIC0, mask, mask);
918 ravb_modify(ndev, TIC, mask, mask);
919 } else {
920 ravb_write(ndev, mask, RIE0);
921 ravb_write(ndev, mask, TIE);
922 }
923 mmiowb();
924 spin_unlock_irqrestore(&priv->lock, flags);
925
926 /* Receive error message handling */
927 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
928 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
929 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
930 ndev->stats.rx_over_errors = priv->rx_over_errors;
931 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
932 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
933 out:
934 return budget - quota;
935 }
936
937 /* PHY state control function */
938 static void ravb_adjust_link(struct net_device *ndev)
939 {
940 struct ravb_private *priv = netdev_priv(ndev);
941 struct phy_device *phydev = ndev->phydev;
942 bool new_state = false;
943
944 if (phydev->link) {
945 if (phydev->duplex != priv->duplex) {
946 new_state = true;
947 priv->duplex = phydev->duplex;
948 ravb_set_duplex(ndev);
949 }
950
951 if (phydev->speed != priv->speed) {
952 new_state = true;
953 priv->speed = phydev->speed;
954 ravb_set_rate(ndev);
955 }
956 if (!priv->link) {
957 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
958 new_state = true;
959 priv->link = phydev->link;
960 if (priv->no_avb_link)
961 ravb_rcv_snd_enable(ndev);
962 }
963 } else if (priv->link) {
964 new_state = true;
965 priv->link = 0;
966 priv->speed = 0;
967 priv->duplex = -1;
968 if (priv->no_avb_link)
969 ravb_rcv_snd_disable(ndev);
970 }
971
972 if (new_state && netif_msg_link(priv))
973 phy_print_status(phydev);
974 }
975
976 /* PHY init function */
977 static int ravb_phy_init(struct net_device *ndev)
978 {
979 struct device_node *np = ndev->dev.parent->of_node;
980 struct ravb_private *priv = netdev_priv(ndev);
981 struct phy_device *phydev;
982 struct device_node *pn;
983 int err;
984
985 priv->link = 0;
986 priv->speed = 0;
987 priv->duplex = -1;
988
989 /* Try connecting to PHY */
990 pn = of_parse_phandle(np, "phy-handle", 0);
991 if (!pn) {
992 /* In the case of a fixed PHY, the DT node associated
993 * to the PHY is the Ethernet MAC DT node.
994 */
995 if (of_phy_is_fixed_link(np)) {
996 err = of_phy_register_fixed_link(np);
997 if (err)
998 return err;
999 }
1000 pn = of_node_get(np);
1001 }
1002 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1003 priv->phy_interface);
1004 of_node_put(pn);
1005 if (!phydev) {
1006 netdev_err(ndev, "failed to connect PHY\n");
1007 err = -ENOENT;
1008 goto err_deregister_fixed_link;
1009 }
1010
1011 /* This driver only support 10/100Mbit speeds on Gen3
1012 * at this time.
1013 */
1014 if (priv->chip_id == RCAR_GEN3) {
1015 err = phy_set_max_speed(phydev, SPEED_100);
1016 if (err) {
1017 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1018 goto err_phy_disconnect;
1019 }
1020
1021 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1022 }
1023
1024 /* 10BASE is not supported */
1025 phydev->supported &= ~PHY_10BT_FEATURES;
1026
1027 phy_attached_info(phydev);
1028
1029 return 0;
1030
1031 err_phy_disconnect:
1032 phy_disconnect(phydev);
1033 err_deregister_fixed_link:
1034 if (of_phy_is_fixed_link(np))
1035 of_phy_deregister_fixed_link(np);
1036
1037 return err;
1038 }
1039
1040 /* PHY control start function */
1041 static int ravb_phy_start(struct net_device *ndev)
1042 {
1043 int error;
1044
1045 error = ravb_phy_init(ndev);
1046 if (error)
1047 return error;
1048
1049 phy_start(ndev->phydev);
1050
1051 return 0;
1052 }
1053
1054 static int ravb_get_link_ksettings(struct net_device *ndev,
1055 struct ethtool_link_ksettings *cmd)
1056 {
1057 struct ravb_private *priv = netdev_priv(ndev);
1058 int error = -ENODEV;
1059 unsigned long flags;
1060
1061 if (ndev->phydev) {
1062 spin_lock_irqsave(&priv->lock, flags);
1063 error = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1064 spin_unlock_irqrestore(&priv->lock, flags);
1065 }
1066
1067 return error;
1068 }
1069
1070 static int ravb_set_link_ksettings(struct net_device *ndev,
1071 const struct ethtool_link_ksettings *cmd)
1072 {
1073 struct ravb_private *priv = netdev_priv(ndev);
1074 unsigned long flags;
1075 int error;
1076
1077 if (!ndev->phydev)
1078 return -ENODEV;
1079
1080 spin_lock_irqsave(&priv->lock, flags);
1081
1082 /* Disable TX and RX */
1083 ravb_rcv_snd_disable(ndev);
1084
1085 error = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1086 if (error)
1087 goto error_exit;
1088
1089 if (cmd->base.duplex == DUPLEX_FULL)
1090 priv->duplex = 1;
1091 else
1092 priv->duplex = 0;
1093
1094 ravb_set_duplex(ndev);
1095
1096 error_exit:
1097 mdelay(1);
1098
1099 /* Enable TX and RX */
1100 ravb_rcv_snd_enable(ndev);
1101
1102 mmiowb();
1103 spin_unlock_irqrestore(&priv->lock, flags);
1104
1105 return error;
1106 }
1107
1108 static int ravb_nway_reset(struct net_device *ndev)
1109 {
1110 struct ravb_private *priv = netdev_priv(ndev);
1111 int error = -ENODEV;
1112 unsigned long flags;
1113
1114 if (ndev->phydev) {
1115 spin_lock_irqsave(&priv->lock, flags);
1116 error = phy_start_aneg(ndev->phydev);
1117 spin_unlock_irqrestore(&priv->lock, flags);
1118 }
1119
1120 return error;
1121 }
1122
1123 static u32 ravb_get_msglevel(struct net_device *ndev)
1124 {
1125 struct ravb_private *priv = netdev_priv(ndev);
1126
1127 return priv->msg_enable;
1128 }
1129
1130 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1131 {
1132 struct ravb_private *priv = netdev_priv(ndev);
1133
1134 priv->msg_enable = value;
1135 }
1136
1137 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1138 "rx_queue_0_current",
1139 "tx_queue_0_current",
1140 "rx_queue_0_dirty",
1141 "tx_queue_0_dirty",
1142 "rx_queue_0_packets",
1143 "tx_queue_0_packets",
1144 "rx_queue_0_bytes",
1145 "tx_queue_0_bytes",
1146 "rx_queue_0_mcast_packets",
1147 "rx_queue_0_errors",
1148 "rx_queue_0_crc_errors",
1149 "rx_queue_0_frame_errors",
1150 "rx_queue_0_length_errors",
1151 "rx_queue_0_missed_errors",
1152 "rx_queue_0_over_errors",
1153
1154 "rx_queue_1_current",
1155 "tx_queue_1_current",
1156 "rx_queue_1_dirty",
1157 "tx_queue_1_dirty",
1158 "rx_queue_1_packets",
1159 "tx_queue_1_packets",
1160 "rx_queue_1_bytes",
1161 "tx_queue_1_bytes",
1162 "rx_queue_1_mcast_packets",
1163 "rx_queue_1_errors",
1164 "rx_queue_1_crc_errors",
1165 "rx_queue_1_frame_errors",
1166 "rx_queue_1_length_errors",
1167 "rx_queue_1_missed_errors",
1168 "rx_queue_1_over_errors",
1169 };
1170
1171 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1172
1173 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1174 {
1175 switch (sset) {
1176 case ETH_SS_STATS:
1177 return RAVB_STATS_LEN;
1178 default:
1179 return -EOPNOTSUPP;
1180 }
1181 }
1182
1183 static void ravb_get_ethtool_stats(struct net_device *ndev,
1184 struct ethtool_stats *stats, u64 *data)
1185 {
1186 struct ravb_private *priv = netdev_priv(ndev);
1187 int i = 0;
1188 int q;
1189
1190 /* Device-specific stats */
1191 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1192 struct net_device_stats *stats = &priv->stats[q];
1193
1194 data[i++] = priv->cur_rx[q];
1195 data[i++] = priv->cur_tx[q];
1196 data[i++] = priv->dirty_rx[q];
1197 data[i++] = priv->dirty_tx[q];
1198 data[i++] = stats->rx_packets;
1199 data[i++] = stats->tx_packets;
1200 data[i++] = stats->rx_bytes;
1201 data[i++] = stats->tx_bytes;
1202 data[i++] = stats->multicast;
1203 data[i++] = stats->rx_errors;
1204 data[i++] = stats->rx_crc_errors;
1205 data[i++] = stats->rx_frame_errors;
1206 data[i++] = stats->rx_length_errors;
1207 data[i++] = stats->rx_missed_errors;
1208 data[i++] = stats->rx_over_errors;
1209 }
1210 }
1211
1212 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1213 {
1214 switch (stringset) {
1215 case ETH_SS_STATS:
1216 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1217 break;
1218 }
1219 }
1220
1221 static void ravb_get_ringparam(struct net_device *ndev,
1222 struct ethtool_ringparam *ring)
1223 {
1224 struct ravb_private *priv = netdev_priv(ndev);
1225
1226 ring->rx_max_pending = BE_RX_RING_MAX;
1227 ring->tx_max_pending = BE_TX_RING_MAX;
1228 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1229 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1230 }
1231
1232 static int ravb_set_ringparam(struct net_device *ndev,
1233 struct ethtool_ringparam *ring)
1234 {
1235 struct ravb_private *priv = netdev_priv(ndev);
1236 int error;
1237
1238 if (ring->tx_pending > BE_TX_RING_MAX ||
1239 ring->rx_pending > BE_RX_RING_MAX ||
1240 ring->tx_pending < BE_TX_RING_MIN ||
1241 ring->rx_pending < BE_RX_RING_MIN)
1242 return -EINVAL;
1243 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1244 return -EINVAL;
1245
1246 if (netif_running(ndev)) {
1247 netif_device_detach(ndev);
1248 /* Stop PTP Clock driver */
1249 if (priv->chip_id == RCAR_GEN2)
1250 ravb_ptp_stop(ndev);
1251 /* Wait for DMA stopping */
1252 error = ravb_stop_dma(ndev);
1253 if (error) {
1254 netdev_err(ndev,
1255 "cannot set ringparam! Any AVB processes are still running?\n");
1256 return error;
1257 }
1258 synchronize_irq(ndev->irq);
1259
1260 /* Free all the skb's in the RX queue and the DMA buffers. */
1261 ravb_ring_free(ndev, RAVB_BE);
1262 ravb_ring_free(ndev, RAVB_NC);
1263 }
1264
1265 /* Set new parameters */
1266 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1267 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1268
1269 if (netif_running(ndev)) {
1270 error = ravb_dmac_init(ndev);
1271 if (error) {
1272 netdev_err(ndev,
1273 "%s: ravb_dmac_init() failed, error %d\n",
1274 __func__, error);
1275 return error;
1276 }
1277
1278 ravb_emac_init(ndev);
1279
1280 /* Initialise PTP Clock driver */
1281 if (priv->chip_id == RCAR_GEN2)
1282 ravb_ptp_init(ndev, priv->pdev);
1283
1284 netif_device_attach(ndev);
1285 }
1286
1287 return 0;
1288 }
1289
1290 static int ravb_get_ts_info(struct net_device *ndev,
1291 struct ethtool_ts_info *info)
1292 {
1293 struct ravb_private *priv = netdev_priv(ndev);
1294
1295 info->so_timestamping =
1296 SOF_TIMESTAMPING_TX_SOFTWARE |
1297 SOF_TIMESTAMPING_RX_SOFTWARE |
1298 SOF_TIMESTAMPING_SOFTWARE |
1299 SOF_TIMESTAMPING_TX_HARDWARE |
1300 SOF_TIMESTAMPING_RX_HARDWARE |
1301 SOF_TIMESTAMPING_RAW_HARDWARE;
1302 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1303 info->rx_filters =
1304 (1 << HWTSTAMP_FILTER_NONE) |
1305 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1306 (1 << HWTSTAMP_FILTER_ALL);
1307 info->phc_index = ptp_clock_index(priv->ptp.clock);
1308
1309 return 0;
1310 }
1311
1312 static const struct ethtool_ops ravb_ethtool_ops = {
1313 .nway_reset = ravb_nway_reset,
1314 .get_msglevel = ravb_get_msglevel,
1315 .set_msglevel = ravb_set_msglevel,
1316 .get_link = ethtool_op_get_link,
1317 .get_strings = ravb_get_strings,
1318 .get_ethtool_stats = ravb_get_ethtool_stats,
1319 .get_sset_count = ravb_get_sset_count,
1320 .get_ringparam = ravb_get_ringparam,
1321 .set_ringparam = ravb_set_ringparam,
1322 .get_ts_info = ravb_get_ts_info,
1323 .get_link_ksettings = ravb_get_link_ksettings,
1324 .set_link_ksettings = ravb_set_link_ksettings,
1325 };
1326
1327 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1328 struct net_device *ndev, struct device *dev,
1329 const char *ch)
1330 {
1331 char *name;
1332 int error;
1333
1334 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1335 if (!name)
1336 return -ENOMEM;
1337 error = request_irq(irq, handler, 0, name, ndev);
1338 if (error)
1339 netdev_err(ndev, "cannot request IRQ %s\n", name);
1340
1341 return error;
1342 }
1343
1344 /* Network device open function for Ethernet AVB */
1345 static int ravb_open(struct net_device *ndev)
1346 {
1347 struct ravb_private *priv = netdev_priv(ndev);
1348 struct platform_device *pdev = priv->pdev;
1349 struct device *dev = &pdev->dev;
1350 int error;
1351
1352 napi_enable(&priv->napi[RAVB_BE]);
1353 napi_enable(&priv->napi[RAVB_NC]);
1354
1355 if (priv->chip_id == RCAR_GEN2) {
1356 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1357 ndev->name, ndev);
1358 if (error) {
1359 netdev_err(ndev, "cannot request IRQ\n");
1360 goto out_napi_off;
1361 }
1362 } else {
1363 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1364 dev, "ch22:multi");
1365 if (error)
1366 goto out_napi_off;
1367 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1368 dev, "ch24:emac");
1369 if (error)
1370 goto out_free_irq;
1371 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1372 ndev, dev, "ch0:rx_be");
1373 if (error)
1374 goto out_free_irq_emac;
1375 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1376 ndev, dev, "ch18:tx_be");
1377 if (error)
1378 goto out_free_irq_be_rx;
1379 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1380 ndev, dev, "ch1:rx_nc");
1381 if (error)
1382 goto out_free_irq_be_tx;
1383 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1384 ndev, dev, "ch19:tx_nc");
1385 if (error)
1386 goto out_free_irq_nc_rx;
1387 }
1388
1389 /* Device init */
1390 error = ravb_dmac_init(ndev);
1391 if (error)
1392 goto out_free_irq_nc_tx;
1393 ravb_emac_init(ndev);
1394
1395 /* Initialise PTP Clock driver */
1396 if (priv->chip_id == RCAR_GEN2)
1397 ravb_ptp_init(ndev, priv->pdev);
1398
1399 netif_tx_start_all_queues(ndev);
1400
1401 /* PHY control start */
1402 error = ravb_phy_start(ndev);
1403 if (error)
1404 goto out_ptp_stop;
1405
1406 return 0;
1407
1408 out_ptp_stop:
1409 /* Stop PTP Clock driver */
1410 if (priv->chip_id == RCAR_GEN2)
1411 ravb_ptp_stop(ndev);
1412 out_free_irq_nc_tx:
1413 if (priv->chip_id == RCAR_GEN2)
1414 goto out_free_irq;
1415 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1416 out_free_irq_nc_rx:
1417 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1418 out_free_irq_be_tx:
1419 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1420 out_free_irq_be_rx:
1421 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1422 out_free_irq_emac:
1423 free_irq(priv->emac_irq, ndev);
1424 out_free_irq:
1425 free_irq(ndev->irq, ndev);
1426 out_napi_off:
1427 napi_disable(&priv->napi[RAVB_NC]);
1428 napi_disable(&priv->napi[RAVB_BE]);
1429 return error;
1430 }
1431
1432 /* Timeout function for Ethernet AVB */
1433 static void ravb_tx_timeout(struct net_device *ndev)
1434 {
1435 struct ravb_private *priv = netdev_priv(ndev);
1436
1437 netif_err(priv, tx_err, ndev,
1438 "transmit timed out, status %08x, resetting...\n",
1439 ravb_read(ndev, ISS));
1440
1441 /* tx_errors count up */
1442 ndev->stats.tx_errors++;
1443
1444 schedule_work(&priv->work);
1445 }
1446
1447 static void ravb_tx_timeout_work(struct work_struct *work)
1448 {
1449 struct ravb_private *priv = container_of(work, struct ravb_private,
1450 work);
1451 struct net_device *ndev = priv->ndev;
1452
1453 netif_tx_stop_all_queues(ndev);
1454
1455 /* Stop PTP Clock driver */
1456 if (priv->chip_id == RCAR_GEN2)
1457 ravb_ptp_stop(ndev);
1458
1459 /* Wait for DMA stopping */
1460 ravb_stop_dma(ndev);
1461
1462 ravb_ring_free(ndev, RAVB_BE);
1463 ravb_ring_free(ndev, RAVB_NC);
1464
1465 /* Device init */
1466 ravb_dmac_init(ndev);
1467 ravb_emac_init(ndev);
1468
1469 /* Initialise PTP Clock driver */
1470 if (priv->chip_id == RCAR_GEN2)
1471 ravb_ptp_init(ndev, priv->pdev);
1472
1473 netif_tx_start_all_queues(ndev);
1474 }
1475
1476 /* Packet transmit function for Ethernet AVB */
1477 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1478 {
1479 struct ravb_private *priv = netdev_priv(ndev);
1480 u16 q = skb_get_queue_mapping(skb);
1481 struct ravb_tstamp_skb *ts_skb;
1482 struct ravb_tx_desc *desc;
1483 unsigned long flags;
1484 u32 dma_addr;
1485 void *buffer;
1486 u32 entry;
1487 u32 len;
1488
1489 spin_lock_irqsave(&priv->lock, flags);
1490 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1491 NUM_TX_DESC) {
1492 netif_err(priv, tx_queued, ndev,
1493 "still transmitting with the full ring!\n");
1494 netif_stop_subqueue(ndev, q);
1495 spin_unlock_irqrestore(&priv->lock, flags);
1496 return NETDEV_TX_BUSY;
1497 }
1498 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1499 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1500
1501 if (skb_put_padto(skb, ETH_ZLEN))
1502 goto drop;
1503
1504 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1505 entry / NUM_TX_DESC * DPTR_ALIGN;
1506 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1507 /* Zero length DMA descriptors are problematic as they seem to
1508 * terminate DMA transfers. Avoid them by simply using a length of
1509 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1510 *
1511 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1512 * data by the call to skb_put_padto() above this is safe with
1513 * respect to both the length of the first DMA descriptor (len)
1514 * overflowing the available data and the length of the second DMA
1515 * descriptor (skb->len - len) being negative.
1516 */
1517 if (len == 0)
1518 len = DPTR_ALIGN;
1519
1520 memcpy(buffer, skb->data, len);
1521 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1522 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1523 goto drop;
1524
1525 desc = &priv->tx_ring[q][entry];
1526 desc->ds_tagl = cpu_to_le16(len);
1527 desc->dptr = cpu_to_le32(dma_addr);
1528
1529 buffer = skb->data + len;
1530 len = skb->len - len;
1531 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1532 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1533 goto unmap;
1534
1535 desc++;
1536 desc->ds_tagl = cpu_to_le16(len);
1537 desc->dptr = cpu_to_le32(dma_addr);
1538
1539 /* TX timestamp required */
1540 if (q == RAVB_NC) {
1541 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1542 if (!ts_skb) {
1543 desc--;
1544 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1545 DMA_TO_DEVICE);
1546 goto unmap;
1547 }
1548 ts_skb->skb = skb;
1549 ts_skb->tag = priv->ts_skb_tag++;
1550 priv->ts_skb_tag &= 0x3ff;
1551 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1552
1553 /* TAG and timestamp required flag */
1554 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1555 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1556 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12);
1557 }
1558
1559 skb_tx_timestamp(skb);
1560 /* Descriptor type must be set after all the above writes */
1561 dma_wmb();
1562 desc->die_dt = DT_FEND;
1563 desc--;
1564 desc->die_dt = DT_FSTART;
1565
1566 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1567
1568 priv->cur_tx[q] += NUM_TX_DESC;
1569 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1570 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q))
1571 netif_stop_subqueue(ndev, q);
1572
1573 exit:
1574 mmiowb();
1575 spin_unlock_irqrestore(&priv->lock, flags);
1576 return NETDEV_TX_OK;
1577
1578 unmap:
1579 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1580 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1581 drop:
1582 dev_kfree_skb_any(skb);
1583 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1584 goto exit;
1585 }
1586
1587 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1588 void *accel_priv, select_queue_fallback_t fallback)
1589 {
1590 /* If skb needs TX timestamp, it is handled in network control queue */
1591 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1592 RAVB_BE;
1593
1594 }
1595
1596 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1597 {
1598 struct ravb_private *priv = netdev_priv(ndev);
1599 struct net_device_stats *nstats, *stats0, *stats1;
1600
1601 nstats = &ndev->stats;
1602 stats0 = &priv->stats[RAVB_BE];
1603 stats1 = &priv->stats[RAVB_NC];
1604
1605 nstats->tx_dropped += ravb_read(ndev, TROCR);
1606 ravb_write(ndev, 0, TROCR); /* (write clear) */
1607 nstats->collisions += ravb_read(ndev, CDCR);
1608 ravb_write(ndev, 0, CDCR); /* (write clear) */
1609 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1610 ravb_write(ndev, 0, LCCR); /* (write clear) */
1611
1612 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1613 ravb_write(ndev, 0, CERCR); /* (write clear) */
1614 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1615 ravb_write(ndev, 0, CEECR); /* (write clear) */
1616
1617 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1618 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1619 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1620 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1621 nstats->multicast = stats0->multicast + stats1->multicast;
1622 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1623 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1624 nstats->rx_frame_errors =
1625 stats0->rx_frame_errors + stats1->rx_frame_errors;
1626 nstats->rx_length_errors =
1627 stats0->rx_length_errors + stats1->rx_length_errors;
1628 nstats->rx_missed_errors =
1629 stats0->rx_missed_errors + stats1->rx_missed_errors;
1630 nstats->rx_over_errors =
1631 stats0->rx_over_errors + stats1->rx_over_errors;
1632
1633 return nstats;
1634 }
1635
1636 /* Update promiscuous bit */
1637 static void ravb_set_rx_mode(struct net_device *ndev)
1638 {
1639 struct ravb_private *priv = netdev_priv(ndev);
1640 unsigned long flags;
1641
1642 spin_lock_irqsave(&priv->lock, flags);
1643 ravb_modify(ndev, ECMR, ECMR_PRM,
1644 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1645 mmiowb();
1646 spin_unlock_irqrestore(&priv->lock, flags);
1647 }
1648
1649 /* Device close function for Ethernet AVB */
1650 static int ravb_close(struct net_device *ndev)
1651 {
1652 struct device_node *np = ndev->dev.parent->of_node;
1653 struct ravb_private *priv = netdev_priv(ndev);
1654 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1655
1656 netif_tx_stop_all_queues(ndev);
1657
1658 /* Disable interrupts by clearing the interrupt masks. */
1659 ravb_write(ndev, 0, RIC0);
1660 ravb_write(ndev, 0, RIC2);
1661 ravb_write(ndev, 0, TIC);
1662
1663 /* Stop PTP Clock driver */
1664 if (priv->chip_id == RCAR_GEN2)
1665 ravb_ptp_stop(ndev);
1666
1667 /* Set the config mode to stop the AVB-DMAC's processes */
1668 if (ravb_stop_dma(ndev) < 0)
1669 netdev_err(ndev,
1670 "device will be stopped after h/w processes are done.\n");
1671
1672 /* Clear the timestamp list */
1673 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1674 list_del(&ts_skb->list);
1675 kfree(ts_skb);
1676 }
1677
1678 /* PHY disconnect */
1679 if (ndev->phydev) {
1680 phy_stop(ndev->phydev);
1681 phy_disconnect(ndev->phydev);
1682 if (of_phy_is_fixed_link(np))
1683 of_phy_deregister_fixed_link(np);
1684 }
1685
1686 if (priv->chip_id != RCAR_GEN2) {
1687 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1688 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1689 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1690 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1691 free_irq(priv->emac_irq, ndev);
1692 }
1693 free_irq(ndev->irq, ndev);
1694
1695 napi_disable(&priv->napi[RAVB_NC]);
1696 napi_disable(&priv->napi[RAVB_BE]);
1697
1698 /* Free all the skb's in the RX queue and the DMA buffers. */
1699 ravb_ring_free(ndev, RAVB_BE);
1700 ravb_ring_free(ndev, RAVB_NC);
1701
1702 return 0;
1703 }
1704
1705 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1706 {
1707 struct ravb_private *priv = netdev_priv(ndev);
1708 struct hwtstamp_config config;
1709
1710 config.flags = 0;
1711 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1712 HWTSTAMP_TX_OFF;
1713 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT)
1714 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1715 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL)
1716 config.rx_filter = HWTSTAMP_FILTER_ALL;
1717 else
1718 config.rx_filter = HWTSTAMP_FILTER_NONE;
1719
1720 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1721 -EFAULT : 0;
1722 }
1723
1724 /* Control hardware time stamping */
1725 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1726 {
1727 struct ravb_private *priv = netdev_priv(ndev);
1728 struct hwtstamp_config config;
1729 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1730 u32 tstamp_tx_ctrl;
1731
1732 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1733 return -EFAULT;
1734
1735 /* Reserved for future extensions */
1736 if (config.flags)
1737 return -EINVAL;
1738
1739 switch (config.tx_type) {
1740 case HWTSTAMP_TX_OFF:
1741 tstamp_tx_ctrl = 0;
1742 break;
1743 case HWTSTAMP_TX_ON:
1744 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1745 break;
1746 default:
1747 return -ERANGE;
1748 }
1749
1750 switch (config.rx_filter) {
1751 case HWTSTAMP_FILTER_NONE:
1752 tstamp_rx_ctrl = 0;
1753 break;
1754 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1755 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1756 break;
1757 default:
1758 config.rx_filter = HWTSTAMP_FILTER_ALL;
1759 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1760 }
1761
1762 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1763 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1764
1765 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1766 -EFAULT : 0;
1767 }
1768
1769 /* ioctl to device function */
1770 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1771 {
1772 struct phy_device *phydev = ndev->phydev;
1773
1774 if (!netif_running(ndev))
1775 return -EINVAL;
1776
1777 if (!phydev)
1778 return -ENODEV;
1779
1780 switch (cmd) {
1781 case SIOCGHWTSTAMP:
1782 return ravb_hwtstamp_get(ndev, req);
1783 case SIOCSHWTSTAMP:
1784 return ravb_hwtstamp_set(ndev, req);
1785 }
1786
1787 return phy_mii_ioctl(phydev, req, cmd);
1788 }
1789
1790 static const struct net_device_ops ravb_netdev_ops = {
1791 .ndo_open = ravb_open,
1792 .ndo_stop = ravb_close,
1793 .ndo_start_xmit = ravb_start_xmit,
1794 .ndo_select_queue = ravb_select_queue,
1795 .ndo_get_stats = ravb_get_stats,
1796 .ndo_set_rx_mode = ravb_set_rx_mode,
1797 .ndo_tx_timeout = ravb_tx_timeout,
1798 .ndo_do_ioctl = ravb_do_ioctl,
1799 .ndo_validate_addr = eth_validate_addr,
1800 .ndo_set_mac_address = eth_mac_addr,
1801 };
1802
1803 /* MDIO bus init function */
1804 static int ravb_mdio_init(struct ravb_private *priv)
1805 {
1806 struct platform_device *pdev = priv->pdev;
1807 struct device *dev = &pdev->dev;
1808 int error;
1809
1810 /* Bitbang init */
1811 priv->mdiobb.ops = &bb_ops;
1812
1813 /* MII controller setting */
1814 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1815 if (!priv->mii_bus)
1816 return -ENOMEM;
1817
1818 /* Hook up MII support for ethtool */
1819 priv->mii_bus->name = "ravb_mii";
1820 priv->mii_bus->parent = dev;
1821 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1822 pdev->name, pdev->id);
1823
1824 /* Register MDIO bus */
1825 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1826 if (error)
1827 goto out_free_bus;
1828
1829 return 0;
1830
1831 out_free_bus:
1832 free_mdio_bitbang(priv->mii_bus);
1833 return error;
1834 }
1835
1836 /* MDIO bus release function */
1837 static int ravb_mdio_release(struct ravb_private *priv)
1838 {
1839 /* Unregister mdio bus */
1840 mdiobus_unregister(priv->mii_bus);
1841
1842 /* Free bitbang info */
1843 free_mdio_bitbang(priv->mii_bus);
1844
1845 return 0;
1846 }
1847
1848 static const struct of_device_id ravb_match_table[] = {
1849 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1850 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1851 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1852 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1853 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1854 { }
1855 };
1856 MODULE_DEVICE_TABLE(of, ravb_match_table);
1857
1858 static int ravb_set_gti(struct net_device *ndev)
1859 {
1860
1861 struct device *dev = ndev->dev.parent;
1862 struct device_node *np = dev->of_node;
1863 unsigned long rate;
1864 struct clk *clk;
1865 uint64_t inc;
1866
1867 clk = of_clk_get(np, 0);
1868 if (IS_ERR(clk)) {
1869 dev_err(dev, "could not get clock\n");
1870 return PTR_ERR(clk);
1871 }
1872
1873 rate = clk_get_rate(clk);
1874 clk_put(clk);
1875
1876 if (!rate)
1877 return -EINVAL;
1878
1879 inc = 1000000000ULL << 20;
1880 do_div(inc, rate);
1881
1882 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1883 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1884 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1885 return -EINVAL;
1886 }
1887
1888 ravb_write(ndev, inc, GTI);
1889
1890 return 0;
1891 }
1892
1893 static void ravb_set_config_mode(struct net_device *ndev)
1894 {
1895 struct ravb_private *priv = netdev_priv(ndev);
1896
1897 if (priv->chip_id == RCAR_GEN2) {
1898 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1899 /* Set CSEL value */
1900 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1901 } else {
1902 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1903 CCC_GAC | CCC_CSEL_HPB);
1904 }
1905 }
1906
1907 static int ravb_probe(struct platform_device *pdev)
1908 {
1909 struct device_node *np = pdev->dev.of_node;
1910 struct ravb_private *priv;
1911 enum ravb_chip_id chip_id;
1912 struct net_device *ndev;
1913 int error, irq, q;
1914 struct resource *res;
1915 int i;
1916
1917 if (!np) {
1918 dev_err(&pdev->dev,
1919 "this driver is required to be instantiated from device tree\n");
1920 return -EINVAL;
1921 }
1922
1923 /* Get base address */
1924 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1925 if (!res) {
1926 dev_err(&pdev->dev, "invalid resource\n");
1927 return -EINVAL;
1928 }
1929
1930 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
1931 NUM_TX_QUEUE, NUM_RX_QUEUE);
1932 if (!ndev)
1933 return -ENOMEM;
1934
1935 pm_runtime_enable(&pdev->dev);
1936 pm_runtime_get_sync(&pdev->dev);
1937
1938 /* The Ether-specific entries in the device structure. */
1939 ndev->base_addr = res->start;
1940
1941 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
1942
1943 if (chip_id == RCAR_GEN3)
1944 irq = platform_get_irq_byname(pdev, "ch22");
1945 else
1946 irq = platform_get_irq(pdev, 0);
1947 if (irq < 0) {
1948 error = irq;
1949 goto out_release;
1950 }
1951 ndev->irq = irq;
1952
1953 SET_NETDEV_DEV(ndev, &pdev->dev);
1954
1955 priv = netdev_priv(ndev);
1956 priv->ndev = ndev;
1957 priv->pdev = pdev;
1958 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
1959 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
1960 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
1961 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
1962 priv->addr = devm_ioremap_resource(&pdev->dev, res);
1963 if (IS_ERR(priv->addr)) {
1964 error = PTR_ERR(priv->addr);
1965 goto out_release;
1966 }
1967
1968 spin_lock_init(&priv->lock);
1969 INIT_WORK(&priv->work, ravb_tx_timeout_work);
1970
1971 priv->phy_interface = of_get_phy_mode(np);
1972
1973 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
1974 priv->avb_link_active_low =
1975 of_property_read_bool(np, "renesas,ether-link-active-low");
1976
1977 if (chip_id == RCAR_GEN3) {
1978 irq = platform_get_irq_byname(pdev, "ch24");
1979 if (irq < 0) {
1980 error = irq;
1981 goto out_release;
1982 }
1983 priv->emac_irq = irq;
1984 for (i = 0; i < NUM_RX_QUEUE; i++) {
1985 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
1986 if (irq < 0) {
1987 error = irq;
1988 goto out_release;
1989 }
1990 priv->rx_irqs[i] = irq;
1991 }
1992 for (i = 0; i < NUM_TX_QUEUE; i++) {
1993 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
1994 if (irq < 0) {
1995 error = irq;
1996 goto out_release;
1997 }
1998 priv->tx_irqs[i] = irq;
1999 }
2000 }
2001
2002 priv->chip_id = chip_id;
2003
2004 /* Set function */
2005 ndev->netdev_ops = &ravb_netdev_ops;
2006 ndev->ethtool_ops = &ravb_ethtool_ops;
2007
2008 /* Set AVB config mode */
2009 ravb_set_config_mode(ndev);
2010
2011 /* Set GTI value */
2012 error = ravb_set_gti(ndev);
2013 if (error)
2014 goto out_release;
2015
2016 /* Request GTI loading */
2017 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2018
2019 /* Allocate descriptor base address table */
2020 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2021 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2022 &priv->desc_bat_dma, GFP_KERNEL);
2023 if (!priv->desc_bat) {
2024 dev_err(&pdev->dev,
2025 "Cannot allocate desc base address table (size %d bytes)\n",
2026 priv->desc_bat_size);
2027 error = -ENOMEM;
2028 goto out_release;
2029 }
2030 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2031 priv->desc_bat[q].die_dt = DT_EOS;
2032 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2033
2034 /* Initialise HW timestamp list */
2035 INIT_LIST_HEAD(&priv->ts_skb_list);
2036
2037 /* Initialise PTP Clock driver */
2038 if (chip_id != RCAR_GEN2)
2039 ravb_ptp_init(ndev, pdev);
2040
2041 /* Debug message level */
2042 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2043
2044 /* Read and set MAC address */
2045 ravb_read_mac_address(ndev, of_get_mac_address(np));
2046 if (!is_valid_ether_addr(ndev->dev_addr)) {
2047 dev_warn(&pdev->dev,
2048 "no valid MAC address supplied, using a random one\n");
2049 eth_hw_addr_random(ndev);
2050 }
2051
2052 /* MDIO bus init */
2053 error = ravb_mdio_init(priv);
2054 if (error) {
2055 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2056 goto out_dma_free;
2057 }
2058
2059 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2060 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2061
2062 /* Network device register */
2063 error = register_netdev(ndev);
2064 if (error)
2065 goto out_napi_del;
2066
2067 /* Print device information */
2068 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2069 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2070
2071 platform_set_drvdata(pdev, ndev);
2072
2073 return 0;
2074
2075 out_napi_del:
2076 netif_napi_del(&priv->napi[RAVB_NC]);
2077 netif_napi_del(&priv->napi[RAVB_BE]);
2078 ravb_mdio_release(priv);
2079 out_dma_free:
2080 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2081 priv->desc_bat_dma);
2082
2083 /* Stop PTP Clock driver */
2084 if (chip_id != RCAR_GEN2)
2085 ravb_ptp_stop(ndev);
2086 out_release:
2087 if (ndev)
2088 free_netdev(ndev);
2089
2090 pm_runtime_put(&pdev->dev);
2091 pm_runtime_disable(&pdev->dev);
2092 return error;
2093 }
2094
2095 static int ravb_remove(struct platform_device *pdev)
2096 {
2097 struct net_device *ndev = platform_get_drvdata(pdev);
2098 struct ravb_private *priv = netdev_priv(ndev);
2099
2100 /* Stop PTP Clock driver */
2101 if (priv->chip_id != RCAR_GEN2)
2102 ravb_ptp_stop(ndev);
2103
2104 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2105 priv->desc_bat_dma);
2106 /* Set reset mode */
2107 ravb_write(ndev, CCC_OPC_RESET, CCC);
2108 pm_runtime_put_sync(&pdev->dev);
2109 unregister_netdev(ndev);
2110 netif_napi_del(&priv->napi[RAVB_NC]);
2111 netif_napi_del(&priv->napi[RAVB_BE]);
2112 ravb_mdio_release(priv);
2113 pm_runtime_disable(&pdev->dev);
2114 free_netdev(ndev);
2115 platform_set_drvdata(pdev, NULL);
2116
2117 return 0;
2118 }
2119
2120 static int __maybe_unused ravb_suspend(struct device *dev)
2121 {
2122 struct net_device *ndev = dev_get_drvdata(dev);
2123 int ret = 0;
2124
2125 if (netif_running(ndev)) {
2126 netif_device_detach(ndev);
2127 ret = ravb_close(ndev);
2128 }
2129
2130 return ret;
2131 }
2132
2133 static int __maybe_unused ravb_resume(struct device *dev)
2134 {
2135 struct net_device *ndev = dev_get_drvdata(dev);
2136 struct ravb_private *priv = netdev_priv(ndev);
2137 int ret = 0;
2138
2139 /* All register have been reset to default values.
2140 * Restore all registers which where setup at probe time and
2141 * reopen device if it was running before system suspended.
2142 */
2143
2144 /* Set AVB config mode */
2145 ravb_set_config_mode(ndev);
2146
2147 /* Set GTI value */
2148 ret = ravb_set_gti(ndev);
2149 if (ret)
2150 return ret;
2151
2152 /* Request GTI loading */
2153 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2154
2155 /* Restore descriptor base address table */
2156 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2157
2158 if (netif_running(ndev)) {
2159 ret = ravb_open(ndev);
2160 if (ret < 0)
2161 return ret;
2162 netif_device_attach(ndev);
2163 }
2164
2165 return ret;
2166 }
2167
2168 static int __maybe_unused ravb_runtime_nop(struct device *dev)
2169 {
2170 /* Runtime PM callback shared between ->runtime_suspend()
2171 * and ->runtime_resume(). Simply returns success.
2172 *
2173 * This driver re-initializes all registers after
2174 * pm_runtime_get_sync() anyway so there is no need
2175 * to save and restore registers here.
2176 */
2177 return 0;
2178 }
2179
2180 static const struct dev_pm_ops ravb_dev_pm_ops = {
2181 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2182 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2183 };
2184
2185 static struct platform_driver ravb_driver = {
2186 .probe = ravb_probe,
2187 .remove = ravb_remove,
2188 .driver = {
2189 .name = "ravb",
2190 .pm = &ravb_dev_pm_ops,
2191 .of_match_table = ravb_match_table,
2192 },
2193 };
2194
2195 module_platform_driver(ravb_driver);
2196
2197 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2198 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2199 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support