include/dt-bindings/clock/r8a7790-clock.h

   1 /*
   2  * Copyright 2013 Ideas On Board SPRL
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
  11 #define __DT_BINDINGS_CLOCK_R8A7790_H__
  12
  13 /* CPG */
  14 #define R8A7790_CLK_MAIN                0
  15 #define R8A7790_CLK_PLL0                1
  16 #define R8A7790_CLK_PLL1                2
  17 #define R8A7790_CLK_PLL3                3
  18 #define R8A7790_CLK_LB                  4
  19 #define R8A7790_CLK_QSPI                5
  20 #define R8A7790_CLK_SDH                 6
  21 #define R8A7790_CLK_SD0                 7
  22 #define R8A7790_CLK_SD1                 8
  23 #define R8A7790_CLK_Z                   9
  24 #define R8A7790_CLK_RCAN                10
  25 #define R8A7790_CLK_ADSP                11
  26
  27 /* MSTP0 */
  28 #define R8A7790_CLK_MSIOF0              0
  29
  30 /* MSTP1 */
  31 #define R8A7790_CLK_VCP1                0
  32 #define R8A7790_CLK_VCP0                1
  33 #define R8A7790_CLK_VPC1                2
  34 #define R8A7790_CLK_VPC0                3
  35 #define R8A7790_CLK_JPU                 6
  36 #define R8A7790_CLK_SSP1                9
  37 #define R8A7790_CLK_TMU1                11
  38 #define R8A7790_CLK_3DG                 12
  39 #define R8A7790_CLK_2DDMAC              15
  40 #define R8A7790_CLK_FDP1_2              17
  41 #define R8A7790_CLK_FDP1_1              18
  42 #define R8A7790_CLK_FDP1_0              19
  43 #define R8A7790_CLK_TMU3                21
  44 #define R8A7790_CLK_TMU2                22
  45 #define R8A7790_CLK_CMT0                24
  46 #define R8A7790_CLK_TMU0                25
  47 #define R8A7790_CLK_VSP1_DU1            27
  48 #define R8A7790_CLK_VSP1_DU0            28
  49 #define R8A7790_CLK_VSP1_R              30
  50 #define R8A7790_CLK_VSP1_S              31
  51
  52 /* MSTP2 */
  53 #define R8A7790_CLK_SCIFA2              2
  54 #define R8A7790_CLK_SCIFA1              3
  55 #define R8A7790_CLK_SCIFA0              4
  56 #define R8A7790_CLK_MSIOF2              5
  57 #define R8A7790_CLK_SCIFB0              6
  58 #define R8A7790_CLK_SCIFB1              7
  59 #define R8A7790_CLK_MSIOF1              8
  60 #define R8A7790_CLK_MSIOF3              15
  61 #define R8A7790_CLK_SCIFB2              16
  62 #define R8A7790_CLK_SYS_DMAC1           18
  63 #define R8A7790_CLK_SYS_DMAC0           19
  64
  65 /* MSTP3 */
  66 #define R8A7790_CLK_IIC2                0
  67 #define R8A7790_CLK_TPU0                4
  68 #define R8A7790_CLK_MMCIF1              5
  69 #define R8A7790_CLK_SCIF2               10
  70 #define R8A7790_CLK_SDHI3               11
  71 #define R8A7790_CLK_SDHI2               12
  72 #define R8A7790_CLK_SDHI1               13
  73 #define R8A7790_CLK_SDHI0               14
  74 #define R8A7790_CLK_MMCIF0              15
  75 #define R8A7790_CLK_IIC0                18
  76 #define R8A7790_CLK_PCIEC               19
  77 #define R8A7790_CLK_IIC1                23
  78 #define R8A7790_CLK_SSUSB               28
  79 #define R8A7790_CLK_CMT1                29
  80 #define R8A7790_CLK_USBDMAC0            30
  81 #define R8A7790_CLK_USBDMAC1            31
  82
  83 /* MSTP4 */
  84 #define R8A7790_CLK_IRQC                7
  85
  86 /* MSTP5 */
  87 #define R8A7790_CLK_AUDIO_DMAC1         1
  88 #define R8A7790_CLK_AUDIO_DMAC0         2
  89 #define R8A7790_CLK_ADSP_MOD            6
  90 #define R8A7790_CLK_THERMAL             22
  91 #define R8A7790_CLK_PWM                 23
  92
  93 /* MSTP7 */
  94 #define R8A7790_CLK_EHCI                3
  95 #define R8A7790_CLK_HSUSB               4
  96 #define R8A7790_CLK_HSCIF1              16
  97 #define R8A7790_CLK_HSCIF0              17
  98 #define R8A7790_CLK_SCIF1               20
  99 #define R8A7790_CLK_SCIF0               21
 100 #define R8A7790_CLK_DU2                 22
 101 #define R8A7790_CLK_DU1                 23
 102 #define R8A7790_CLK_DU0                 24
 103 #define R8A7790_CLK_LVDS1               25
 104 #define R8A7790_CLK_LVDS0               26
 105
 106 /* MSTP8 */
 107 #define R8A7790_CLK_MLB                 2
 108 #define R8A7790_CLK_VIN3                8
 109 #define R8A7790_CLK_VIN2                9
 110 #define R8A7790_CLK_VIN1                10
 111 #define R8A7790_CLK_VIN0                11
 112 #define R8A7790_CLK_ETHERAVB            12
 113 #define R8A7790_CLK_ETHER               13
 114 #define R8A7790_CLK_SATA1               14
 115 #define R8A7790_CLK_SATA0               15
 116
 117 /* MSTP9 */
 118 #define R8A7790_CLK_GPIO5               7
 119 #define R8A7790_CLK_GPIO4               8
 120 #define R8A7790_CLK_GPIO3               9
 121 #define R8A7790_CLK_GPIO2               10
 122 #define R8A7790_CLK_GPIO1               11
 123 #define R8A7790_CLK_GPIO0               12
 124 #define R8A7790_CLK_RCAN1               15
 125 #define R8A7790_CLK_RCAN0               16
 126 #define R8A7790_CLK_QSPI_MOD            17
 127 #define R8A7790_CLK_IICDVFS             26
 128 #define R8A7790_CLK_I2C3                28
 129 #define R8A7790_CLK_I2C2                29
 130 #define R8A7790_CLK_I2C1                30
 131 #define R8A7790_CLK_I2C0                31
 132
 133 /* MSTP10 */
 134 #define R8A7790_CLK_SSI_ALL             5
 135 #define R8A7790_CLK_SSI9                6
 136 #define R8A7790_CLK_SSI8                7
 137 #define R8A7790_CLK_SSI7                8
 138 #define R8A7790_CLK_SSI6                9
 139 #define R8A7790_CLK_SSI5                10
 140 #define R8A7790_CLK_SSI4                11
 141 #define R8A7790_CLK_SSI3                12
 142 #define R8A7790_CLK_SSI2                13
 143 #define R8A7790_CLK_SSI1                14
 144 #define R8A7790_CLK_SSI0                15
 145 #define R8A7790_CLK_SCU_ALL             17
 146 #define R8A7790_CLK_SCU_DVC1            18
 147 #define R8A7790_CLK_SCU_DVC0            19
 148 #define R8A7790_CLK_SCU_CTU1_MIX1       20
 149 #define R8A7790_CLK_SCU_CTU0_MIX0       21
 150 #define R8A7790_CLK_SCU_SRC9            22
 151 #define R8A7790_CLK_SCU_SRC8            23
 152 #define R8A7790_CLK_SCU_SRC7            24
 153 #define R8A7790_CLK_SCU_SRC6            25
 154 #define R8A7790_CLK_SCU_SRC5            26
 155 #define R8A7790_CLK_SCU_SRC4            27
 156 #define R8A7790_CLK_SCU_SRC3            28
 157 #define R8A7790_CLK_SCU_SRC2            29
 158 #define R8A7790_CLK_SCU_SRC1            30
 159 #define R8A7790_CLK_SCU_SRC0            31
 160
 161 #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */