include/dt-bindings/clock/rk3228-cru.h

   1 /*
   2  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   3  * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
  17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
  18
  19 /* core clocks */
  20 #define PLL_APLL                1
  21 #define PLL_DPLL                2
  22 #define PLL_CPLL                3
  23 #define PLL_GPLL                4
  24 #define ARMCLK                  5
  25
  26 /* sclk gates (special clocks) */
  27 #define SCLK_SPI0               65
  28 #define SCLK_NANDC              67
  29 #define SCLK_SDMMC              68
  30 #define SCLK_SDIO               69
  31 #define SCLK_EMMC               71
  32 #define SCLK_TSADC              72
  33 #define SCLK_UART0              77
  34 #define SCLK_UART1              78
  35 #define SCLK_UART2              79
  36 #define SCLK_I2S0               80
  37 #define SCLK_I2S1               81
  38 #define SCLK_I2S2               82
  39 #define SCLK_SPDIF              83
  40 #define SCLK_TIMER0             85
  41 #define SCLK_TIMER1             86
  42 #define SCLK_TIMER2             87
  43 #define SCLK_TIMER3             88
  44 #define SCLK_TIMER4             89
  45 #define SCLK_TIMER5             90
  46 #define SCLK_I2S_OUT            113
  47 #define SCLK_SDMMC_DRV          114
  48 #define SCLK_SDIO_DRV           115
  49 #define SCLK_EMMC_DRV           117
  50 #define SCLK_SDMMC_SAMPLE       118
  51 #define SCLK_SDIO_SAMPLE        119
  52 #define SCLK_EMMC_SAMPLE        121
  53 #define SCLK_VOP                122
  54 #define SCLK_HDMI_HDCP          123
  55 #define SCLK_MAC_SRC            124
  56 #define SCLK_MAC_EXTCLK         125
  57 #define SCLK_MAC                126
  58 #define SCLK_MAC_REFOUT         127
  59 #define SCLK_MAC_REF            128
  60 #define SCLK_MAC_RX             129
  61 #define SCLK_MAC_TX             130
  62 #define SCLK_MAC_PHY            131
  63 #define SCLK_MAC_OUT            132
  64
  65 /* dclk gates */
  66 #define DCLK_VOP                190
  67 #define DCLK_HDMI_PHY           191
  68
  69 /* aclk gates */
  70 #define ACLK_DMAC               194
  71 #define ACLK_PERI               210
  72 #define ACLK_VOP                211
  73 #define ACLK_GMAC               212
  74
  75 /* pclk gates */
  76 #define PCLK_GPIO0              320
  77 #define PCLK_GPIO1              321
  78 #define PCLK_GPIO2              322
  79 #define PCLK_GPIO3              323
  80 #define PCLK_GRF                329
  81 #define PCLK_I2C0               332
  82 #define PCLK_I2C1               333
  83 #define PCLK_I2C2               334
  84 #define PCLK_I2C3               335
  85 #define PCLK_SPI0               338
  86 #define PCLK_UART0              341
  87 #define PCLK_UART1              342
  88 #define PCLK_UART2              343
  89 #define PCLK_TSADC              344
  90 #define PCLK_PWM                350
  91 #define PCLK_TIMER              353
  92 #define PCLK_PERI               363
  93 #define PCLK_HDMI_CTRL          364
  94 #define PCLK_HDMI_PHY           365
  95 #define PCLK_GMAC               367
  96
  97 /* hclk gates */
  98 #define HCLK_I2S0_8CH           442
  99 #define HCLK_I2S1_8CH           443
 100 #define HCLK_I2S2_2CH           444
 101 #define HCLK_SPDIF_8CH          445
 102 #define HCLK_VOP                452
 103 #define HCLK_NANDC              453
 104 #define HCLK_SDMMC              456
 105 #define HCLK_SDIO               457
 106 #define HCLK_EMMC               459
 107 #define HCLK_PERI               478
 108
 109 #define CLK_NR_CLKS             (HCLK_PERI + 1)
 110
 111 /* soft-reset indices */
 112 #define SRST_CORE0_PO           0
 113 #define SRST_CORE1_PO           1
 114 #define SRST_CORE2_PO           2
 115 #define SRST_CORE3_PO           3
 116 #define SRST_CORE0              4
 117 #define SRST_CORE1              5
 118 #define SRST_CORE2              6
 119 #define SRST_CORE3              7
 120 #define SRST_CORE0_DBG          8
 121 #define SRST_CORE1_DBG          9
 122 #define SRST_CORE2_DBG          10
 123 #define SRST_CORE3_DBG          11
 124 #define SRST_TOPDBG             12
 125 #define SRST_ACLK_CORE          13
 126 #define SRST_NOC                14
 127 #define SRST_L2C                15
 128
 129 #define SRST_CPUSYS_H           18
 130 #define SRST_BUSSYS_H           19
 131 #define SRST_SPDIF              20
 132 #define SRST_INTMEM             21
 133 #define SRST_ROM                22
 134 #define SRST_OTG_ADP            23
 135 #define SRST_I2S0               24
 136 #define SRST_I2S1               25
 137 #define SRST_I2S2               26
 138 #define SRST_ACODEC_P           27
 139 #define SRST_DFIMON             28
 140 #define SRST_MSCH               29
 141 #define SRST_EFUSE1024          30
 142 #define SRST_EFUSE256           31
 143
 144 #define SRST_GPIO0              32
 145 #define SRST_GPIO1              33
 146 #define SRST_GPIO2              34
 147 #define SRST_GPIO3              35
 148 #define SRST_PERIPH_NOC_A       36
 149 #define SRST_PERIPH_NOC_BUS_H   37
 150 #define SRST_PERIPH_NOC_P       38
 151 #define SRST_UART0              39
 152 #define SRST_UART1              40
 153 #define SRST_UART2              41
 154 #define SRST_PHYNOC             42
 155 #define SRST_I2C0               43
 156 #define SRST_I2C1               44
 157 #define SRST_I2C2               45
 158 #define SRST_I2C3               46
 159
 160 #define SRST_PWM                48
 161 #define SRST_A53_GIC            49
 162 #define SRST_DAP                51
 163 #define SRST_DAP_NOC            52
 164 #define SRST_CRYPTO             53
 165 #define SRST_SGRF               54
 166 #define SRST_GRF                55
 167 #define SRST_GMAC               56
 168 #define SRST_PERIPH_NOC_H       58
 169 #define SRST_MACPHY             63
 170
 171 #define SRST_DMA                64
 172 #define SRST_NANDC              68
 173 #define SRST_USBOTG             69
 174 #define SRST_OTGC               70
 175 #define SRST_USBHOST0           71
 176 #define SRST_HOST_CTRL0         72
 177 #define SRST_USBHOST1           73
 178 #define SRST_HOST_CTRL1         74
 179 #define SRST_USBHOST2           75
 180 #define SRST_HOST_CTRL2         76
 181 #define SRST_USBPOR0            77
 182 #define SRST_USBPOR1            78
 183 #define SRST_DDRMSCH            79
 184
 185 #define SRST_SMART_CARD         80
 186 #define SRST_SDMMC              81
 187 #define SRST_SDIO               82
 188 #define SRST_EMMC               83
 189 #define SRST_SPI                84
 190 #define SRST_TSP_H              85
 191 #define SRST_TSP                86
 192 #define SRST_TSADC              87
 193 #define SRST_DDRPHY             88
 194 #define SRST_DDRPHY_P           89
 195 #define SRST_DDRCTRL            90
 196 #define SRST_DDRCTRL_P          91
 197 #define SRST_HOST0_ECHI         92
 198 #define SRST_HOST1_ECHI         93
 199 #define SRST_HOST2_ECHI         94
 200 #define SRST_VOP_NOC_A          95
 201
 202 #define SRST_HDMI_P             96
 203 #define SRST_VIO_ARBI_H         97
 204 #define SRST_IEP_NOC_A          98
 205 #define SRST_VIO_NOC_H          99
 206 #define SRST_VOP_A              100
 207 #define SRST_VOP_H              101
 208 #define SRST_VOP_D              102
 209 #define SRST_UTMI0              103
 210 #define SRST_UTMI1              104
 211 #define SRST_UTMI2              105
 212 #define SRST_UTMI3              106
 213 #define SRST_RGA                107
 214 #define SRST_RGA_NOC_A          108
 215 #define SRST_RGA_A              109
 216 #define SRST_RGA_H              110
 217 #define SRST_HDCP_A             111
 218
 219 #define SRST_VPU_A              112
 220 #define SRST_VPU_H              113
 221 #define SRST_VPU_NOC_A          116
 222 #define SRST_VPU_NOC_H          117
 223 #define SRST_RKVDEC_A           118
 224 #define SRST_RKVDEC_NOC_A       119
 225 #define SRST_RKVDEC_H           120
 226 #define SRST_RKVDEC_NOC_H       121
 227 #define SRST_RKVDEC_CORE        122
 228 #define SRST_RKVDEC_CABAC       123
 229 #define SRST_IEP_A              124
 230 #define SRST_IEP_H              125
 231 #define SRST_GPU_A              126
 232 #define SRST_GPU_NOC_A          127
 233
 234 #define SRST_CORE_DBG           128
 235 #define SRST_DBG_P              129
 236 #define SRST_TIMER0             130
 237 #define SRST_TIMER1             131
 238 #define SRST_TIMER2             132
 239 #define SRST_TIMER3             133
 240 #define SRST_TIMER4             134
 241 #define SRST_TIMER5             135
 242 #define SRST_VIO_H2P            136
 243 #define SRST_HDMIPHY            139
 244 #define SRST_VDAC               140
 245 #define SRST_TIMER_6CH_P        141
 246
 247 #endif