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r8152: fix tx packets accounting
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-amd.c
bloba5b7bd3c9bac3b22d3e873d13d9223a9d361d907
1 /*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
22 #include <linux/io.h>
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
34
35 #include "core.h"
36 #include "pinctrl-utils.h"
37 #include "pinctrl-amd.h"
38
39 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
40 {
41 unsigned long flags;
42 u32 pin_reg;
43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
44
45 spin_lock_irqsave(&gpio_dev->lock, flags);
46 pin_reg = readl(gpio_dev->base + offset * 4);
47 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
48 writel(pin_reg, gpio_dev->base + offset * 4);
49 spin_unlock_irqrestore(&gpio_dev->lock, flags);
50
51 return 0;
52 }
53
54 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
55 int value)
56 {
57 u32 pin_reg;
58 unsigned long flags;
59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
60
61 spin_lock_irqsave(&gpio_dev->lock, flags);
62 pin_reg = readl(gpio_dev->base + offset * 4);
63 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
64 if (value)
65 pin_reg |= BIT(OUTPUT_VALUE_OFF);
66 else
67 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
68 writel(pin_reg, gpio_dev->base + offset * 4);
69 spin_unlock_irqrestore(&gpio_dev->lock, flags);
70
71 return 0;
72 }
73
74 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
75 {
76 u32 pin_reg;
77 unsigned long flags;
78 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
79
80 spin_lock_irqsave(&gpio_dev->lock, flags);
81 pin_reg = readl(gpio_dev->base + offset * 4);
82 spin_unlock_irqrestore(&gpio_dev->lock, flags);
83
84 return !!(pin_reg & BIT(PIN_STS_OFF));
85 }
86
87 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
88 {
89 u32 pin_reg;
90 unsigned long flags;
91 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
92
93 spin_lock_irqsave(&gpio_dev->lock, flags);
94 pin_reg = readl(gpio_dev->base + offset * 4);
95 if (value)
96 pin_reg |= BIT(OUTPUT_VALUE_OFF);
97 else
98 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
99 writel(pin_reg, gpio_dev->base + offset * 4);
100 spin_unlock_irqrestore(&gpio_dev->lock, flags);
101 }
102
103 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
104 unsigned debounce)
105 {
106 u32 time;
107 u32 pin_reg;
108 int ret = 0;
109 unsigned long flags;
110 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
111
112 spin_lock_irqsave(&gpio_dev->lock, flags);
113 pin_reg = readl(gpio_dev->base + offset * 4);
114
115 if (debounce) {
116 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
117 pin_reg &= ~DB_TMR_OUT_MASK;
118 /*
119 Debounce Debounce Timer Max
120 TmrLarge TmrOutUnit Unit Debounce
121 Time
122 0 0 61 usec (2 RtcClk) 976 usec
123 0 1 244 usec (8 RtcClk) 3.9 msec
124 1 0 15.6 msec (512 RtcClk) 250 msec
125 1 1 62.5 msec (2048 RtcClk) 1 sec
126 */
127
128 if (debounce < 61) {
129 pin_reg |= 1;
130 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
131 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
132 } else if (debounce < 976) {
133 time = debounce / 61;
134 pin_reg |= time & DB_TMR_OUT_MASK;
135 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
136 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
137 } else if (debounce < 3900) {
138 time = debounce / 244;
139 pin_reg |= time & DB_TMR_OUT_MASK;
140 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
141 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
142 } else if (debounce < 250000) {
143 time = debounce / 15600;
144 pin_reg |= time & DB_TMR_OUT_MASK;
145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
146 pin_reg |= BIT(DB_TMR_LARGE_OFF);
147 } else if (debounce < 1000000) {
148 time = debounce / 62500;
149 pin_reg |= time & DB_TMR_OUT_MASK;
150 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
151 pin_reg |= BIT(DB_TMR_LARGE_OFF);
152 } else {
153 pin_reg &= ~DB_CNTRl_MASK;
154 ret = -EINVAL;
155 }
156 } else {
157 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
158 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
159 pin_reg &= ~DB_TMR_OUT_MASK;
160 pin_reg &= ~DB_CNTRl_MASK;
161 }
162 writel(pin_reg, gpio_dev->base + offset * 4);
163 spin_unlock_irqrestore(&gpio_dev->lock, flags);
164
165 return ret;
166 }
167
168 #ifdef CONFIG_DEBUG_FS
169 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
170 {
171 u32 pin_reg;
172 unsigned long flags;
173 unsigned int bank, i, pin_num;
174 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
175
176 char *level_trig;
177 char *active_level;
178 char *interrupt_enable;
179 char *interrupt_mask;
180 char *wake_cntrl0;
181 char *wake_cntrl1;
182 char *wake_cntrl2;
183 char *pin_sts;
184 char *pull_up_sel;
185 char *pull_up_enable;
186 char *pull_down_enable;
187 char *output_value;
188 char *output_enable;
189
190 for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
191 seq_printf(s, "GPIO bank%d\t", bank);
192
193 switch (bank) {
194 case 0:
195 i = 0;
196 pin_num = AMD_GPIO_PINS_BANK0;
197 break;
198 case 1:
199 i = 64;
200 pin_num = AMD_GPIO_PINS_BANK1 + i;
201 break;
202 case 2:
203 i = 128;
204 pin_num = AMD_GPIO_PINS_BANK2 + i;
205 break;
206 }
207
208 for (; i < pin_num; i++) {
209 seq_printf(s, "pin%d\t", i);
210 spin_lock_irqsave(&gpio_dev->lock, flags);
211 pin_reg = readl(gpio_dev->base + i * 4);
212 spin_unlock_irqrestore(&gpio_dev->lock, flags);
213
214 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
215 interrupt_enable = "interrupt is enabled|";
216
217 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
218 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
219 active_level = "Active low|";
220 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
221 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
222 active_level = "Active high|";
223 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
224 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
225 active_level = "Active on both|";
226 else
227 active_level = "Unknow Active level|";
228
229 if (pin_reg & BIT(LEVEL_TRIG_OFF))
230 level_trig = "Level trigger|";
231 else
232 level_trig = "Edge trigger|";
233
234 } else {
235 interrupt_enable =
236 "interrupt is disabled|";
237 active_level = " ";
238 level_trig = " ";
239 }
240
241 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
242 interrupt_mask =
243 "interrupt is unmasked|";
244 else
245 interrupt_mask =
246 "interrupt is masked|";
247
248 if (pin_reg & BIT(WAKE_CNTRL_OFF))
249 wake_cntrl0 = "enable wakeup in S0i3 state|";
250 else
251 wake_cntrl0 = "disable wakeup in S0i3 state|";
252
253 if (pin_reg & BIT(WAKE_CNTRL_OFF))
254 wake_cntrl1 = "enable wakeup in S3 state|";
255 else
256 wake_cntrl1 = "disable wakeup in S3 state|";
257
258 if (pin_reg & BIT(WAKE_CNTRL_OFF))
259 wake_cntrl2 = "enable wakeup in S4/S5 state|";
260 else
261 wake_cntrl2 = "disable wakeup in S4/S5 state|";
262
263 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
264 pull_up_enable = "pull-up is enabled|";
265 if (pin_reg & BIT(PULL_UP_SEL_OFF))
266 pull_up_sel = "8k pull-up|";
267 else
268 pull_up_sel = "4k pull-up|";
269 } else {
270 pull_up_enable = "pull-up is disabled|";
271 pull_up_sel = " ";
272 }
273
274 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
275 pull_down_enable = "pull-down is enabled|";
276 else
277 pull_down_enable = "Pull-down is disabled|";
278
279 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
280 pin_sts = " ";
281 output_enable = "output is enabled|";
282 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
283 output_value = "output is high|";
284 else
285 output_value = "output is low|";
286 } else {
287 output_enable = "output is disabled|";
288 output_value = " ";
289
290 if (pin_reg & BIT(PIN_STS_OFF))
291 pin_sts = "input is high|";
292 else
293 pin_sts = "input is low|";
294 }
295
296 seq_printf(s, "%s %s %s %s %s %s\n"
297 " %s %s %s %s %s %s %s 0x%x\n",
298 level_trig, active_level, interrupt_enable,
299 interrupt_mask, wake_cntrl0, wake_cntrl1,
300 wake_cntrl2, pin_sts, pull_up_sel,
301 pull_up_enable, pull_down_enable,
302 output_value, output_enable, pin_reg);
303 }
304 }
305 }
306 #else
307 #define amd_gpio_dbg_show NULL
308 #endif
309
310 static void amd_gpio_irq_enable(struct irq_data *d)
311 {
312 u32 pin_reg;
313 unsigned long flags;
314 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
315 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
316
317 spin_lock_irqsave(&gpio_dev->lock, flags);
318 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
319 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
320 pin_reg |= BIT(INTERRUPT_MASK_OFF);
321 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
322 spin_unlock_irqrestore(&gpio_dev->lock, flags);
323 }
324
325 static void amd_gpio_irq_disable(struct irq_data *d)
326 {
327 u32 pin_reg;
328 unsigned long flags;
329 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
330 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
331
332 spin_lock_irqsave(&gpio_dev->lock, flags);
333 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
334 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
335 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
336 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
337 spin_unlock_irqrestore(&gpio_dev->lock, flags);
338 }
339
340 static void amd_gpio_irq_mask(struct irq_data *d)
341 {
342 u32 pin_reg;
343 unsigned long flags;
344 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
345 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
346
347 spin_lock_irqsave(&gpio_dev->lock, flags);
348 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
349 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
350 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
351 spin_unlock_irqrestore(&gpio_dev->lock, flags);
352 }
353
354 static void amd_gpio_irq_unmask(struct irq_data *d)
355 {
356 u32 pin_reg;
357 unsigned long flags;
358 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
359 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
360
361 spin_lock_irqsave(&gpio_dev->lock, flags);
362 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
363 pin_reg |= BIT(INTERRUPT_MASK_OFF);
364 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
365 spin_unlock_irqrestore(&gpio_dev->lock, flags);
366 }
367
368 static void amd_gpio_irq_eoi(struct irq_data *d)
369 {
370 u32 reg;
371 unsigned long flags;
372 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
373 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
374
375 spin_lock_irqsave(&gpio_dev->lock, flags);
376 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
377 reg |= EOI_MASK;
378 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
379 spin_unlock_irqrestore(&gpio_dev->lock, flags);
380 }
381
382 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
383 {
384 int ret = 0;
385 u32 pin_reg;
386 unsigned long flags, irq_flags;
387 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
388 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
389
390 spin_lock_irqsave(&gpio_dev->lock, flags);
391 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
392
393 /* Ignore the settings coming from the client and
394 * read the values from the ACPI tables
395 * while setting the trigger type
396 */
397
398 irq_flags = irq_get_trigger_type(d->irq);
399 if (irq_flags != IRQ_TYPE_NONE)
400 type = irq_flags;
401
402 switch (type & IRQ_TYPE_SENSE_MASK) {
403 case IRQ_TYPE_EDGE_RISING:
404 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
405 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
406 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
407 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
408 irq_set_handler_locked(d, handle_edge_irq);
409 break;
410
411 case IRQ_TYPE_EDGE_FALLING:
412 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
413 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
414 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
415 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
416 irq_set_handler_locked(d, handle_edge_irq);
417 break;
418
419 case IRQ_TYPE_EDGE_BOTH:
420 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
421 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
422 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
423 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
424 irq_set_handler_locked(d, handle_edge_irq);
425 break;
426
427 case IRQ_TYPE_LEVEL_HIGH:
428 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
429 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
430 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
431 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
432 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
433 irq_set_handler_locked(d, handle_level_irq);
434 break;
435
436 case IRQ_TYPE_LEVEL_LOW:
437 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
438 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
439 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
440 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
441 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
442 irq_set_handler_locked(d, handle_level_irq);
443 break;
444
445 case IRQ_TYPE_NONE:
446 break;
447
448 default:
449 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
450 ret = -EINVAL;
451 }
452
453 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
454 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
455 spin_unlock_irqrestore(&gpio_dev->lock, flags);
456
457 return ret;
458 }
459
460 static void amd_irq_ack(struct irq_data *d)
461 {
462 /*
463 * based on HW design,there is no need to ack HW
464 * before handle current irq. But this routine is
465 * necessary for handle_edge_irq
466 */
467 }
468
469 static struct irq_chip amd_gpio_irqchip = {
470 .name = "amd_gpio",
471 .irq_ack = amd_irq_ack,
472 .irq_enable = amd_gpio_irq_enable,
473 .irq_disable = amd_gpio_irq_disable,
474 .irq_mask = amd_gpio_irq_mask,
475 .irq_unmask = amd_gpio_irq_unmask,
476 .irq_eoi = amd_gpio_irq_eoi,
477 .irq_set_type = amd_gpio_irq_set_type,
478 };
479
480 static void amd_gpio_irq_handler(struct irq_desc *desc)
481 {
482 u32 i;
483 u32 off;
484 u32 reg;
485 u32 pin_reg;
486 u64 reg64;
487 int handled = 0;
488 unsigned int irq;
489 unsigned long flags;
490 struct irq_chip *chip = irq_desc_get_chip(desc);
491 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
492 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
493
494 chained_irq_enter(chip, desc);
495 /*enable GPIO interrupt again*/
496 spin_lock_irqsave(&gpio_dev->lock, flags);
497 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
498 reg64 = reg;
499 reg64 = reg64 << 32;
500
501 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
502 reg64 |= reg;
503 spin_unlock_irqrestore(&gpio_dev->lock, flags);
504
505 /*
506 * first 46 bits indicates interrupt status.
507 * one bit represents four interrupt sources.
508 */
509 for (off = 0; off < 46 ; off++) {
510 if (reg64 & BIT(off)) {
511 for (i = 0; i < 4; i++) {
512 pin_reg = readl(gpio_dev->base +
513 (off * 4 + i) * 4);
514 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
515 (pin_reg & BIT(WAKE_STS_OFF))) {
516 irq = irq_find_mapping(gc->irqdomain,
517 off * 4 + i);
518 generic_handle_irq(irq);
519 writel(pin_reg,
520 gpio_dev->base
521 + (off * 4 + i) * 4);
522 handled++;
523 }
524 }
525 }
526 }
527
528 if (handled == 0)
529 handle_bad_irq(desc);
530
531 spin_lock_irqsave(&gpio_dev->lock, flags);
532 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
533 reg |= EOI_MASK;
534 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
535 spin_unlock_irqrestore(&gpio_dev->lock, flags);
536
537 chained_irq_exit(chip, desc);
538 }
539
540 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
541 {
542 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
543
544 return gpio_dev->ngroups;
545 }
546
547 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
548 unsigned group)
549 {
550 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
551
552 return gpio_dev->groups[group].name;
553 }
554
555 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
556 unsigned group,
557 const unsigned **pins,
558 unsigned *num_pins)
559 {
560 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
561
562 *pins = gpio_dev->groups[group].pins;
563 *num_pins = gpio_dev->groups[group].npins;
564 return 0;
565 }
566
567 static const struct pinctrl_ops amd_pinctrl_ops = {
568 .get_groups_count = amd_get_groups_count,
569 .get_group_name = amd_get_group_name,
570 .get_group_pins = amd_get_group_pins,
571 #ifdef CONFIG_OF
572 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
573 .dt_free_map = pinctrl_utils_free_map,
574 #endif
575 };
576
577 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
578 unsigned int pin,
579 unsigned long *config)
580 {
581 u32 pin_reg;
582 unsigned arg;
583 unsigned long flags;
584 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
585 enum pin_config_param param = pinconf_to_config_param(*config);
586
587 spin_lock_irqsave(&gpio_dev->lock, flags);
588 pin_reg = readl(gpio_dev->base + pin*4);
589 spin_unlock_irqrestore(&gpio_dev->lock, flags);
590 switch (param) {
591 case PIN_CONFIG_INPUT_DEBOUNCE:
592 arg = pin_reg & DB_TMR_OUT_MASK;
593 break;
594
595 case PIN_CONFIG_BIAS_PULL_DOWN:
596 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
597 break;
598
599 case PIN_CONFIG_BIAS_PULL_UP:
600 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
601 break;
602
603 case PIN_CONFIG_DRIVE_STRENGTH:
604 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
605 break;
606
607 default:
608 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
609 param);
610 return -ENOTSUPP;
611 }
612
613 *config = pinconf_to_config_packed(param, arg);
614
615 return 0;
616 }
617
618 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
619 unsigned long *configs, unsigned num_configs)
620 {
621 int i;
622 u32 arg;
623 int ret = 0;
624 u32 pin_reg;
625 unsigned long flags;
626 enum pin_config_param param;
627 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
628
629 spin_lock_irqsave(&gpio_dev->lock, flags);
630 for (i = 0; i < num_configs; i++) {
631 param = pinconf_to_config_param(configs[i]);
632 arg = pinconf_to_config_argument(configs[i]);
633 pin_reg = readl(gpio_dev->base + pin*4);
634
635 switch (param) {
636 case PIN_CONFIG_INPUT_DEBOUNCE:
637 pin_reg &= ~DB_TMR_OUT_MASK;
638 pin_reg |= arg & DB_TMR_OUT_MASK;
639 break;
640
641 case PIN_CONFIG_BIAS_PULL_DOWN:
642 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
643 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
644 break;
645
646 case PIN_CONFIG_BIAS_PULL_UP:
647 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
648 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
649 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
650 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
651 break;
652
653 case PIN_CONFIG_DRIVE_STRENGTH:
654 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
655 << DRV_STRENGTH_SEL_OFF);
656 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
657 << DRV_STRENGTH_SEL_OFF;
658 break;
659
660 default:
661 dev_err(&gpio_dev->pdev->dev,
662 "Invalid config param %04x\n", param);
663 ret = -ENOTSUPP;
664 }
665
666 writel(pin_reg, gpio_dev->base + pin*4);
667 }
668 spin_unlock_irqrestore(&gpio_dev->lock, flags);
669
670 return ret;
671 }
672
673 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
674 unsigned int group,
675 unsigned long *config)
676 {
677 const unsigned *pins;
678 unsigned npins;
679 int ret;
680
681 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
682 if (ret)
683 return ret;
684
685 if (amd_pinconf_get(pctldev, pins[0], config))
686 return -ENOTSUPP;
687
688 return 0;
689 }
690
691 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
692 unsigned group, unsigned long *configs,
693 unsigned num_configs)
694 {
695 const unsigned *pins;
696 unsigned npins;
697 int i, ret;
698
699 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
700 if (ret)
701 return ret;
702 for (i = 0; i < npins; i++) {
703 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
704 return -ENOTSUPP;
705 }
706 return 0;
707 }
708
709 static const struct pinconf_ops amd_pinconf_ops = {
710 .pin_config_get = amd_pinconf_get,
711 .pin_config_set = amd_pinconf_set,
712 .pin_config_group_get = amd_pinconf_group_get,
713 .pin_config_group_set = amd_pinconf_group_set,
714 };
715
716 #ifdef CONFIG_PM_SLEEP
717 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
718 {
719 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
720
721 if (!pd)
722 return false;
723
724 /*
725 * Only restore the pin if it is actually in use by the kernel (or
726 * by userspace).
727 */
728 if (pd->mux_owner || pd->gpio_owner ||
729 gpiochip_line_is_irq(&gpio_dev->gc, pin))
730 return true;
731
732 return false;
733 }
734
735 int amd_gpio_suspend(struct device *dev)
736 {
737 struct platform_device *pdev = to_platform_device(dev);
738 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
739 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
740 int i;
741
742 for (i = 0; i < desc->npins; i++) {
743 int pin = desc->pins[i].number;
744
745 if (!amd_gpio_should_save(gpio_dev, pin))
746 continue;
747
748 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
749 }
750
751 return 0;
752 }
753
754 int amd_gpio_resume(struct device *dev)
755 {
756 struct platform_device *pdev = to_platform_device(dev);
757 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
758 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
759 int i;
760
761 for (i = 0; i < desc->npins; i++) {
762 int pin = desc->pins[i].number;
763
764 if (!amd_gpio_should_save(gpio_dev, pin))
765 continue;
766
767 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
768 }
769
770 return 0;
771 }
772
773 static const struct dev_pm_ops amd_gpio_pm_ops = {
774 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
775 amd_gpio_resume)
776 };
777 #endif
778
779 static struct pinctrl_desc amd_pinctrl_desc = {
780 .pins = kerncz_pins,
781 .npins = ARRAY_SIZE(kerncz_pins),
782 .pctlops = &amd_pinctrl_ops,
783 .confops = &amd_pinconf_ops,
784 .owner = THIS_MODULE,
785 };
786
787 static int amd_gpio_probe(struct platform_device *pdev)
788 {
789 int ret = 0;
790 int irq_base;
791 struct resource *res;
792 struct amd_gpio *gpio_dev;
793
794 gpio_dev = devm_kzalloc(&pdev->dev,
795 sizeof(struct amd_gpio), GFP_KERNEL);
796 if (!gpio_dev)
797 return -ENOMEM;
798
799 spin_lock_init(&gpio_dev->lock);
800
801 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
802 if (!res) {
803 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
804 return -EINVAL;
805 }
806
807 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
808 resource_size(res));
809 if (!gpio_dev->base)
810 return -ENOMEM;
811
812 irq_base = platform_get_irq(pdev, 0);
813 if (irq_base < 0) {
814 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
815 return -EINVAL;
816 }
817
818 #ifdef CONFIG_PM_SLEEP
819 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
820 sizeof(*gpio_dev->saved_regs),
821 GFP_KERNEL);
822 if (!gpio_dev->saved_regs)
823 return -ENOMEM;
824 #endif
825
826 gpio_dev->pdev = pdev;
827 gpio_dev->gc.direction_input = amd_gpio_direction_input;
828 gpio_dev->gc.direction_output = amd_gpio_direction_output;
829 gpio_dev->gc.get = amd_gpio_get_value;
830 gpio_dev->gc.set = amd_gpio_set_value;
831 gpio_dev->gc.set_debounce = amd_gpio_set_debounce;
832 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
833
834 gpio_dev->gc.base = 0;
835 gpio_dev->gc.label = pdev->name;
836 gpio_dev->gc.owner = THIS_MODULE;
837 gpio_dev->gc.parent = &pdev->dev;
838 gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS;
839 #if defined(CONFIG_OF_GPIO)
840 gpio_dev->gc.of_node = pdev->dev.of_node;
841 #endif
842
843 gpio_dev->groups = kerncz_groups;
844 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
845
846 amd_pinctrl_desc.name = dev_name(&pdev->dev);
847 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
848 gpio_dev);
849 if (IS_ERR(gpio_dev->pctrl)) {
850 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
851 return PTR_ERR(gpio_dev->pctrl);
852 }
853
854 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
855 if (ret)
856 return ret;
857
858 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
859 0, 0, TOTAL_NUMBER_OF_PINS);
860 if (ret) {
861 dev_err(&pdev->dev, "Failed to add pin range\n");
862 goto out2;
863 }
864
865 ret = gpiochip_irqchip_add(&gpio_dev->gc,
866 &amd_gpio_irqchip,
867 0,
868 handle_simple_irq,
869 IRQ_TYPE_NONE);
870 if (ret) {
871 dev_err(&pdev->dev, "could not add irqchip\n");
872 ret = -ENODEV;
873 goto out2;
874 }
875
876 gpiochip_set_chained_irqchip(&gpio_dev->gc,
877 &amd_gpio_irqchip,
878 irq_base,
879 amd_gpio_irq_handler);
880
881 platform_set_drvdata(pdev, gpio_dev);
882
883 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
884 return ret;
885
886 out2:
887 gpiochip_remove(&gpio_dev->gc);
888
889 return ret;
890 }
891
892 static int amd_gpio_remove(struct platform_device *pdev)
893 {
894 struct amd_gpio *gpio_dev;
895
896 gpio_dev = platform_get_drvdata(pdev);
897
898 gpiochip_remove(&gpio_dev->gc);
899
900 return 0;
901 }
902
903 static const struct acpi_device_id amd_gpio_acpi_match[] = {
904 { "AMD0030", 0 },
905 { "AMDI0030", 0},
906 { },
907 };
908 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
909
910 static struct platform_driver amd_gpio_driver = {
911 .driver = {
912 .name = "amd_gpio",
913 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
914 #ifdef CONFIG_PM_SLEEP
915 .pm = &amd_gpio_pm_ops,
916 #endif
917 },
918 .probe = amd_gpio_probe,
919 .remove = amd_gpio_remove,
920 };
921
922 module_platform_driver(amd_gpio_driver);
923
924 MODULE_LICENSE("GPL v2");
925 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
926 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
Linux with added FPC-III support