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r8152: fix tx packets accounting
[linux/fpc-iii.git] / drivers / pinctrl / sh-pfc / pfc-r8a7796.c
blobdc9b671ccf2e51261d26becbbe32572de67b6b2e
1 /*
2 * R8A7796 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 *
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
7 *
8 * R-Car Gen3 processor support - PFC hardware block.
9 *
10 * Copyright (C) 2015 Renesas Electronics Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 */
16
17 #include <linux/kernel.h>
18
19 #include "core.h"
20 #include "sh_pfc.h"
21
22 #define CPU_ALL_PORT(fn, sfx) \
23 PORT_GP_16(0, fn, sfx), \
24 PORT_GP_29(1, fn, sfx), \
25 PORT_GP_15(2, fn, sfx), \
26 PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_1(3, 12, fn, sfx), \
28 PORT_GP_1(3, 13, fn, sfx), \
29 PORT_GP_1(3, 14, fn, sfx), \
30 PORT_GP_1(3, 15, fn, sfx), \
31 PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_26(5, fn, sfx), \
33 PORT_GP_32(6, fn, sfx), \
34 PORT_GP_4(7, fn, sfx)
35 /*
36 * F_() : just information
37 * FM() : macro for FN_xxx / xxx_MARK
38 */
39
40 /* GPSR0 */
41 #define GPSR0_15 F_(D15, IP7_11_8)
42 #define GPSR0_14 F_(D14, IP7_7_4)
43 #define GPSR0_13 F_(D13, IP7_3_0)
44 #define GPSR0_12 F_(D12, IP6_31_28)
45 #define GPSR0_11 F_(D11, IP6_27_24)
46 #define GPSR0_10 F_(D10, IP6_23_20)
47 #define GPSR0_9 F_(D9, IP6_19_16)
48 #define GPSR0_8 F_(D8, IP6_15_12)
49 #define GPSR0_7 F_(D7, IP6_11_8)
50 #define GPSR0_6 F_(D6, IP6_7_4)
51 #define GPSR0_5 F_(D5, IP6_3_0)
52 #define GPSR0_4 F_(D4, IP5_31_28)
53 #define GPSR0_3 F_(D3, IP5_27_24)
54 #define GPSR0_2 F_(D2, IP5_23_20)
55 #define GPSR0_1 F_(D1, IP5_19_16)
56 #define GPSR0_0 F_(D0, IP5_15_12)
57
58 /* GPSR1 */
59 #define GPSR1_28 FM(CLKOUT)
60 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
61 #define GPSR1_26 F_(WE1_N, IP5_7_4)
62 #define GPSR1_25 F_(WE0_N, IP5_3_0)
63 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
64 #define GPSR1_23 F_(RD_N, IP4_27_24)
65 #define GPSR1_22 F_(BS_N, IP4_23_20)
66 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
67 #define GPSR1_20 F_(CS0_N, IP4_15_12)
68 #define GPSR1_19 F_(A19, IP4_11_8)
69 #define GPSR1_18 F_(A18, IP4_7_4)
70 #define GPSR1_17 F_(A17, IP4_3_0)
71 #define GPSR1_16 F_(A16, IP3_31_28)
72 #define GPSR1_15 F_(A15, IP3_27_24)
73 #define GPSR1_14 F_(A14, IP3_23_20)
74 #define GPSR1_13 F_(A13, IP3_19_16)
75 #define GPSR1_12 F_(A12, IP3_15_12)
76 #define GPSR1_11 F_(A11, IP3_11_8)
77 #define GPSR1_10 F_(A10, IP3_7_4)
78 #define GPSR1_9 F_(A9, IP3_3_0)
79 #define GPSR1_8 F_(A8, IP2_31_28)
80 #define GPSR1_7 F_(A7, IP2_27_24)
81 #define GPSR1_6 F_(A6, IP2_23_20)
82 #define GPSR1_5 F_(A5, IP2_19_16)
83 #define GPSR1_4 F_(A4, IP2_15_12)
84 #define GPSR1_3 F_(A3, IP2_11_8)
85 #define GPSR1_2 F_(A2, IP2_7_4)
86 #define GPSR1_1 F_(A1, IP2_3_0)
87 #define GPSR1_0 F_(A0, IP1_31_28)
88
89 /* GPSR2 */
90 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
91 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
92 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
93 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
94 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
95 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
96 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
97 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
98 #define GPSR2_6 F_(PWM0, IP1_19_16)
99 #define GPSR2_5 F_(IRQ5, IP1_15_12)
100 #define GPSR2_4 F_(IRQ4, IP1_11_8)
101 #define GPSR2_3 F_(IRQ3, IP1_7_4)
102 #define GPSR2_2 F_(IRQ2, IP1_3_0)
103 #define GPSR2_1 F_(IRQ1, IP0_31_28)
104 #define GPSR2_0 F_(IRQ0, IP0_27_24)
105
106 /* GPSR3 */
107 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
108 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
109 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
110 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
111 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
112 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
113 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
114 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
115 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
116 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
117 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
118 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
119 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
120 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
121 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
122 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
123
124 /* GPSR4 */
125 #define GPSR4_17 F_(SD3_DS, IP11_11_8)
126 #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
127 #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
128 #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
129 #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
130 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
131 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
132 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
133 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
134 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
135 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
136 #define GPSR4_6 F_(SD2_DS, IP9_23_20)
137 #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
138 #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
139 #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
140 #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
141 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
142 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
143
144 /* GPSR5 */
145 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
146 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
147 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
148 #define GPSR5_22 FM(MSIOF0_RXD)
149 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
150 #define GPSR5_20 FM(MSIOF0_TXD)
151 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
152 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
153 #define GPSR5_17 FM(MSIOF0_SCK)
154 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
155 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
156 #define GPSR5_14 F_(HTX0, IP13_19_16)
157 #define GPSR5_13 F_(HRX0, IP13_15_12)
158 #define GPSR5_12 F_(HSCK0, IP13_11_8)
159 #define GPSR5_11 F_(RX2_A, IP13_7_4)
160 #define GPSR5_10 F_(TX2_A, IP13_3_0)
161 #define GPSR5_9 F_(SCK2, IP12_31_28)
162 #define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
163 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
164 #define GPSR5_6 F_(TX1_A, IP12_19_16)
165 #define GPSR5_5 F_(RX1_A, IP12_15_12)
166 #define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
167 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
168 #define GPSR5_2 F_(TX0, IP12_3_0)
169 #define GPSR5_1 F_(RX0, IP11_31_28)
170 #define GPSR5_0 F_(SCK0, IP11_27_24)
171
172 /* GPSR6 */
173 #define GPSR6_31 F_(GP6_31, IP18_7_4)
174 #define GPSR6_30 F_(GP6_30, IP18_3_0)
175 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
176 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
177 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
178 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
179 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
180 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
181 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
182 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
183 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
184 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
185 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
186 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
187 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
188 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
189 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
190 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
191 #define GPSR6_13 FM(SSI_SDATA5)
192 #define GPSR6_12 FM(SSI_WS5)
193 #define GPSR6_11 FM(SSI_SCK5)
194 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
195 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
196 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
197 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
198 #define GPSR6_6 F_(SSI_WS34, IP15_15_12)
199 #define GPSR6_5 F_(SSI_SCK34, IP15_11_8)
200 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
201 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
202 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
203 #define GPSR6_1 F_(SSI_WS0129, IP14_27_24)
204 #define GPSR6_0 F_(SSI_SCK0129, IP14_23_20)
205
206 /* GPSR7 */
207 #define GPSR7_3 FM(GP7_03)
208 #define GPSR7_2 FM(HDMI0_CEC)
209 #define GPSR7_1 FM(AVS2)
210 #define GPSR7_0 FM(AVS1)
211
212
213 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
214 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241
242 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
243 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272
273 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
274 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309
310 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
311 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) FM(FSO_TOE_A) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
332 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339
340 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
341 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
361 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
362 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
363 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
364 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
365 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) FM(FSO_CFE_0_A) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0)
367 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) FM(FSO_CFE_1_A) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0)
368
369 #define PINMUX_GPSR \
370 \
371 GPSR6_31 \
372 GPSR6_30 \
373 GPSR6_29 \
374 GPSR1_28 GPSR6_28 \
375 GPSR1_27 GPSR6_27 \
376 GPSR1_26 GPSR6_26 \
377 GPSR1_25 GPSR5_25 GPSR6_25 \
378 GPSR1_24 GPSR5_24 GPSR6_24 \
379 GPSR1_23 GPSR5_23 GPSR6_23 \
380 GPSR1_22 GPSR5_22 GPSR6_22 \
381 GPSR1_21 GPSR5_21 GPSR6_21 \
382 GPSR1_20 GPSR5_20 GPSR6_20 \
383 GPSR1_19 GPSR5_19 GPSR6_19 \
384 GPSR1_18 GPSR5_18 GPSR6_18 \
385 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
386 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
387 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
388 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
389 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
390 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
391 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
392 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
393 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
394 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
395 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
396 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
397 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
398 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
399 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
400 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
401 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
402 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
403
404 #define PINMUX_IPSR \
405 \
406 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
407 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
408 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
409 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
410 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
411 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
412 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
413 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
414 \
415 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
416 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
417 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
418 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
419 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
420 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
421 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
422 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
423 \
424 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
425 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
426 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
427 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
428 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
429 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
430 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
431 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
432 \
433 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
434 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
435 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
436 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
437 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
438 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
439 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
440 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
441 \
442 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
443 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
444 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
445 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
446 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
447 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
448 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
449 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
450
451 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
452 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
453 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
454 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
455 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
456 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
457 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
458 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
459 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
460 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
461 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
462 #define MOD_SEL0_15 FM(SEL_FSO_0) FM(SEL_FSO_1)
463 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
464 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
465 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
466 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
467 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
468 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
469 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
470 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
471 #define MOD_SEL0_2 FM(SEL_5LINE_0) FM(SEL_5LINE_1)
472
473 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
474 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
475 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
476 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
477 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
478 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
479 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
480 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
481 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
482 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
483 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
484 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
485 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
486 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
487 #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
488 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
489 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
490 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
491 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
492 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
493 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
494 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
495 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
496
497 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
498 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
499 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
500 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
501 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
502 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
503 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
504 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
505 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
506 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
507 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
508 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
509 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
510 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
511
512 #define PINMUX_MOD_SELS \
513 \
514 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
515 MOD_SEL2_30 \
516 MOD_SEL1_29_28_27 MOD_SEL2_29 \
517 MOD_SEL0_28_27 MOD_SEL2_28_27 \
518 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
519 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
520 MOD_SEL0_23 MOD_SEL1_23_22_21 \
521 MOD_SEL0_22 MOD_SEL2_22 \
522 MOD_SEL0_21 MOD_SEL2_21 \
523 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
524 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
525 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
526 MOD_SEL2_17 \
527 MOD_SEL0_16 MOD_SEL1_16 \
528 MOD_SEL0_15 MOD_SEL1_15_14 \
529 MOD_SEL0_14_13 \
530 MOD_SEL1_13 \
531 MOD_SEL0_12 MOD_SEL1_12 \
532 MOD_SEL0_11 MOD_SEL1_11 \
533 MOD_SEL0_10 MOD_SEL1_10 \
534 MOD_SEL0_9_8 MOD_SEL1_9 \
535 MOD_SEL0_7_6 \
536 MOD_SEL1_6 \
537 MOD_SEL0_5 MOD_SEL1_5 \
538 MOD_SEL0_4_3 MOD_SEL1_4 \
539 MOD_SEL1_3 \
540 MOD_SEL0_2 MOD_SEL1_2 \
541 MOD_SEL1_1 \
542 MOD_SEL1_0 MOD_SEL2_0
543
544 enum {
545 PINMUX_RESERVED = 0,
546
547 PINMUX_DATA_BEGIN,
548 GP_ALL(DATA),
549 PINMUX_DATA_END,
550
551 #define F_(x, y)
552 #define FM(x) FN_##x,
553 PINMUX_FUNCTION_BEGIN,
554 GP_ALL(FN),
555 PINMUX_GPSR
556 PINMUX_IPSR
557 PINMUX_MOD_SELS
558 PINMUX_FUNCTION_END,
559 #undef F_
560 #undef FM
561
562 #define F_(x, y)
563 #define FM(x) x##_MARK,
564 PINMUX_MARK_BEGIN,
565 PINMUX_GPSR
566 PINMUX_IPSR
567 PINMUX_MOD_SELS
568 PINMUX_MARK_END,
569 #undef F_
570 #undef FM
571 };
572
573 static const u16 pinmux_data[] = {
574 PINMUX_DATA_GP_ALL(),
575
576 PINMUX_SINGLE(AVS1),
577 PINMUX_SINGLE(AVS2),
578 PINMUX_SINGLE(CLKOUT),
579 PINMUX_SINGLE(GP7_03),
580 PINMUX_SINGLE(HDMI0_CEC),
581 PINMUX_SINGLE(MSIOF0_RXD),
582 PINMUX_SINGLE(MSIOF0_SCK),
583 PINMUX_SINGLE(MSIOF0_TXD),
584 PINMUX_SINGLE(SSI_SCK5),
585 PINMUX_SINGLE(SSI_SDATA5),
586 PINMUX_SINGLE(SSI_WS5),
587
588 /* IPSR0 */
589 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
590 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
591
592 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
593 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
594 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
595
596 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
597 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
598 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
599
600 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
601 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
602 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
603
604 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
605 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
606 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
607
608 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
609 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
610 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
611
612 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
613 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
614 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
615 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
616 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
617 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
618 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
619
620 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
621 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
622 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
623 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
624 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
625 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
626 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E, SEL_MSIOF3_4),
627
628 /* IPSR1 */
629 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
630 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
631 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
632 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
634 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
635
636 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
637 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
638 PINMUX_IPSR_GPSR(IP1_7_4, A25),
639 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
640 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
642 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
643
644 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
645 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
646 PINMUX_IPSR_GPSR(IP1_11_8, A24),
647 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
648 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
649 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
650 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
651
652 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
653 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
654 PINMUX_IPSR_GPSR(IP1_15_12, A23),
655 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
656 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
657 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
658 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
659
660 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
661 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
662 PINMUX_IPSR_GPSR(IP1_19_16, A22),
663 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
664 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
665
666 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
667 PINMUX_IPSR_GPSR(IP1_23_20, A21),
668 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
669 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
670 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
671
672 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
673 PINMUX_IPSR_GPSR(IP1_27_24, A20),
674 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
675 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
676
677 PINMUX_IPSR_GPSR(IP1_31_28, A0),
678 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
679 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
680 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
681 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
682 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
683
684 /* IPSR2 */
685 PINMUX_IPSR_GPSR(IP2_3_0, A1),
686 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
687 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
688 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
689 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
690 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
691
692 PINMUX_IPSR_GPSR(IP2_7_4, A2),
693 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
694 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
695 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
696 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
697 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
698
699 PINMUX_IPSR_GPSR(IP2_11_8, A3),
700 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
701 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
702 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
703 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
704 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
705
706 PINMUX_IPSR_GPSR(IP2_15_12, A4),
707 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
708 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
709 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
710 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
711 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
712
713 PINMUX_IPSR_GPSR(IP2_19_16, A5),
714 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
715 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
716 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
717 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
718 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
719 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
720
721 PINMUX_IPSR_GPSR(IP2_23_20, A6),
722 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
723 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
724 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
725 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
726 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
727 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
728
729 PINMUX_IPSR_GPSR(IP2_27_24, A7),
730 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
731 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
732 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
733 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
734 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
735 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
736
737 PINMUX_IPSR_GPSR(IP2_31_28, A8),
738 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
739 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
740 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
741 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
742 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
743 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
744
745 /* IPSR3 */
746 PINMUX_IPSR_GPSR(IP3_3_0, A9),
747 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
749 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
750
751 PINMUX_IPSR_GPSR(IP3_7_4, A10),
752 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
753 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
754 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
755
756 PINMUX_IPSR_GPSR(IP3_11_8, A11),
757 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
758 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
759 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
760 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
761 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
762 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
763 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
764 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
765
766 PINMUX_IPSR_GPSR(IP3_15_12, A12),
767 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
768 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
769 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
770 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
771 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
772
773 PINMUX_IPSR_GPSR(IP3_19_16, A13),
774 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
775 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
776 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
777 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
778 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
779
780 PINMUX_IPSR_GPSR(IP3_23_20, A14),
781 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
782 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
783 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
784 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
785 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
786
787 PINMUX_IPSR_GPSR(IP3_27_24, A15),
788 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
789 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
790 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
791 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
792 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
793
794 PINMUX_IPSR_GPSR(IP3_31_28, A16),
795 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
796 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
797 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
798
799 /* IPSR4 */
800 PINMUX_IPSR_GPSR(IP4_3_0, A17),
801 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
802 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
803 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
804
805 PINMUX_IPSR_GPSR(IP4_7_4, A18),
806 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
807 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
808 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
809
810 PINMUX_IPSR_GPSR(IP4_11_8, A19),
811 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
812 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
813 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
814
815 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
816 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
817
818 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
819 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
820 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
821
822 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
823 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
824 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
825 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
826 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
827 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
828 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
829 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
830
831 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
832 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
833 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
834 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
835 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
836 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
837
838 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
839 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
840 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
841 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
842 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
843 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
844
845 /* IPSR5 */
846 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
847 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
848 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
849 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
850 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
851 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
852 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
853
854 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
855 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
856 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
857 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
858 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
859 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
860 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
861 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
862
863 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
864 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
865 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
866 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
867
868 PINMUX_IPSR_GPSR(IP5_15_12, D0),
869 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
870 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
871 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
872 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
873
874 PINMUX_IPSR_GPSR(IP5_19_16, D1),
875 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
876 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
877 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
878 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
879
880 PINMUX_IPSR_GPSR(IP5_23_20, D2),
881 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
882 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
883 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
884
885 PINMUX_IPSR_GPSR(IP5_27_24, D3),
886 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
887 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
888 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
889
890 PINMUX_IPSR_GPSR(IP5_31_28, D4),
891 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
893 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
894
895 /* IPSR6 */
896 PINMUX_IPSR_GPSR(IP6_3_0, D5),
897 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
898 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
899 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
900
901 PINMUX_IPSR_GPSR(IP6_7_4, D6),
902 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
903 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
904 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
905
906 PINMUX_IPSR_GPSR(IP6_11_8, D7),
907 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
908 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
909 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
910
911 PINMUX_IPSR_GPSR(IP6_15_12, D8),
912 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
913 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
914 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
915 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
916 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
917
918 PINMUX_IPSR_GPSR(IP6_19_16, D9),
919 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
920 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
921 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
922 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
923
924 PINMUX_IPSR_GPSR(IP6_23_20, D10),
925 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
926 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
927 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
928 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
929 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
930 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
931
932 PINMUX_IPSR_GPSR(IP6_27_24, D11),
933 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
934 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
935 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
936 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
937 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
938 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
939
940 PINMUX_IPSR_GPSR(IP6_31_28, D12),
941 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
942 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
943 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
944 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
945 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
946
947 /* IPSR7 */
948 PINMUX_IPSR_GPSR(IP7_3_0, D13),
949 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
950 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
952 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
953 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
954
955 PINMUX_IPSR_GPSR(IP7_7_4, D14),
956 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
957 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
958 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
959 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
960 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
961 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
962
963 PINMUX_IPSR_GPSR(IP7_11_8, D15),
964 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
965 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
966 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
967 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
968 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
969 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
970
971 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
972
973 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
974 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
975 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
976
977 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
978 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
979 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
980
981 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
982 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
983 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
984 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
985
986 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
987 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
988 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
989 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
990
991 /* IPSR8 */
992 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
993 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
994 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
995 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
996
997 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
998 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
999 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1000 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1001
1002 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1003 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1004 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1005
1006 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1007 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1008 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1009 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1010 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1011
1012 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1013 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1014 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1015 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1016 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1017 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1018
1019 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1020 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1021 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1022 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1023 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1024 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1025
1026 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1027 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1028 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1029 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1030 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1031 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1032
1033 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1034 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1035 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1036 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1037 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1038 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1039
1040 /* IPSR9 */
1041 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1042 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1043
1044 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1045 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1046
1047 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1048 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1049
1050 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1051 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1052
1053 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1054 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1055
1056 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1057 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1058
1059 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1060 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1061
1062 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1063 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1064
1065 /* IPSR10 */
1066 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1067 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1068
1069 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1070 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1071
1072 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1073 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1074
1075 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1076 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1077
1078 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1079 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1080
1081 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1082 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1083 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1084
1085 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1086 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1087 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1088
1089 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1090 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1091 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1092
1093 /* IPSR11 */
1094 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1095 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1096 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1097
1098 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1099 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1100
1101 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1102 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1103 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1104
1105 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1106 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1107
1108 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1109 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1110
1111 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1112 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1113
1114 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1115 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1116 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1117 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1118 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1119 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1120 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1121 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1122 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1123 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1124
1125 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1126 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1127 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1128 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1129 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1130
1131 /* IPSR12 */
1132 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1133 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1134 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1135 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1136 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1137
1138 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1139 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1140 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1141 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1142 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1143 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1144 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1145 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1146
1147 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1148 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1149 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1150 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1151 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1152 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1153 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1154 PINMUX_IPSR_MSEL(IP12_11_8, FSO_TOE_A, SEL_FSO_0),
1155 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1156
1157 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1158 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1159 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1160 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1161 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1162
1163 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1164 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1165 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1166 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1167 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1168
1169 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1170 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1171 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1172 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1173 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1174 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1175 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1176
1177 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1178 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1180 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1181 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1182 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1183 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1184
1185 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1186 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1187 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1188 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1189 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1190 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1191 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1192
1193 /* IPSR13 */
1194 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1195 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1196 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1197 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1198 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1199 PINMUX_IPSR_MSEL(IP13_3_0, FSO_CFE_0_B, SEL_FSO_1),
1200
1201 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1202 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1203 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1204 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1205 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1206 PINMUX_IPSR_MSEL(IP13_7_4, FSO_CFE_1_B, SEL_FSO_1),
1207
1208 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1209 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1210 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1211 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1212 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1213 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1214 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1215 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1216
1217 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1218 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1219 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1220 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1221 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1222 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1223
1224 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1225 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1226 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1227 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1228 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1229 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1230
1231 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1232 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1233 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1234 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1235 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1236 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1237 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1238 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1239
1240 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1241 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1242 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1243 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1244 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1245 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1246 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1247
1248 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1249 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1250 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1251 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1252
1253 /* IPSR14 */
1254 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1255 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1256 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1257 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1258 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1259 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1260 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1261 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1262
1263 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1264 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1265 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1266 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1267 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1268 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1269 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1270 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1271
1272 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1273 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1274 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1275
1276 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1277 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1278 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1279 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1280
1281 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1282 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1283 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1284
1285 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK0129),
1286 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1287
1288 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS0129),
1289 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1290
1291 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1292 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1293
1294 /* IPSR15 */
1295 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1296
1297 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1298 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1299
1300 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK34),
1301 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1302 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1303
1304 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS34),
1305 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1306 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1307 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1308
1309 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1310 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1311 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1312 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1313 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1314 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1315 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1316
1317 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1318 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1319 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1320 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1321 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1322 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1323 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1324
1325 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1326 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1327 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1328 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1330 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1332
1333 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1334 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1335 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1336 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1338 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1340
1341 /* IPSR16 */
1342 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1343 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1344
1345 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1346 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1347
1348 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1349 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1350
1351 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1352 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1353 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1354 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1355 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1356 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1357 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1358
1359 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1360 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1361 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1362 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1363 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1364 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1365 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1366
1367 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1368 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1369 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1370 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1371 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1372 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1373 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1374 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1375
1376 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1377 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1378 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1379 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1380 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1381 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1383
1384 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1385 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1386 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1387 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1388 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1389 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1390 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1391 PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A),
1392
1393 /* IPSR17 */
1394 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1395 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1396
1397 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1398 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1399 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1400 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1401 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1402
1403 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1404 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1405 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1406 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1407 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1408 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1409 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1410
1411 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1412 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1413 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1414 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1415 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1416 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1417
1418 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1419 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1420 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1421 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1422 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1423 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1424 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1425 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1426 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1427
1428 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1429 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1430 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1431 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1432 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1433 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1434 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1435 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1436 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1437
1438 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1439 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1440 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1441 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1442 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1443 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1444 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1445 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1446 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1447 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1448 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1449
1450 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1451 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1452 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1453 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1454 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1455 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1456 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1457 PINMUX_IPSR_MSEL(IP17_31_28, FSO_TOE_B, SEL_FSO_1),
1458 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1459
1460 /* IPSR18 */
1461 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1462 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1463 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1464 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1465 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1466 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1467 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1468 PINMUX_IPSR_MSEL(IP18_3_0, FSO_CFE_0_A, SEL_FSO_0),
1469 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1470 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1471
1472 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1473 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1474 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1475 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1476 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1477 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1478 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1479 PINMUX_IPSR_MSEL(IP18_7_4, FSO_CFE_1_A, SEL_FSO_0),
1480 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1481 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1482
1483 /* I2C */
1484 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1485 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1486 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1487 };
1488
1489 static const struct sh_pfc_pin pinmux_pins[] = {
1490 PINMUX_GPIO_GP_ALL(),
1491 };
1492
1493 /* - SCIF0 ------------------------------------------------------------------ */
1494 static const unsigned int scif0_data_pins[] = {
1495 /* RX, TX */
1496 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1497 };
1498 static const unsigned int scif0_data_mux[] = {
1499 RX0_MARK, TX0_MARK,
1500 };
1501 static const unsigned int scif0_clk_pins[] = {
1502 /* SCK */
1503 RCAR_GP_PIN(5, 0),
1504 };
1505 static const unsigned int scif0_clk_mux[] = {
1506 SCK0_MARK,
1507 };
1508 static const unsigned int scif0_ctrl_pins[] = {
1509 /* RTS, CTS */
1510 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1511 };
1512 static const unsigned int scif0_ctrl_mux[] = {
1513 RTS0_N_TANS_MARK, CTS0_N_MARK,
1514 };
1515 /* - SCIF1 ------------------------------------------------------------------ */
1516 static const unsigned int scif1_data_a_pins[] = {
1517 /* RX, TX */
1518 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1519 };
1520 static const unsigned int scif1_data_a_mux[] = {
1521 RX1_A_MARK, TX1_A_MARK,
1522 };
1523 static const unsigned int scif1_clk_pins[] = {
1524 /* SCK */
1525 RCAR_GP_PIN(6, 21),
1526 };
1527 static const unsigned int scif1_clk_mux[] = {
1528 SCK1_MARK,
1529 };
1530 static const unsigned int scif1_ctrl_pins[] = {
1531 /* RTS, CTS */
1532 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1533 };
1534 static const unsigned int scif1_ctrl_mux[] = {
1535 RTS1_N_TANS_MARK, CTS1_N_MARK,
1536 };
1537
1538 static const unsigned int scif1_data_b_pins[] = {
1539 /* RX, TX */
1540 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1541 };
1542 static const unsigned int scif1_data_b_mux[] = {
1543 RX1_B_MARK, TX1_B_MARK,
1544 };
1545 /* - SCIF2 ------------------------------------------------------------------ */
1546 static const unsigned int scif2_data_a_pins[] = {
1547 /* RX, TX */
1548 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1549 };
1550 static const unsigned int scif2_data_a_mux[] = {
1551 RX2_A_MARK, TX2_A_MARK,
1552 };
1553 static const unsigned int scif2_clk_pins[] = {
1554 /* SCK */
1555 RCAR_GP_PIN(5, 9),
1556 };
1557 static const unsigned int scif2_clk_mux[] = {
1558 SCK2_MARK,
1559 };
1560 static const unsigned int scif2_data_b_pins[] = {
1561 /* RX, TX */
1562 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1563 };
1564 static const unsigned int scif2_data_b_mux[] = {
1565 RX2_B_MARK, TX2_B_MARK,
1566 };
1567 /* - SCIF3 ------------------------------------------------------------------ */
1568 static const unsigned int scif3_data_a_pins[] = {
1569 /* RX, TX */
1570 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1571 };
1572 static const unsigned int scif3_data_a_mux[] = {
1573 RX3_A_MARK, TX3_A_MARK,
1574 };
1575 static const unsigned int scif3_clk_pins[] = {
1576 /* SCK */
1577 RCAR_GP_PIN(1, 22),
1578 };
1579 static const unsigned int scif3_clk_mux[] = {
1580 SCK3_MARK,
1581 };
1582 static const unsigned int scif3_ctrl_pins[] = {
1583 /* RTS, CTS */
1584 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1585 };
1586 static const unsigned int scif3_ctrl_mux[] = {
1587 RTS3_N_TANS_MARK, CTS3_N_MARK,
1588 };
1589 static const unsigned int scif3_data_b_pins[] = {
1590 /* RX, TX */
1591 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1592 };
1593 static const unsigned int scif3_data_b_mux[] = {
1594 RX3_B_MARK, TX3_B_MARK,
1595 };
1596 /* - SCIF4 ------------------------------------------------------------------ */
1597 static const unsigned int scif4_data_a_pins[] = {
1598 /* RX, TX */
1599 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1600 };
1601 static const unsigned int scif4_data_a_mux[] = {
1602 RX4_A_MARK, TX4_A_MARK,
1603 };
1604 static const unsigned int scif4_clk_a_pins[] = {
1605 /* SCK */
1606 RCAR_GP_PIN(2, 10),
1607 };
1608 static const unsigned int scif4_clk_a_mux[] = {
1609 SCK4_A_MARK,
1610 };
1611 static const unsigned int scif4_ctrl_a_pins[] = {
1612 /* RTS, CTS */
1613 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1614 };
1615 static const unsigned int scif4_ctrl_a_mux[] = {
1616 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
1617 };
1618 static const unsigned int scif4_data_b_pins[] = {
1619 /* RX, TX */
1620 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1621 };
1622 static const unsigned int scif4_data_b_mux[] = {
1623 RX4_B_MARK, TX4_B_MARK,
1624 };
1625 static const unsigned int scif4_clk_b_pins[] = {
1626 /* SCK */
1627 RCAR_GP_PIN(1, 5),
1628 };
1629 static const unsigned int scif4_clk_b_mux[] = {
1630 SCK4_B_MARK,
1631 };
1632 static const unsigned int scif4_ctrl_b_pins[] = {
1633 /* RTS, CTS */
1634 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1635 };
1636 static const unsigned int scif4_ctrl_b_mux[] = {
1637 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
1638 };
1639 static const unsigned int scif4_data_c_pins[] = {
1640 /* RX, TX */
1641 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1642 };
1643 static const unsigned int scif4_data_c_mux[] = {
1644 RX4_C_MARK, TX4_C_MARK,
1645 };
1646 static const unsigned int scif4_clk_c_pins[] = {
1647 /* SCK */
1648 RCAR_GP_PIN(0, 8),
1649 };
1650 static const unsigned int scif4_clk_c_mux[] = {
1651 SCK4_C_MARK,
1652 };
1653 static const unsigned int scif4_ctrl_c_pins[] = {
1654 /* RTS, CTS */
1655 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1656 };
1657 static const unsigned int scif4_ctrl_c_mux[] = {
1658 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
1659 };
1660 /* - SCIF5 ------------------------------------------------------------------ */
1661 static const unsigned int scif5_data_a_pins[] = {
1662 /* RX, TX */
1663 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
1664 };
1665 static const unsigned int scif5_data_a_mux[] = {
1666 RX5_A_MARK, TX5_A_MARK,
1667 };
1668 static const unsigned int scif5_clk_a_pins[] = {
1669 /* SCK */
1670 RCAR_GP_PIN(6, 21),
1671 };
1672 static const unsigned int scif5_clk_a_mux[] = {
1673 SCK5_A_MARK,
1674 };
1675
1676 static const unsigned int scif5_data_b_pins[] = {
1677 /* RX, TX */
1678 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
1679 };
1680 static const unsigned int scif5_data_b_mux[] = {
1681 RX5_B_MARK, TX5_B_MARK,
1682 };
1683 static const unsigned int scif5_clk_b_pins[] = {
1684 /* SCK */
1685 RCAR_GP_PIN(5, 0),
1686 };
1687 static const unsigned int scif5_clk_b_mux[] = {
1688 SCK5_B_MARK,
1689 };
1690
1691 /* - SCIF Clock ------------------------------------------------------------- */
1692 static const unsigned int scif_clk_a_pins[] = {
1693 /* SCIF_CLK */
1694 RCAR_GP_PIN(6, 23),
1695 };
1696 static const unsigned int scif_clk_a_mux[] = {
1697 SCIF_CLK_A_MARK,
1698 };
1699 static const unsigned int scif_clk_b_pins[] = {
1700 /* SCIF_CLK */
1701 RCAR_GP_PIN(5, 9),
1702 };
1703 static const unsigned int scif_clk_b_mux[] = {
1704 SCIF_CLK_B_MARK,
1705 };
1706
1707 /* - SDHI0 ------------------------------------------------------------------ */
1708 static const unsigned int sdhi0_data1_pins[] = {
1709 /* D0 */
1710 RCAR_GP_PIN(3, 2),
1711 };
1712 static const unsigned int sdhi0_data1_mux[] = {
1713 SD0_DAT0_MARK,
1714 };
1715 static const unsigned int sdhi0_data4_pins[] = {
1716 /* D[0:3] */
1717 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1718 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1719 };
1720 static const unsigned int sdhi0_data4_mux[] = {
1721 SD0_DAT0_MARK, SD0_DAT1_MARK,
1722 SD0_DAT2_MARK, SD0_DAT3_MARK,
1723 };
1724 static const unsigned int sdhi0_ctrl_pins[] = {
1725 /* CLK, CMD */
1726 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1727 };
1728 static const unsigned int sdhi0_ctrl_mux[] = {
1729 SD0_CLK_MARK, SD0_CMD_MARK,
1730 };
1731 static const unsigned int sdhi0_cd_pins[] = {
1732 /* CD */
1733 RCAR_GP_PIN(3, 12),
1734 };
1735 static const unsigned int sdhi0_cd_mux[] = {
1736 SD0_CD_MARK,
1737 };
1738 static const unsigned int sdhi0_wp_pins[] = {
1739 /* WP */
1740 RCAR_GP_PIN(3, 13),
1741 };
1742 static const unsigned int sdhi0_wp_mux[] = {
1743 SD0_WP_MARK,
1744 };
1745 /* - SDHI1 ------------------------------------------------------------------ */
1746 static const unsigned int sdhi1_data1_pins[] = {
1747 /* D0 */
1748 RCAR_GP_PIN(3, 8),
1749 };
1750 static const unsigned int sdhi1_data1_mux[] = {
1751 SD1_DAT0_MARK,
1752 };
1753 static const unsigned int sdhi1_data4_pins[] = {
1754 /* D[0:3] */
1755 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1756 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1757 };
1758 static const unsigned int sdhi1_data4_mux[] = {
1759 SD1_DAT0_MARK, SD1_DAT1_MARK,
1760 SD1_DAT2_MARK, SD1_DAT3_MARK,
1761 };
1762 static const unsigned int sdhi1_ctrl_pins[] = {
1763 /* CLK, CMD */
1764 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1765 };
1766 static const unsigned int sdhi1_ctrl_mux[] = {
1767 SD1_CLK_MARK, SD1_CMD_MARK,
1768 };
1769 static const unsigned int sdhi1_cd_pins[] = {
1770 /* CD */
1771 RCAR_GP_PIN(3, 14),
1772 };
1773 static const unsigned int sdhi1_cd_mux[] = {
1774 SD1_CD_MARK,
1775 };
1776 static const unsigned int sdhi1_wp_pins[] = {
1777 /* WP */
1778 RCAR_GP_PIN(3, 15),
1779 };
1780 static const unsigned int sdhi1_wp_mux[] = {
1781 SD1_WP_MARK,
1782 };
1783 /* - SDHI2 ------------------------------------------------------------------ */
1784 static const unsigned int sdhi2_data1_pins[] = {
1785 /* D0 */
1786 RCAR_GP_PIN(4, 2),
1787 };
1788 static const unsigned int sdhi2_data1_mux[] = {
1789 SD2_DAT0_MARK,
1790 };
1791 static const unsigned int sdhi2_data4_pins[] = {
1792 /* D[0:3] */
1793 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1794 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1795 };
1796 static const unsigned int sdhi2_data4_mux[] = {
1797 SD2_DAT0_MARK, SD2_DAT1_MARK,
1798 SD2_DAT2_MARK, SD2_DAT3_MARK,
1799 };
1800 static const unsigned int sdhi2_data8_pins[] = {
1801 /* D[0:7] */
1802 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1803 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1804 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1805 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1806 };
1807 static const unsigned int sdhi2_data8_mux[] = {
1808 SD2_DAT0_MARK, SD2_DAT1_MARK,
1809 SD2_DAT2_MARK, SD2_DAT3_MARK,
1810 SD2_DAT4_MARK, SD2_DAT5_MARK,
1811 SD2_DAT6_MARK, SD2_DAT7_MARK,
1812 };
1813 static const unsigned int sdhi2_ctrl_pins[] = {
1814 /* CLK, CMD */
1815 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1816 };
1817 static const unsigned int sdhi2_ctrl_mux[] = {
1818 SD2_CLK_MARK, SD2_CMD_MARK,
1819 };
1820 static const unsigned int sdhi2_cd_a_pins[] = {
1821 /* CD */
1822 RCAR_GP_PIN(4, 13),
1823 };
1824 static const unsigned int sdhi2_cd_a_mux[] = {
1825 SD2_CD_A_MARK,
1826 };
1827 static const unsigned int sdhi2_cd_b_pins[] = {
1828 /* CD */
1829 RCAR_GP_PIN(5, 10),
1830 };
1831 static const unsigned int sdhi2_cd_b_mux[] = {
1832 SD2_CD_B_MARK,
1833 };
1834 static const unsigned int sdhi2_wp_a_pins[] = {
1835 /* WP */
1836 RCAR_GP_PIN(4, 14),
1837 };
1838 static const unsigned int sdhi2_wp_a_mux[] = {
1839 SD2_WP_A_MARK,
1840 };
1841 static const unsigned int sdhi2_wp_b_pins[] = {
1842 /* WP */
1843 RCAR_GP_PIN(5, 11),
1844 };
1845 static const unsigned int sdhi2_wp_b_mux[] = {
1846 SD2_WP_B_MARK,
1847 };
1848 static const unsigned int sdhi2_ds_pins[] = {
1849 /* DS */
1850 RCAR_GP_PIN(4, 6),
1851 };
1852 static const unsigned int sdhi2_ds_mux[] = {
1853 SD2_DS_MARK,
1854 };
1855 /* - SDHI3 ------------------------------------------------------------------ */
1856 static const unsigned int sdhi3_data1_pins[] = {
1857 /* D0 */
1858 RCAR_GP_PIN(4, 9),
1859 };
1860 static const unsigned int sdhi3_data1_mux[] = {
1861 SD3_DAT0_MARK,
1862 };
1863 static const unsigned int sdhi3_data4_pins[] = {
1864 /* D[0:3] */
1865 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
1866 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
1867 };
1868 static const unsigned int sdhi3_data4_mux[] = {
1869 SD3_DAT0_MARK, SD3_DAT1_MARK,
1870 SD3_DAT2_MARK, SD3_DAT3_MARK,
1871 };
1872 static const unsigned int sdhi3_data8_pins[] = {
1873 /* D[0:7] */
1874 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
1875 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
1876 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1877 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
1878 };
1879 static const unsigned int sdhi3_data8_mux[] = {
1880 SD3_DAT0_MARK, SD3_DAT1_MARK,
1881 SD3_DAT2_MARK, SD3_DAT3_MARK,
1882 SD3_DAT4_MARK, SD3_DAT5_MARK,
1883 SD3_DAT6_MARK, SD3_DAT7_MARK,
1884 };
1885 static const unsigned int sdhi3_ctrl_pins[] = {
1886 /* CLK, CMD */
1887 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
1888 };
1889 static const unsigned int sdhi3_ctrl_mux[] = {
1890 SD3_CLK_MARK, SD3_CMD_MARK,
1891 };
1892 static const unsigned int sdhi3_cd_pins[] = {
1893 /* CD */
1894 RCAR_GP_PIN(4, 15),
1895 };
1896 static const unsigned int sdhi3_cd_mux[] = {
1897 SD3_CD_MARK,
1898 };
1899 static const unsigned int sdhi3_wp_pins[] = {
1900 /* WP */
1901 RCAR_GP_PIN(4, 16),
1902 };
1903 static const unsigned int sdhi3_wp_mux[] = {
1904 SD3_WP_MARK,
1905 };
1906 static const unsigned int sdhi3_ds_pins[] = {
1907 /* DS */
1908 RCAR_GP_PIN(4, 17),
1909 };
1910 static const unsigned int sdhi3_ds_mux[] = {
1911 SD3_DS_MARK,
1912 };
1913
1914 static const struct sh_pfc_pin_group pinmux_groups[] = {
1915 SH_PFC_PIN_GROUP(scif0_data),
1916 SH_PFC_PIN_GROUP(scif0_clk),
1917 SH_PFC_PIN_GROUP(scif0_ctrl),
1918 SH_PFC_PIN_GROUP(scif1_data_a),
1919 SH_PFC_PIN_GROUP(scif1_clk),
1920 SH_PFC_PIN_GROUP(scif1_ctrl),
1921 SH_PFC_PIN_GROUP(scif1_data_b),
1922 SH_PFC_PIN_GROUP(scif2_data_a),
1923 SH_PFC_PIN_GROUP(scif2_clk),
1924 SH_PFC_PIN_GROUP(scif2_data_b),
1925 SH_PFC_PIN_GROUP(scif3_data_a),
1926 SH_PFC_PIN_GROUP(scif3_clk),
1927 SH_PFC_PIN_GROUP(scif3_ctrl),
1928 SH_PFC_PIN_GROUP(scif3_data_b),
1929 SH_PFC_PIN_GROUP(scif4_data_a),
1930 SH_PFC_PIN_GROUP(scif4_clk_a),
1931 SH_PFC_PIN_GROUP(scif4_ctrl_a),
1932 SH_PFC_PIN_GROUP(scif4_data_b),
1933 SH_PFC_PIN_GROUP(scif4_clk_b),
1934 SH_PFC_PIN_GROUP(scif4_ctrl_b),
1935 SH_PFC_PIN_GROUP(scif4_data_c),
1936 SH_PFC_PIN_GROUP(scif4_clk_c),
1937 SH_PFC_PIN_GROUP(scif4_ctrl_c),
1938 SH_PFC_PIN_GROUP(scif5_data_a),
1939 SH_PFC_PIN_GROUP(scif5_clk_a),
1940 SH_PFC_PIN_GROUP(scif5_data_b),
1941 SH_PFC_PIN_GROUP(scif5_clk_b),
1942 SH_PFC_PIN_GROUP(scif_clk_a),
1943 SH_PFC_PIN_GROUP(scif_clk_b),
1944 SH_PFC_PIN_GROUP(sdhi0_data1),
1945 SH_PFC_PIN_GROUP(sdhi0_data4),
1946 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1947 SH_PFC_PIN_GROUP(sdhi0_cd),
1948 SH_PFC_PIN_GROUP(sdhi0_wp),
1949 SH_PFC_PIN_GROUP(sdhi1_data1),
1950 SH_PFC_PIN_GROUP(sdhi1_data4),
1951 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1952 SH_PFC_PIN_GROUP(sdhi1_cd),
1953 SH_PFC_PIN_GROUP(sdhi1_wp),
1954 SH_PFC_PIN_GROUP(sdhi2_data1),
1955 SH_PFC_PIN_GROUP(sdhi2_data4),
1956 SH_PFC_PIN_GROUP(sdhi2_data8),
1957 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1958 SH_PFC_PIN_GROUP(sdhi2_cd_a),
1959 SH_PFC_PIN_GROUP(sdhi2_wp_a),
1960 SH_PFC_PIN_GROUP(sdhi2_cd_b),
1961 SH_PFC_PIN_GROUP(sdhi2_wp_b),
1962 SH_PFC_PIN_GROUP(sdhi2_ds),
1963 SH_PFC_PIN_GROUP(sdhi3_data1),
1964 SH_PFC_PIN_GROUP(sdhi3_data4),
1965 SH_PFC_PIN_GROUP(sdhi3_data8),
1966 SH_PFC_PIN_GROUP(sdhi3_ctrl),
1967 SH_PFC_PIN_GROUP(sdhi3_cd),
1968 SH_PFC_PIN_GROUP(sdhi3_wp),
1969 SH_PFC_PIN_GROUP(sdhi3_ds),
1970 };
1971
1972 static const char * const scif0_groups[] = {
1973 "scif0_data",
1974 "scif0_clk",
1975 "scif0_ctrl",
1976 };
1977
1978 static const char * const scif1_groups[] = {
1979 "scif1_data_a",
1980 "scif1_clk",
1981 "scif1_ctrl",
1982 "scif1_data_b",
1983 };
1984
1985 static const char * const scif2_groups[] = {
1986 "scif2_data_a",
1987 "scif2_clk",
1988 "scif2_data_b",
1989 };
1990
1991 static const char * const scif3_groups[] = {
1992 "scif3_data_a",
1993 "scif3_clk",
1994 "scif3_ctrl",
1995 "scif3_data_b",
1996 };
1997
1998 static const char * const scif4_groups[] = {
1999 "scif4_data_a",
2000 "scif4_clk_a",
2001 "scif4_ctrl_a",
2002 "scif4_data_b",
2003 "scif4_clk_b",
2004 "scif4_ctrl_b",
2005 "scif4_data_c",
2006 "scif4_clk_c",
2007 "scif4_ctrl_c",
2008 };
2009
2010 static const char * const scif5_groups[] = {
2011 "scif5_data_a",
2012 "scif5_clk_a",
2013 "scif5_data_b",
2014 "scif5_clk_b",
2015 };
2016
2017 static const char * const scif_clk_groups[] = {
2018 "scif_clk_a",
2019 "scif_clk_b",
2020 };
2021
2022 static const char * const sdhi0_groups[] = {
2023 "sdhi0_data1",
2024 "sdhi0_data4",
2025 "sdhi0_ctrl",
2026 "sdhi0_cd",
2027 "sdhi0_wp",
2028 };
2029
2030 static const char * const sdhi1_groups[] = {
2031 "sdhi1_data1",
2032 "sdhi1_data4",
2033 "sdhi1_ctrl",
2034 "sdhi1_cd",
2035 "sdhi1_wp",
2036 };
2037
2038 static const char * const sdhi2_groups[] = {
2039 "sdhi2_data1",
2040 "sdhi2_data4",
2041 "sdhi2_data8",
2042 "sdhi2_ctrl",
2043 "sdhi2_cd_a",
2044 "sdhi2_wp_a",
2045 "sdhi2_cd_b",
2046 "sdhi2_wp_b",
2047 "sdhi2_ds",
2048 };
2049
2050 static const char * const sdhi3_groups[] = {
2051 "sdhi3_data1",
2052 "sdhi3_data4",
2053 "sdhi3_data8",
2054 "sdhi3_ctrl",
2055 "sdhi3_cd",
2056 "sdhi3_wp",
2057 "sdhi3_ds",
2058 };
2059
2060 static const struct sh_pfc_function pinmux_functions[] = {
2061 SH_PFC_FUNCTION(scif0),
2062 SH_PFC_FUNCTION(scif1),
2063 SH_PFC_FUNCTION(scif2),
2064 SH_PFC_FUNCTION(scif3),
2065 SH_PFC_FUNCTION(scif4),
2066 SH_PFC_FUNCTION(scif5),
2067 SH_PFC_FUNCTION(scif_clk),
2068 SH_PFC_FUNCTION(sdhi0),
2069 SH_PFC_FUNCTION(sdhi1),
2070 SH_PFC_FUNCTION(sdhi2),
2071 SH_PFC_FUNCTION(sdhi3),
2072 };
2073
2074 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2075 #define F_(x, y) FN_##y
2076 #define FM(x) FN_##x
2077 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2078 0, 0,
2079 0, 0,
2080 0, 0,
2081 0, 0,
2082 0, 0,
2083 0, 0,
2084 0, 0,
2085 0, 0,
2086 0, 0,
2087 0, 0,
2088 0, 0,
2089 0, 0,
2090 0, 0,
2091 0, 0,
2092 0, 0,
2093 0, 0,
2094 GP_0_15_FN, GPSR0_15,
2095 GP_0_14_FN, GPSR0_14,
2096 GP_0_13_FN, GPSR0_13,
2097 GP_0_12_FN, GPSR0_12,
2098 GP_0_11_FN, GPSR0_11,
2099 GP_0_10_FN, GPSR0_10,
2100 GP_0_9_FN, GPSR0_9,
2101 GP_0_8_FN, GPSR0_8,
2102 GP_0_7_FN, GPSR0_7,
2103 GP_0_6_FN, GPSR0_6,
2104 GP_0_5_FN, GPSR0_5,
2105 GP_0_4_FN, GPSR0_4,
2106 GP_0_3_FN, GPSR0_3,
2107 GP_0_2_FN, GPSR0_2,
2108 GP_0_1_FN, GPSR0_1,
2109 GP_0_0_FN, GPSR0_0, }
2110 },
2111 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2112 0, 0,
2113 0, 0,
2114 0, 0,
2115 GP_1_28_FN, GPSR1_28,
2116 GP_1_27_FN, GPSR1_27,
2117 GP_1_26_FN, GPSR1_26,
2118 GP_1_25_FN, GPSR1_25,
2119 GP_1_24_FN, GPSR1_24,
2120 GP_1_23_FN, GPSR1_23,
2121 GP_1_22_FN, GPSR1_22,
2122 GP_1_21_FN, GPSR1_21,
2123 GP_1_20_FN, GPSR1_20,
2124 GP_1_19_FN, GPSR1_19,
2125 GP_1_18_FN, GPSR1_18,
2126 GP_1_17_FN, GPSR1_17,
2127 GP_1_16_FN, GPSR1_16,
2128 GP_1_15_FN, GPSR1_15,
2129 GP_1_14_FN, GPSR1_14,
2130 GP_1_13_FN, GPSR1_13,
2131 GP_1_12_FN, GPSR1_12,
2132 GP_1_11_FN, GPSR1_11,
2133 GP_1_10_FN, GPSR1_10,
2134 GP_1_9_FN, GPSR1_9,
2135 GP_1_8_FN, GPSR1_8,
2136 GP_1_7_FN, GPSR1_7,
2137 GP_1_6_FN, GPSR1_6,
2138 GP_1_5_FN, GPSR1_5,
2139 GP_1_4_FN, GPSR1_4,
2140 GP_1_3_FN, GPSR1_3,
2141 GP_1_2_FN, GPSR1_2,
2142 GP_1_1_FN, GPSR1_1,
2143 GP_1_0_FN, GPSR1_0, }
2144 },
2145 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2146 0, 0,
2147 0, 0,
2148 0, 0,
2149 0, 0,
2150 0, 0,
2151 0, 0,
2152 0, 0,
2153 0, 0,
2154 0, 0,
2155 0, 0,
2156 0, 0,
2157 0, 0,
2158 0, 0,
2159 0, 0,
2160 0, 0,
2161 0, 0,
2162 0, 0,
2163 GP_2_14_FN, GPSR2_14,
2164 GP_2_13_FN, GPSR2_13,
2165 GP_2_12_FN, GPSR2_12,
2166 GP_2_11_FN, GPSR2_11,
2167 GP_2_10_FN, GPSR2_10,
2168 GP_2_9_FN, GPSR2_9,
2169 GP_2_8_FN, GPSR2_8,
2170 GP_2_7_FN, GPSR2_7,
2171 GP_2_6_FN, GPSR2_6,
2172 GP_2_5_FN, GPSR2_5,
2173 GP_2_4_FN, GPSR2_4,
2174 GP_2_3_FN, GPSR2_3,
2175 GP_2_2_FN, GPSR2_2,
2176 GP_2_1_FN, GPSR2_1,
2177 GP_2_0_FN, GPSR2_0, }
2178 },
2179 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2180 0, 0,
2181 0, 0,
2182 0, 0,
2183 0, 0,
2184 0, 0,
2185 0, 0,
2186 0, 0,
2187 0, 0,
2188 0, 0,
2189 0, 0,
2190 0, 0,
2191 0, 0,
2192 0, 0,
2193 0, 0,
2194 0, 0,
2195 0, 0,
2196 GP_3_15_FN, GPSR3_15,
2197 GP_3_14_FN, GPSR3_14,
2198 GP_3_13_FN, GPSR3_13,
2199 GP_3_12_FN, GPSR3_12,
2200 GP_3_11_FN, GPSR3_11,
2201 GP_3_10_FN, GPSR3_10,
2202 GP_3_9_FN, GPSR3_9,
2203 GP_3_8_FN, GPSR3_8,
2204 GP_3_7_FN, GPSR3_7,
2205 GP_3_6_FN, GPSR3_6,
2206 GP_3_5_FN, GPSR3_5,
2207 GP_3_4_FN, GPSR3_4,
2208 GP_3_3_FN, GPSR3_3,
2209 GP_3_2_FN, GPSR3_2,
2210 GP_3_1_FN, GPSR3_1,
2211 GP_3_0_FN, GPSR3_0, }
2212 },
2213 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2214 0, 0,
2215 0, 0,
2216 0, 0,
2217 0, 0,
2218 0, 0,
2219 0, 0,
2220 0, 0,
2221 0, 0,
2222 0, 0,
2223 0, 0,
2224 0, 0,
2225 0, 0,
2226 0, 0,
2227 0, 0,
2228 GP_4_17_FN, GPSR4_17,
2229 GP_4_16_FN, GPSR4_16,
2230 GP_4_15_FN, GPSR4_15,
2231 GP_4_14_FN, GPSR4_14,
2232 GP_4_13_FN, GPSR4_13,
2233 GP_4_12_FN, GPSR4_12,
2234 GP_4_11_FN, GPSR4_11,
2235 GP_4_10_FN, GPSR4_10,
2236 GP_4_9_FN, GPSR4_9,
2237 GP_4_8_FN, GPSR4_8,
2238 GP_4_7_FN, GPSR4_7,
2239 GP_4_6_FN, GPSR4_6,
2240 GP_4_5_FN, GPSR4_5,
2241 GP_4_4_FN, GPSR4_4,
2242 GP_4_3_FN, GPSR4_3,
2243 GP_4_2_FN, GPSR4_2,
2244 GP_4_1_FN, GPSR4_1,
2245 GP_4_0_FN, GPSR4_0, }
2246 },
2247 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2248 0, 0,
2249 0, 0,
2250 0, 0,
2251 0, 0,
2252 0, 0,
2253 0, 0,
2254 GP_5_25_FN, GPSR5_25,
2255 GP_5_24_FN, GPSR5_24,
2256 GP_5_23_FN, GPSR5_23,
2257 GP_5_22_FN, GPSR5_22,
2258 GP_5_21_FN, GPSR5_21,
2259 GP_5_20_FN, GPSR5_20,
2260 GP_5_19_FN, GPSR5_19,
2261 GP_5_18_FN, GPSR5_18,
2262 GP_5_17_FN, GPSR5_17,
2263 GP_5_16_FN, GPSR5_16,
2264 GP_5_15_FN, GPSR5_15,
2265 GP_5_14_FN, GPSR5_14,
2266 GP_5_13_FN, GPSR5_13,
2267 GP_5_12_FN, GPSR5_12,
2268 GP_5_11_FN, GPSR5_11,
2269 GP_5_10_FN, GPSR5_10,
2270 GP_5_9_FN, GPSR5_9,
2271 GP_5_8_FN, GPSR5_8,
2272 GP_5_7_FN, GPSR5_7,
2273 GP_5_6_FN, GPSR5_6,
2274 GP_5_5_FN, GPSR5_5,
2275 GP_5_4_FN, GPSR5_4,
2276 GP_5_3_FN, GPSR5_3,
2277 GP_5_2_FN, GPSR5_2,
2278 GP_5_1_FN, GPSR5_1,
2279 GP_5_0_FN, GPSR5_0, }
2280 },
2281 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
2282 GP_6_31_FN, GPSR6_31,
2283 GP_6_30_FN, GPSR6_30,
2284 GP_6_29_FN, GPSR6_29,
2285 GP_6_28_FN, GPSR6_28,
2286 GP_6_27_FN, GPSR6_27,
2287 GP_6_26_FN, GPSR6_26,
2288 GP_6_25_FN, GPSR6_25,
2289 GP_6_24_FN, GPSR6_24,
2290 GP_6_23_FN, GPSR6_23,
2291 GP_6_22_FN, GPSR6_22,
2292 GP_6_21_FN, GPSR6_21,
2293 GP_6_20_FN, GPSR6_20,
2294 GP_6_19_FN, GPSR6_19,
2295 GP_6_18_FN, GPSR6_18,
2296 GP_6_17_FN, GPSR6_17,
2297 GP_6_16_FN, GPSR6_16,
2298 GP_6_15_FN, GPSR6_15,
2299 GP_6_14_FN, GPSR6_14,
2300 GP_6_13_FN, GPSR6_13,
2301 GP_6_12_FN, GPSR6_12,
2302 GP_6_11_FN, GPSR6_11,
2303 GP_6_10_FN, GPSR6_10,
2304 GP_6_9_FN, GPSR6_9,
2305 GP_6_8_FN, GPSR6_8,
2306 GP_6_7_FN, GPSR6_7,
2307 GP_6_6_FN, GPSR6_6,
2308 GP_6_5_FN, GPSR6_5,
2309 GP_6_4_FN, GPSR6_4,
2310 GP_6_3_FN, GPSR6_3,
2311 GP_6_2_FN, GPSR6_2,
2312 GP_6_1_FN, GPSR6_1,
2313 GP_6_0_FN, GPSR6_0, }
2314 },
2315 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
2316 0, 0,
2317 0, 0,
2318 0, 0,
2319 0, 0,
2320 0, 0,
2321 0, 0,
2322 0, 0,
2323 0, 0,
2324 0, 0,
2325 0, 0,
2326 0, 0,
2327 0, 0,
2328 0, 0,
2329 0, 0,
2330 0, 0,
2331 0, 0,
2332 0, 0,
2333 0, 0,
2334 0, 0,
2335 0, 0,
2336 0, 0,
2337 0, 0,
2338 0, 0,
2339 0, 0,
2340 0, 0,
2341 0, 0,
2342 0, 0,
2343 0, 0,
2344 GP_7_3_FN, GPSR7_3,
2345 GP_7_2_FN, GPSR7_2,
2346 GP_7_1_FN, GPSR7_1,
2347 GP_7_0_FN, GPSR7_0, }
2348 },
2349 #undef F_
2350 #undef FM
2351
2352 #define F_(x, y) x,
2353 #define FM(x) FN_##x,
2354 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2355 IP0_31_28
2356 IP0_27_24
2357 IP0_23_20
2358 IP0_19_16
2359 IP0_15_12
2360 IP0_11_8
2361 IP0_7_4
2362 IP0_3_0 }
2363 },
2364 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2365 IP1_31_28
2366 IP1_27_24
2367 IP1_23_20
2368 IP1_19_16
2369 IP1_15_12
2370 IP1_11_8
2371 IP1_7_4
2372 IP1_3_0 }
2373 },
2374 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2375 IP2_31_28
2376 IP2_27_24
2377 IP2_23_20
2378 IP2_19_16
2379 IP2_15_12
2380 IP2_11_8
2381 IP2_7_4
2382 IP2_3_0 }
2383 },
2384 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2385 IP3_31_28
2386 IP3_27_24
2387 IP3_23_20
2388 IP3_19_16
2389 IP3_15_12
2390 IP3_11_8
2391 IP3_7_4
2392 IP3_3_0 }
2393 },
2394 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2395 IP4_31_28
2396 IP4_27_24
2397 IP4_23_20
2398 IP4_19_16
2399 IP4_15_12
2400 IP4_11_8
2401 IP4_7_4
2402 IP4_3_0 }
2403 },
2404 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2405 IP5_31_28
2406 IP5_27_24
2407 IP5_23_20
2408 IP5_19_16
2409 IP5_15_12
2410 IP5_11_8
2411 IP5_7_4
2412 IP5_3_0 }
2413 },
2414 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2415 IP6_31_28
2416 IP6_27_24
2417 IP6_23_20
2418 IP6_19_16
2419 IP6_15_12
2420 IP6_11_8
2421 IP6_7_4
2422 IP6_3_0 }
2423 },
2424 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2425 IP7_31_28
2426 IP7_27_24
2427 IP7_23_20
2428 IP7_19_16
2429 IP7_15_12
2430 IP7_11_8
2431 IP7_7_4
2432 IP7_3_0 }
2433 },
2434 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2435 IP8_31_28
2436 IP8_27_24
2437 IP8_23_20
2438 IP8_19_16
2439 IP8_15_12
2440 IP8_11_8
2441 IP8_7_4
2442 IP8_3_0 }
2443 },
2444 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
2445 IP9_31_28
2446 IP9_27_24
2447 IP9_23_20
2448 IP9_19_16
2449 IP9_15_12
2450 IP9_11_8
2451 IP9_7_4
2452 IP9_3_0 }
2453 },
2454 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
2455 IP10_31_28
2456 IP10_27_24
2457 IP10_23_20
2458 IP10_19_16
2459 IP10_15_12
2460 IP10_11_8
2461 IP10_7_4
2462 IP10_3_0 }
2463 },
2464 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
2465 IP11_31_28
2466 IP11_27_24
2467 IP11_23_20
2468 IP11_19_16
2469 IP11_15_12
2470 IP11_11_8
2471 IP11_7_4
2472 IP11_3_0 }
2473 },
2474 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
2475 IP12_31_28
2476 IP12_27_24
2477 IP12_23_20
2478 IP12_19_16
2479 IP12_15_12
2480 IP12_11_8
2481 IP12_7_4
2482 IP12_3_0 }
2483 },
2484 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
2485 IP13_31_28
2486 IP13_27_24
2487 IP13_23_20
2488 IP13_19_16
2489 IP13_15_12
2490 IP13_11_8
2491 IP13_7_4
2492 IP13_3_0 }
2493 },
2494 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
2495 IP14_31_28
2496 IP14_27_24
2497 IP14_23_20
2498 IP14_19_16
2499 IP14_15_12
2500 IP14_11_8
2501 IP14_7_4
2502 IP14_3_0 }
2503 },
2504 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
2505 IP15_31_28
2506 IP15_27_24
2507 IP15_23_20
2508 IP15_19_16
2509 IP15_15_12
2510 IP15_11_8
2511 IP15_7_4
2512 IP15_3_0 }
2513 },
2514 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
2515 IP16_31_28
2516 IP16_27_24
2517 IP16_23_20
2518 IP16_19_16
2519 IP16_15_12
2520 IP16_11_8
2521 IP16_7_4
2522 IP16_3_0 }
2523 },
2524 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
2525 IP17_31_28
2526 IP17_27_24
2527 IP17_23_20
2528 IP17_19_16
2529 IP17_15_12
2530 IP17_11_8
2531 IP17_7_4
2532 IP17_3_0 }
2533 },
2534 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
2535 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2536 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2537 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2538 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2539 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2540 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2541 IP18_7_4
2542 IP18_3_0 }
2543 },
2544 #undef F_
2545 #undef FM
2546
2547 #define F_(x, y) x,
2548 #define FM(x) FN_##x,
2549 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2550 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
2551 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
2552 MOD_SEL0_31_30_29
2553 MOD_SEL0_28_27
2554 MOD_SEL0_26_25_24
2555 MOD_SEL0_23
2556 MOD_SEL0_22
2557 MOD_SEL0_21
2558 MOD_SEL0_20
2559 MOD_SEL0_19
2560 MOD_SEL0_18_17
2561 MOD_SEL0_16
2562 MOD_SEL0_15
2563 MOD_SEL0_14_13
2564 MOD_SEL0_12
2565 MOD_SEL0_11
2566 MOD_SEL0_10
2567 MOD_SEL0_9_8
2568 MOD_SEL0_7_6
2569 MOD_SEL0_5
2570 MOD_SEL0_4_3
2571 /* RESERVED 2, 1, 0 */
2572 0, 0, 0, 0, 0, 0, 0, 0 }
2573 },
2574 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2575 2, 3, 1, 2, 3, 1, 1, 2, 1,
2576 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2577 MOD_SEL1_31_30
2578 MOD_SEL1_29_28_27
2579 MOD_SEL1_26
2580 MOD_SEL1_25_24
2581 MOD_SEL1_23_22_21
2582 MOD_SEL1_20
2583 MOD_SEL1_19
2584 MOD_SEL1_18_17
2585 MOD_SEL1_16
2586 MOD_SEL1_15_14
2587 MOD_SEL1_13
2588 MOD_SEL1_12
2589 MOD_SEL1_11
2590 MOD_SEL1_10
2591 MOD_SEL1_9
2592 0, 0, 0, 0, /* RESERVED 8, 7 */
2593 MOD_SEL1_6
2594 MOD_SEL1_5
2595 MOD_SEL1_4
2596 MOD_SEL1_3
2597 MOD_SEL1_2
2598 MOD_SEL1_1
2599 MOD_SEL1_0 }
2600 },
2601 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
2602 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
2603 4, 4, 4, 3, 1) {
2604 MOD_SEL2_31
2605 MOD_SEL2_30
2606 MOD_SEL2_29
2607 MOD_SEL2_28_27
2608 MOD_SEL2_26
2609 MOD_SEL2_25_24_23
2610 MOD_SEL2_22
2611 MOD_SEL2_21
2612 MOD_SEL2_20
2613 MOD_SEL2_19
2614 MOD_SEL2_18
2615 MOD_SEL2_17
2616 /* RESERVED 16 */
2617 0, 0,
2618 /* RESERVED 15, 14, 13, 12 */
2619 0, 0, 0, 0, 0, 0, 0, 0,
2620 0, 0, 0, 0, 0, 0, 0, 0,
2621 /* RESERVED 11, 10, 9, 8 */
2622 0, 0, 0, 0, 0, 0, 0, 0,
2623 0, 0, 0, 0, 0, 0, 0, 0,
2624 /* RESERVED 7, 6, 5, 4 */
2625 0, 0, 0, 0, 0, 0, 0, 0,
2626 0, 0, 0, 0, 0, 0, 0, 0,
2627 /* RESERVED 3, 2, 1 */
2628 0, 0, 0, 0, 0, 0, 0, 0,
2629 MOD_SEL2_0 }
2630 },
2631 { },
2632 };
2633
2634 static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
2635 {
2636 int bit = -EINVAL;
2637
2638 *pocctrl = 0xe6060380;
2639
2640 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
2641 bit = pin & 0x1f;
2642
2643 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
2644 bit = (pin & 0x1f) + 12;
2645
2646 return bit;
2647 }
2648
2649 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
2650 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
2651 };
2652
2653 const struct sh_pfc_soc_info r8a7796_pinmux_info = {
2654 .name = "r8a77960_pfc",
2655 .ops = &r8a7796_pinmux_ops,
2656 .unlock_reg = 0xe6060000, /* PMMR */
2657
2658 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2659
2660 .pins = pinmux_pins,
2661 .nr_pins = ARRAY_SIZE(pinmux_pins),
2662 .groups = pinmux_groups,
2663 .nr_groups = ARRAY_SIZE(pinmux_groups),
2664 .functions = pinmux_functions,
2665 .nr_functions = ARRAY_SIZE(pinmux_functions),
2666
2667 .cfg_regs = pinmux_config_regs,
2668
2669 .pinmux_data = pinmux_data,
2670 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2671 };
Linux with added FPC-III support