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r8152: fix tx packets accounting
[linux/fpc-iii.git] / drivers / tty / serial / samsung.c
blobf2ab6d8aab4127ff86e172afa61e89238b93c093
1 /*
2 * Driver core for Samsung SoC onboard UARTs.
3 *
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 /* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25 */
26
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #define SUPPORT_SYSRQ
29 #endif
30
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/io.h>
37 #include <linux/platform_device.h>
38 #include <linux/init.h>
39 #include <linux/sysrq.h>
40 #include <linux/console.h>
41 #include <linux/tty.h>
42 #include <linux/tty_flip.h>
43 #include <linux/serial_core.h>
44 #include <linux/serial.h>
45 #include <linux/serial_s3c.h>
46 #include <linux/delay.h>
47 #include <linux/clk.h>
48 #include <linux/cpufreq.h>
49 #include <linux/of.h>
50
51 #include <asm/irq.h>
52
53 #include "samsung.h"
54
55 #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
56 !defined(MODULE)
57
58 extern void printascii(const char *);
59
60 __printf(1, 2)
61 static void dbg(const char *fmt, ...)
62 {
63 va_list va;
64 char buff[256];
65
66 va_start(va, fmt);
67 vscnprintf(buff, sizeof(buff), fmt, va);
68 va_end(va);
69
70 printascii(buff);
71 }
72
73 #else
74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
75 #endif
76
77 /* UART name and device definitions */
78
79 #define S3C24XX_SERIAL_NAME "ttySAC"
80 #define S3C24XX_SERIAL_MAJOR 204
81 #define S3C24XX_SERIAL_MINOR 64
82
83 #define S3C24XX_TX_PIO 1
84 #define S3C24XX_TX_DMA 2
85 #define S3C24XX_RX_PIO 1
86 #define S3C24XX_RX_DMA 2
87 /* macros to change one thing to another */
88
89 #define tx_enabled(port) ((port)->unused[0])
90 #define rx_enabled(port) ((port)->unused[1])
91
92 /* flag to ignore all characters coming in */
93 #define RXSTAT_DUMMY_READ (0x10000000)
94
95 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
96 {
97 return container_of(port, struct s3c24xx_uart_port, port);
98 }
99
100 /* translate a port to the device name */
101
102 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
103 {
104 return to_platform_device(port->dev)->name;
105 }
106
107 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
108 {
109 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
110 }
111
112 /*
113 * s3c64xx and later SoC's include the interrupt mask and status registers in
114 * the controller itself, unlike the s3c24xx SoC's which have these registers
115 * in the interrupt controller. Check if the port type is s3c64xx or higher.
116 */
117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
118 {
119 return to_ourport(port)->info->type == PORT_S3C6400;
120 }
121
122 static void s3c24xx_serial_rx_enable(struct uart_port *port)
123 {
124 unsigned long flags;
125 unsigned int ucon, ufcon;
126 int count = 10000;
127
128 spin_lock_irqsave(&port->lock, flags);
129
130 while (--count && !s3c24xx_serial_txempty_nofifo(port))
131 udelay(100);
132
133 ufcon = rd_regl(port, S3C2410_UFCON);
134 ufcon |= S3C2410_UFCON_RESETRX;
135 wr_regl(port, S3C2410_UFCON, ufcon);
136
137 ucon = rd_regl(port, S3C2410_UCON);
138 ucon |= S3C2410_UCON_RXIRQMODE;
139 wr_regl(port, S3C2410_UCON, ucon);
140
141 rx_enabled(port) = 1;
142 spin_unlock_irqrestore(&port->lock, flags);
143 }
144
145 static void s3c24xx_serial_rx_disable(struct uart_port *port)
146 {
147 unsigned long flags;
148 unsigned int ucon;
149
150 spin_lock_irqsave(&port->lock, flags);
151
152 ucon = rd_regl(port, S3C2410_UCON);
153 ucon &= ~S3C2410_UCON_RXIRQMODE;
154 wr_regl(port, S3C2410_UCON, ucon);
155
156 rx_enabled(port) = 0;
157 spin_unlock_irqrestore(&port->lock, flags);
158 }
159
160 static void s3c24xx_serial_stop_tx(struct uart_port *port)
161 {
162 struct s3c24xx_uart_port *ourport = to_ourport(port);
163 struct s3c24xx_uart_dma *dma = ourport->dma;
164 struct circ_buf *xmit = &port->state->xmit;
165 struct dma_tx_state state;
166 int count;
167
168 if (!tx_enabled(port))
169 return;
170
171 if (s3c24xx_serial_has_interrupt_mask(port))
172 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
173 else
174 disable_irq_nosync(ourport->tx_irq);
175
176 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
177 dmaengine_pause(dma->tx_chan);
178 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
179 dmaengine_terminate_all(dma->tx_chan);
180 dma_sync_single_for_cpu(ourport->port.dev,
181 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
182 async_tx_ack(dma->tx_desc);
183 count = dma->tx_bytes_requested - state.residue;
184 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
185 port->icount.tx += count;
186 }
187
188 tx_enabled(port) = 0;
189 ourport->tx_in_progress = 0;
190
191 if (port->flags & UPF_CONS_FLOW)
192 s3c24xx_serial_rx_enable(port);
193
194 ourport->tx_mode = 0;
195 }
196
197 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
198
199 static void s3c24xx_serial_tx_dma_complete(void *args)
200 {
201 struct s3c24xx_uart_port *ourport = args;
202 struct uart_port *port = &ourport->port;
203 struct circ_buf *xmit = &port->state->xmit;
204 struct s3c24xx_uart_dma *dma = ourport->dma;
205 struct dma_tx_state state;
206 unsigned long flags;
207 int count;
208
209
210 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
211 count = dma->tx_bytes_requested - state.residue;
212 async_tx_ack(dma->tx_desc);
213
214 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
215 dma->tx_size, DMA_TO_DEVICE);
216
217 spin_lock_irqsave(&port->lock, flags);
218
219 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
220 port->icount.tx += count;
221 ourport->tx_in_progress = 0;
222
223 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
224 uart_write_wakeup(port);
225
226 s3c24xx_serial_start_next_tx(ourport);
227 spin_unlock_irqrestore(&port->lock, flags);
228 }
229
230 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
231 {
232 struct uart_port *port = &ourport->port;
233 u32 ucon;
234
235 /* Mask Tx interrupt */
236 if (s3c24xx_serial_has_interrupt_mask(port))
237 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
238 else
239 disable_irq_nosync(ourport->tx_irq);
240
241 /* Enable tx dma mode */
242 ucon = rd_regl(port, S3C2410_UCON);
243 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
244 ucon |= (dma_get_cache_alignment() >= 16) ?
245 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
246 ucon |= S3C64XX_UCON_TXMODE_DMA;
247 wr_regl(port, S3C2410_UCON, ucon);
248
249 ourport->tx_mode = S3C24XX_TX_DMA;
250 }
251
252 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
253 {
254 struct uart_port *port = &ourport->port;
255 u32 ucon, ufcon;
256
257 /* Set ufcon txtrig */
258 ourport->tx_in_progress = S3C24XX_TX_PIO;
259 ufcon = rd_regl(port, S3C2410_UFCON);
260 wr_regl(port, S3C2410_UFCON, ufcon);
261
262 /* Enable tx pio mode */
263 ucon = rd_regl(port, S3C2410_UCON);
264 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
265 ucon |= S3C64XX_UCON_TXMODE_CPU;
266 wr_regl(port, S3C2410_UCON, ucon);
267
268 /* Unmask Tx interrupt */
269 if (s3c24xx_serial_has_interrupt_mask(port))
270 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
271 S3C64XX_UINTM);
272 else
273 enable_irq(ourport->tx_irq);
274
275 ourport->tx_mode = S3C24XX_TX_PIO;
276 }
277
278 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
279 {
280 if (ourport->tx_mode != S3C24XX_TX_PIO)
281 enable_tx_pio(ourport);
282 }
283
284 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
285 unsigned int count)
286 {
287 struct uart_port *port = &ourport->port;
288 struct circ_buf *xmit = &port->state->xmit;
289 struct s3c24xx_uart_dma *dma = ourport->dma;
290
291
292 if (ourport->tx_mode != S3C24XX_TX_DMA)
293 enable_tx_dma(ourport);
294
295 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
296 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
297
298 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
299 dma->tx_size, DMA_TO_DEVICE);
300
301 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
302 dma->tx_transfer_addr, dma->tx_size,
303 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
304 if (!dma->tx_desc) {
305 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
306 return -EIO;
307 }
308
309 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
310 dma->tx_desc->callback_param = ourport;
311 dma->tx_bytes_requested = dma->tx_size;
312
313 ourport->tx_in_progress = S3C24XX_TX_DMA;
314 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
315 dma_async_issue_pending(dma->tx_chan);
316 return 0;
317 }
318
319 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
320 {
321 struct uart_port *port = &ourport->port;
322 struct circ_buf *xmit = &port->state->xmit;
323 unsigned long count;
324
325 /* Get data size up to the end of buffer */
326 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
327
328 if (!count) {
329 s3c24xx_serial_stop_tx(port);
330 return;
331 }
332
333 if (!ourport->dma || !ourport->dma->tx_chan ||
334 count < ourport->min_dma_size ||
335 xmit->tail & (dma_get_cache_alignment() - 1))
336 s3c24xx_serial_start_tx_pio(ourport);
337 else
338 s3c24xx_serial_start_tx_dma(ourport, count);
339 }
340
341 static void s3c24xx_serial_start_tx(struct uart_port *port)
342 {
343 struct s3c24xx_uart_port *ourport = to_ourport(port);
344 struct circ_buf *xmit = &port->state->xmit;
345
346 if (!tx_enabled(port)) {
347 if (port->flags & UPF_CONS_FLOW)
348 s3c24xx_serial_rx_disable(port);
349
350 tx_enabled(port) = 1;
351 if (!ourport->dma || !ourport->dma->tx_chan)
352 s3c24xx_serial_start_tx_pio(ourport);
353 }
354
355 if (ourport->dma && ourport->dma->tx_chan) {
356 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
357 s3c24xx_serial_start_next_tx(ourport);
358 }
359 }
360
361 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
362 struct tty_port *tty, int count)
363 {
364 struct s3c24xx_uart_dma *dma = ourport->dma;
365 int copied;
366
367 if (!count)
368 return;
369
370 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
371 dma->rx_size, DMA_FROM_DEVICE);
372
373 ourport->port.icount.rx += count;
374 if (!tty) {
375 dev_err(ourport->port.dev, "No tty port\n");
376 return;
377 }
378 copied = tty_insert_flip_string(tty,
379 ((unsigned char *)(ourport->dma->rx_buf)), count);
380 if (copied != count) {
381 WARN_ON(1);
382 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
383 }
384 }
385
386 static void s3c24xx_serial_stop_rx(struct uart_port *port)
387 {
388 struct s3c24xx_uart_port *ourport = to_ourport(port);
389 struct s3c24xx_uart_dma *dma = ourport->dma;
390 struct tty_port *t = &port->state->port;
391 struct dma_tx_state state;
392 enum dma_status dma_status;
393 unsigned int received;
394
395 if (rx_enabled(port)) {
396 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
397 if (s3c24xx_serial_has_interrupt_mask(port))
398 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
399 S3C64XX_UINTM);
400 else
401 disable_irq_nosync(ourport->rx_irq);
402 rx_enabled(port) = 0;
403 }
404 if (dma && dma->rx_chan) {
405 dmaengine_pause(dma->tx_chan);
406 dma_status = dmaengine_tx_status(dma->rx_chan,
407 dma->rx_cookie, &state);
408 if (dma_status == DMA_IN_PROGRESS ||
409 dma_status == DMA_PAUSED) {
410 received = dma->rx_bytes_requested - state.residue;
411 dmaengine_terminate_all(dma->rx_chan);
412 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
413 }
414 }
415 }
416
417 static inline struct s3c24xx_uart_info
418 *s3c24xx_port_to_info(struct uart_port *port)
419 {
420 return to_ourport(port)->info;
421 }
422
423 static inline struct s3c2410_uartcfg
424 *s3c24xx_port_to_cfg(struct uart_port *port)
425 {
426 struct s3c24xx_uart_port *ourport;
427
428 if (port->dev == NULL)
429 return NULL;
430
431 ourport = container_of(port, struct s3c24xx_uart_port, port);
432 return ourport->cfg;
433 }
434
435 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
436 unsigned long ufstat)
437 {
438 struct s3c24xx_uart_info *info = ourport->info;
439
440 if (ufstat & info->rx_fifofull)
441 return ourport->port.fifosize;
442
443 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
444 }
445
446 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
447 static void s3c24xx_serial_rx_dma_complete(void *args)
448 {
449 struct s3c24xx_uart_port *ourport = args;
450 struct uart_port *port = &ourport->port;
451
452 struct s3c24xx_uart_dma *dma = ourport->dma;
453 struct tty_port *t = &port->state->port;
454 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
455
456 struct dma_tx_state state;
457 unsigned long flags;
458 int received;
459
460 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
461 received = dma->rx_bytes_requested - state.residue;
462 async_tx_ack(dma->rx_desc);
463
464 spin_lock_irqsave(&port->lock, flags);
465
466 if (received)
467 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
468
469 if (tty) {
470 tty_flip_buffer_push(t);
471 tty_kref_put(tty);
472 }
473
474 s3c64xx_start_rx_dma(ourport);
475
476 spin_unlock_irqrestore(&port->lock, flags);
477 }
478
479 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
480 {
481 struct s3c24xx_uart_dma *dma = ourport->dma;
482
483 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
484 dma->rx_size, DMA_FROM_DEVICE);
485
486 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
487 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
488 DMA_PREP_INTERRUPT);
489 if (!dma->rx_desc) {
490 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
491 return;
492 }
493
494 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
495 dma->rx_desc->callback_param = ourport;
496 dma->rx_bytes_requested = dma->rx_size;
497
498 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
499 dma_async_issue_pending(dma->rx_chan);
500 }
501
502 /* ? - where has parity gone?? */
503 #define S3C2410_UERSTAT_PARITY (0x1000)
504
505 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
506 {
507 struct uart_port *port = &ourport->port;
508 unsigned int ucon;
509
510 /* set Rx mode to DMA mode */
511 ucon = rd_regl(port, S3C2410_UCON);
512 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
513 S3C64XX_UCON_TIMEOUT_MASK |
514 S3C64XX_UCON_EMPTYINT_EN |
515 S3C64XX_UCON_DMASUS_EN |
516 S3C64XX_UCON_TIMEOUT_EN |
517 S3C64XX_UCON_RXMODE_MASK);
518 ucon |= S3C64XX_UCON_RXBURST_16 |
519 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
520 S3C64XX_UCON_EMPTYINT_EN |
521 S3C64XX_UCON_TIMEOUT_EN |
522 S3C64XX_UCON_RXMODE_DMA;
523 wr_regl(port, S3C2410_UCON, ucon);
524
525 ourport->rx_mode = S3C24XX_RX_DMA;
526 }
527
528 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
529 {
530 struct uart_port *port = &ourport->port;
531 unsigned int ucon;
532
533 /* set Rx mode to DMA mode */
534 ucon = rd_regl(port, S3C2410_UCON);
535 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
536 S3C64XX_UCON_EMPTYINT_EN |
537 S3C64XX_UCON_DMASUS_EN |
538 S3C64XX_UCON_TIMEOUT_EN |
539 S3C64XX_UCON_RXMODE_MASK);
540 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
541 S3C64XX_UCON_TIMEOUT_EN |
542 S3C64XX_UCON_RXMODE_CPU;
543 wr_regl(port, S3C2410_UCON, ucon);
544
545 ourport->rx_mode = S3C24XX_RX_PIO;
546 }
547
548 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
549
550 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
551 {
552 unsigned int utrstat, ufstat, received;
553 struct s3c24xx_uart_port *ourport = dev_id;
554 struct uart_port *port = &ourport->port;
555 struct s3c24xx_uart_dma *dma = ourport->dma;
556 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
557 struct tty_port *t = &port->state->port;
558 unsigned long flags;
559 struct dma_tx_state state;
560
561 utrstat = rd_regl(port, S3C2410_UTRSTAT);
562 ufstat = rd_regl(port, S3C2410_UFSTAT);
563
564 spin_lock_irqsave(&port->lock, flags);
565
566 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
567 s3c64xx_start_rx_dma(ourport);
568 if (ourport->rx_mode == S3C24XX_RX_PIO)
569 enable_rx_dma(ourport);
570 goto finish;
571 }
572
573 if (ourport->rx_mode == S3C24XX_RX_DMA) {
574 dmaengine_pause(dma->rx_chan);
575 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
576 dmaengine_terminate_all(dma->rx_chan);
577 received = dma->rx_bytes_requested - state.residue;
578 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
579
580 enable_rx_pio(ourport);
581 }
582
583 s3c24xx_serial_rx_drain_fifo(ourport);
584
585 if (tty) {
586 tty_flip_buffer_push(t);
587 tty_kref_put(tty);
588 }
589
590 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
591
592 finish:
593 spin_unlock_irqrestore(&port->lock, flags);
594
595 return IRQ_HANDLED;
596 }
597
598 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
599 {
600 struct uart_port *port = &ourport->port;
601 unsigned int ufcon, ch, flag, ufstat, uerstat;
602 unsigned int fifocnt = 0;
603 int max_count = port->fifosize;
604
605 while (max_count-- > 0) {
606 /*
607 * Receive all characters known to be in FIFO
608 * before reading FIFO level again
609 */
610 if (fifocnt == 0) {
611 ufstat = rd_regl(port, S3C2410_UFSTAT);
612 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
613 if (fifocnt == 0)
614 break;
615 }
616 fifocnt--;
617
618 uerstat = rd_regl(port, S3C2410_UERSTAT);
619 ch = rd_regb(port, S3C2410_URXH);
620
621 if (port->flags & UPF_CONS_FLOW) {
622 int txe = s3c24xx_serial_txempty_nofifo(port);
623
624 if (rx_enabled(port)) {
625 if (!txe) {
626 rx_enabled(port) = 0;
627 continue;
628 }
629 } else {
630 if (txe) {
631 ufcon = rd_regl(port, S3C2410_UFCON);
632 ufcon |= S3C2410_UFCON_RESETRX;
633 wr_regl(port, S3C2410_UFCON, ufcon);
634 rx_enabled(port) = 1;
635 return;
636 }
637 continue;
638 }
639 }
640
641 /* insert the character into the buffer */
642
643 flag = TTY_NORMAL;
644 port->icount.rx++;
645
646 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
647 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
648 ch, uerstat);
649
650 /* check for break */
651 if (uerstat & S3C2410_UERSTAT_BREAK) {
652 dbg("break!\n");
653 port->icount.brk++;
654 if (uart_handle_break(port))
655 continue; /* Ignore character */
656 }
657
658 if (uerstat & S3C2410_UERSTAT_FRAME)
659 port->icount.frame++;
660 if (uerstat & S3C2410_UERSTAT_OVERRUN)
661 port->icount.overrun++;
662
663 uerstat &= port->read_status_mask;
664
665 if (uerstat & S3C2410_UERSTAT_BREAK)
666 flag = TTY_BREAK;
667 else if (uerstat & S3C2410_UERSTAT_PARITY)
668 flag = TTY_PARITY;
669 else if (uerstat & (S3C2410_UERSTAT_FRAME |
670 S3C2410_UERSTAT_OVERRUN))
671 flag = TTY_FRAME;
672 }
673
674 if (uart_handle_sysrq_char(port, ch))
675 continue; /* Ignore character */
676
677 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
678 ch, flag);
679 }
680
681 tty_flip_buffer_push(&port->state->port);
682 }
683
684 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
685 {
686 struct s3c24xx_uart_port *ourport = dev_id;
687 struct uart_port *port = &ourport->port;
688 unsigned long flags;
689
690 spin_lock_irqsave(&port->lock, flags);
691 s3c24xx_serial_rx_drain_fifo(ourport);
692 spin_unlock_irqrestore(&port->lock, flags);
693
694 return IRQ_HANDLED;
695 }
696
697
698 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
699 {
700 struct s3c24xx_uart_port *ourport = dev_id;
701
702 if (ourport->dma && ourport->dma->rx_chan)
703 return s3c24xx_serial_rx_chars_dma(dev_id);
704 return s3c24xx_serial_rx_chars_pio(dev_id);
705 }
706
707 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
708 {
709 struct s3c24xx_uart_port *ourport = id;
710 struct uart_port *port = &ourport->port;
711 struct circ_buf *xmit = &port->state->xmit;
712 unsigned long flags;
713 int count, dma_count = 0;
714
715 spin_lock_irqsave(&port->lock, flags);
716
717 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
718
719 if (ourport->dma && ourport->dma->tx_chan &&
720 count >= ourport->min_dma_size) {
721 int align = dma_get_cache_alignment() -
722 (xmit->tail & (dma_get_cache_alignment() - 1));
723 if (count-align >= ourport->min_dma_size) {
724 dma_count = count-align;
725 count = align;
726 }
727 }
728
729 if (port->x_char) {
730 wr_regb(port, S3C2410_UTXH, port->x_char);
731 port->icount.tx++;
732 port->x_char = 0;
733 goto out;
734 }
735
736 /* if there isn't anything more to transmit, or the uart is now
737 * stopped, disable the uart and exit
738 */
739
740 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
741 s3c24xx_serial_stop_tx(port);
742 goto out;
743 }
744
745 /* try and drain the buffer... */
746
747 if (count > port->fifosize) {
748 count = port->fifosize;
749 dma_count = 0;
750 }
751
752 while (!uart_circ_empty(xmit) && count > 0) {
753 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
754 break;
755
756 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
757 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
758 port->icount.tx++;
759 count--;
760 }
761
762 if (!count && dma_count) {
763 s3c24xx_serial_start_tx_dma(ourport, dma_count);
764 goto out;
765 }
766
767 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
768 spin_unlock(&port->lock);
769 uart_write_wakeup(port);
770 spin_lock(&port->lock);
771 }
772
773 if (uart_circ_empty(xmit))
774 s3c24xx_serial_stop_tx(port);
775
776 out:
777 spin_unlock_irqrestore(&port->lock, flags);
778 return IRQ_HANDLED;
779 }
780
781 /* interrupt handler for s3c64xx and later SoC's.*/
782 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
783 {
784 struct s3c24xx_uart_port *ourport = id;
785 struct uart_port *port = &ourport->port;
786 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
787 irqreturn_t ret = IRQ_HANDLED;
788
789 if (pend & S3C64XX_UINTM_RXD_MSK) {
790 ret = s3c24xx_serial_rx_chars(irq, id);
791 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
792 }
793 if (pend & S3C64XX_UINTM_TXD_MSK) {
794 ret = s3c24xx_serial_tx_chars(irq, id);
795 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
796 }
797 return ret;
798 }
799
800 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
801 {
802 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
803 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
804 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
805
806 if (ufcon & S3C2410_UFCON_FIFOMODE) {
807 if ((ufstat & info->tx_fifomask) != 0 ||
808 (ufstat & info->tx_fifofull))
809 return 0;
810
811 return 1;
812 }
813
814 return s3c24xx_serial_txempty_nofifo(port);
815 }
816
817 /* no modem control lines */
818 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
819 {
820 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
821
822 if (umstat & S3C2410_UMSTAT_CTS)
823 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
824 else
825 return TIOCM_CAR | TIOCM_DSR;
826 }
827
828 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
829 {
830 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
831
832 if (mctrl & TIOCM_RTS)
833 umcon |= S3C2410_UMCOM_RTS_LOW;
834 else
835 umcon &= ~S3C2410_UMCOM_RTS_LOW;
836
837 wr_regl(port, S3C2410_UMCON, umcon);
838 }
839
840 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
841 {
842 unsigned long flags;
843 unsigned int ucon;
844
845 spin_lock_irqsave(&port->lock, flags);
846
847 ucon = rd_regl(port, S3C2410_UCON);
848
849 if (break_state)
850 ucon |= S3C2410_UCON_SBREAK;
851 else
852 ucon &= ~S3C2410_UCON_SBREAK;
853
854 wr_regl(port, S3C2410_UCON, ucon);
855
856 spin_unlock_irqrestore(&port->lock, flags);
857 }
858
859 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
860 {
861 struct s3c24xx_uart_dma *dma = p->dma;
862 dma_cap_mask_t mask;
863 unsigned long flags;
864
865 /* Default slave configuration parameters */
866 dma->rx_conf.direction = DMA_DEV_TO_MEM;
867 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
868 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
869 dma->rx_conf.src_maxburst = 16;
870
871 dma->tx_conf.direction = DMA_MEM_TO_DEV;
872 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
873 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
874 if (dma_get_cache_alignment() >= 16)
875 dma->tx_conf.dst_maxburst = 16;
876 else
877 dma->tx_conf.dst_maxburst = 1;
878
879 dma_cap_zero(mask);
880 dma_cap_set(DMA_SLAVE, mask);
881
882 dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
883 dma->rx_param, p->port.dev, "rx");
884 if (!dma->rx_chan)
885 return -ENODEV;
886
887 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
888
889 dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
890 dma->tx_param, p->port.dev, "tx");
891 if (!dma->tx_chan) {
892 dma_release_channel(dma->rx_chan);
893 return -ENODEV;
894 }
895
896 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
897
898 /* RX buffer */
899 dma->rx_size = PAGE_SIZE;
900
901 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
902
903 if (!dma->rx_buf) {
904 dma_release_channel(dma->rx_chan);
905 dma_release_channel(dma->tx_chan);
906 return -ENOMEM;
907 }
908
909 dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
910 dma->rx_size, DMA_FROM_DEVICE);
911
912 spin_lock_irqsave(&p->port.lock, flags);
913
914 /* TX buffer */
915 dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
916 UART_XMIT_SIZE, DMA_TO_DEVICE);
917
918 spin_unlock_irqrestore(&p->port.lock, flags);
919
920 return 0;
921 }
922
923 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
924 {
925 struct s3c24xx_uart_dma *dma = p->dma;
926
927 if (dma->rx_chan) {
928 dmaengine_terminate_all(dma->rx_chan);
929 dma_unmap_single(p->port.dev, dma->rx_addr,
930 dma->rx_size, DMA_FROM_DEVICE);
931 kfree(dma->rx_buf);
932 dma_release_channel(dma->rx_chan);
933 dma->rx_chan = NULL;
934 }
935
936 if (dma->tx_chan) {
937 dmaengine_terminate_all(dma->tx_chan);
938 dma_unmap_single(p->port.dev, dma->tx_addr,
939 UART_XMIT_SIZE, DMA_TO_DEVICE);
940 dma_release_channel(dma->tx_chan);
941 dma->tx_chan = NULL;
942 }
943 }
944
945 static void s3c24xx_serial_shutdown(struct uart_port *port)
946 {
947 struct s3c24xx_uart_port *ourport = to_ourport(port);
948
949 if (ourport->tx_claimed) {
950 if (!s3c24xx_serial_has_interrupt_mask(port))
951 free_irq(ourport->tx_irq, ourport);
952 tx_enabled(port) = 0;
953 ourport->tx_claimed = 0;
954 ourport->tx_mode = 0;
955 }
956
957 if (ourport->rx_claimed) {
958 if (!s3c24xx_serial_has_interrupt_mask(port))
959 free_irq(ourport->rx_irq, ourport);
960 ourport->rx_claimed = 0;
961 rx_enabled(port) = 0;
962 }
963
964 /* Clear pending interrupts and mask all interrupts */
965 if (s3c24xx_serial_has_interrupt_mask(port)) {
966 free_irq(port->irq, ourport);
967
968 wr_regl(port, S3C64XX_UINTP, 0xf);
969 wr_regl(port, S3C64XX_UINTM, 0xf);
970 }
971
972 if (ourport->dma)
973 s3c24xx_serial_release_dma(ourport);
974
975 ourport->tx_in_progress = 0;
976 }
977
978 static int s3c24xx_serial_startup(struct uart_port *port)
979 {
980 struct s3c24xx_uart_port *ourport = to_ourport(port);
981 int ret;
982
983 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
984 port, (unsigned long long)port->mapbase, port->membase);
985
986 rx_enabled(port) = 1;
987
988 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
989 s3c24xx_serial_portname(port), ourport);
990
991 if (ret != 0) {
992 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
993 return ret;
994 }
995
996 ourport->rx_claimed = 1;
997
998 dbg("requesting tx irq...\n");
999
1000 tx_enabled(port) = 1;
1001
1002 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1003 s3c24xx_serial_portname(port), ourport);
1004
1005 if (ret) {
1006 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1007 goto err;
1008 }
1009
1010 ourport->tx_claimed = 1;
1011
1012 dbg("s3c24xx_serial_startup ok\n");
1013
1014 /* the port reset code should have done the correct
1015 * register setup for the port controls */
1016
1017 return ret;
1018
1019 err:
1020 s3c24xx_serial_shutdown(port);
1021 return ret;
1022 }
1023
1024 static int s3c64xx_serial_startup(struct uart_port *port)
1025 {
1026 struct s3c24xx_uart_port *ourport = to_ourport(port);
1027 unsigned long flags;
1028 unsigned int ufcon;
1029 int ret;
1030
1031 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1032 port, (unsigned long long)port->mapbase, port->membase);
1033
1034 wr_regl(port, S3C64XX_UINTM, 0xf);
1035 if (ourport->dma) {
1036 ret = s3c24xx_serial_request_dma(ourport);
1037 if (ret < 0) {
1038 dev_warn(port->dev,
1039 "DMA request failed, DMA will not be used\n");
1040 devm_kfree(port->dev, ourport->dma);
1041 ourport->dma = NULL;
1042 }
1043 }
1044
1045 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1046 s3c24xx_serial_portname(port), ourport);
1047 if (ret) {
1048 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1049 return ret;
1050 }
1051
1052 /* For compatibility with s3c24xx Soc's */
1053 rx_enabled(port) = 1;
1054 ourport->rx_claimed = 1;
1055 tx_enabled(port) = 0;
1056 ourport->tx_claimed = 1;
1057
1058 spin_lock_irqsave(&port->lock, flags);
1059
1060 ufcon = rd_regl(port, S3C2410_UFCON);
1061 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1062 if (!uart_console(port))
1063 ufcon |= S3C2410_UFCON_RESETTX;
1064 wr_regl(port, S3C2410_UFCON, ufcon);
1065
1066 enable_rx_pio(ourport);
1067
1068 spin_unlock_irqrestore(&port->lock, flags);
1069
1070 /* Enable Rx Interrupt */
1071 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1072
1073 dbg("s3c64xx_serial_startup ok\n");
1074 return ret;
1075 }
1076
1077 /* power power management control */
1078
1079 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1080 unsigned int old)
1081 {
1082 struct s3c24xx_uart_port *ourport = to_ourport(port);
1083 int timeout = 10000;
1084
1085 ourport->pm_level = level;
1086
1087 switch (level) {
1088 case 3:
1089 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1090 udelay(100);
1091
1092 if (!IS_ERR(ourport->baudclk))
1093 clk_disable_unprepare(ourport->baudclk);
1094
1095 clk_disable_unprepare(ourport->clk);
1096 break;
1097
1098 case 0:
1099 clk_prepare_enable(ourport->clk);
1100
1101 if (!IS_ERR(ourport->baudclk))
1102 clk_prepare_enable(ourport->baudclk);
1103
1104 break;
1105 default:
1106 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1107 }
1108 }
1109
1110 /* baud rate calculation
1111 *
1112 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1113 * of different sources, including the peripheral clock ("pclk") and an
1114 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1115 * with a programmable extra divisor.
1116 *
1117 * The following code goes through the clock sources, and calculates the
1118 * baud clocks (and the resultant actual baud rates) and then tries to
1119 * pick the closest one and select that.
1120 *
1121 */
1122
1123 #define MAX_CLK_NAME_LENGTH 15
1124
1125 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1126 {
1127 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1128 unsigned int ucon;
1129
1130 if (info->num_clks == 1)
1131 return 0;
1132
1133 ucon = rd_regl(port, S3C2410_UCON);
1134 ucon &= info->clksel_mask;
1135 return ucon >> info->clksel_shift;
1136 }
1137
1138 static void s3c24xx_serial_setsource(struct uart_port *port,
1139 unsigned int clk_sel)
1140 {
1141 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1142 unsigned int ucon;
1143
1144 if (info->num_clks == 1)
1145 return;
1146
1147 ucon = rd_regl(port, S3C2410_UCON);
1148 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1149 return;
1150
1151 ucon &= ~info->clksel_mask;
1152 ucon |= clk_sel << info->clksel_shift;
1153 wr_regl(port, S3C2410_UCON, ucon);
1154 }
1155
1156 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1157 unsigned int req_baud, struct clk **best_clk,
1158 unsigned int *clk_num)
1159 {
1160 struct s3c24xx_uart_info *info = ourport->info;
1161 struct clk *clk;
1162 unsigned long rate;
1163 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1164 char clkname[MAX_CLK_NAME_LENGTH];
1165 int calc_deviation, deviation = (1 << 30) - 1;
1166
1167 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1168 ourport->info->def_clk_sel;
1169 for (cnt = 0; cnt < info->num_clks; cnt++) {
1170 if (!(clk_sel & (1 << cnt)))
1171 continue;
1172
1173 sprintf(clkname, "clk_uart_baud%d", cnt);
1174 clk = clk_get(ourport->port.dev, clkname);
1175 if (IS_ERR(clk))
1176 continue;
1177
1178 rate = clk_get_rate(clk);
1179 if (!rate)
1180 continue;
1181
1182 if (ourport->info->has_divslot) {
1183 unsigned long div = rate / req_baud;
1184
1185 /* The UDIVSLOT register on the newer UARTs allows us to
1186 * get a divisor adjustment of 1/16th on the baud clock.
1187 *
1188 * We don't keep the UDIVSLOT value (the 16ths we
1189 * calculated by not multiplying the baud by 16) as it
1190 * is easy enough to recalculate.
1191 */
1192
1193 quot = div / 16;
1194 baud = rate / div;
1195 } else {
1196 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1197 baud = rate / (quot * 16);
1198 }
1199 quot--;
1200
1201 calc_deviation = req_baud - baud;
1202 if (calc_deviation < 0)
1203 calc_deviation = -calc_deviation;
1204
1205 if (calc_deviation < deviation) {
1206 *best_clk = clk;
1207 best_quot = quot;
1208 *clk_num = cnt;
1209 deviation = calc_deviation;
1210 }
1211 }
1212
1213 return best_quot;
1214 }
1215
1216 /* udivslot_table[]
1217 *
1218 * This table takes the fractional value of the baud divisor and gives
1219 * the recommended setting for the UDIVSLOT register.
1220 */
1221 static u16 udivslot_table[16] = {
1222 [0] = 0x0000,
1223 [1] = 0x0080,
1224 [2] = 0x0808,
1225 [3] = 0x0888,
1226 [4] = 0x2222,
1227 [5] = 0x4924,
1228 [6] = 0x4A52,
1229 [7] = 0x54AA,
1230 [8] = 0x5555,
1231 [9] = 0xD555,
1232 [10] = 0xD5D5,
1233 [11] = 0xDDD5,
1234 [12] = 0xDDDD,
1235 [13] = 0xDFDD,
1236 [14] = 0xDFDF,
1237 [15] = 0xFFDF,
1238 };
1239
1240 static void s3c24xx_serial_set_termios(struct uart_port *port,
1241 struct ktermios *termios,
1242 struct ktermios *old)
1243 {
1244 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1245 struct s3c24xx_uart_port *ourport = to_ourport(port);
1246 struct clk *clk = ERR_PTR(-EINVAL);
1247 unsigned long flags;
1248 unsigned int baud, quot, clk_sel = 0;
1249 unsigned int ulcon;
1250 unsigned int umcon;
1251 unsigned int udivslot = 0;
1252
1253 /*
1254 * We don't support modem control lines.
1255 */
1256 termios->c_cflag &= ~(HUPCL | CMSPAR);
1257 termios->c_cflag |= CLOCAL;
1258
1259 /*
1260 * Ask the core to calculate the divisor for us.
1261 */
1262
1263 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1264 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1265 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1266 quot = port->custom_divisor;
1267 if (IS_ERR(clk))
1268 return;
1269
1270 /* check to see if we need to change clock source */
1271
1272 if (ourport->baudclk != clk) {
1273 clk_prepare_enable(clk);
1274
1275 s3c24xx_serial_setsource(port, clk_sel);
1276
1277 if (!IS_ERR(ourport->baudclk)) {
1278 clk_disable_unprepare(ourport->baudclk);
1279 ourport->baudclk = ERR_PTR(-EINVAL);
1280 }
1281
1282 ourport->baudclk = clk;
1283 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1284 }
1285
1286 if (ourport->info->has_divslot) {
1287 unsigned int div = ourport->baudclk_rate / baud;
1288
1289 if (cfg->has_fracval) {
1290 udivslot = (div & 15);
1291 dbg("fracval = %04x\n", udivslot);
1292 } else {
1293 udivslot = udivslot_table[div & 15];
1294 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1295 }
1296 }
1297
1298 switch (termios->c_cflag & CSIZE) {
1299 case CS5:
1300 dbg("config: 5bits/char\n");
1301 ulcon = S3C2410_LCON_CS5;
1302 break;
1303 case CS6:
1304 dbg("config: 6bits/char\n");
1305 ulcon = S3C2410_LCON_CS6;
1306 break;
1307 case CS7:
1308 dbg("config: 7bits/char\n");
1309 ulcon = S3C2410_LCON_CS7;
1310 break;
1311 case CS8:
1312 default:
1313 dbg("config: 8bits/char\n");
1314 ulcon = S3C2410_LCON_CS8;
1315 break;
1316 }
1317
1318 /* preserve original lcon IR settings */
1319 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1320
1321 if (termios->c_cflag & CSTOPB)
1322 ulcon |= S3C2410_LCON_STOPB;
1323
1324 if (termios->c_cflag & PARENB) {
1325 if (termios->c_cflag & PARODD)
1326 ulcon |= S3C2410_LCON_PODD;
1327 else
1328 ulcon |= S3C2410_LCON_PEVEN;
1329 } else {
1330 ulcon |= S3C2410_LCON_PNONE;
1331 }
1332
1333 spin_lock_irqsave(&port->lock, flags);
1334
1335 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1336 ulcon, quot, udivslot);
1337
1338 wr_regl(port, S3C2410_ULCON, ulcon);
1339 wr_regl(port, S3C2410_UBRDIV, quot);
1340
1341 umcon = rd_regl(port, S3C2410_UMCON);
1342 if (termios->c_cflag & CRTSCTS) {
1343 umcon |= S3C2410_UMCOM_AFC;
1344 /* Disable RTS when RX FIFO contains 63 bytes */
1345 umcon &= ~S3C2412_UMCON_AFC_8;
1346 } else {
1347 umcon &= ~S3C2410_UMCOM_AFC;
1348 }
1349 wr_regl(port, S3C2410_UMCON, umcon);
1350
1351 if (ourport->info->has_divslot)
1352 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1353
1354 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1355 rd_regl(port, S3C2410_ULCON),
1356 rd_regl(port, S3C2410_UCON),
1357 rd_regl(port, S3C2410_UFCON));
1358
1359 /*
1360 * Update the per-port timeout.
1361 */
1362 uart_update_timeout(port, termios->c_cflag, baud);
1363
1364 /*
1365 * Which character status flags are we interested in?
1366 */
1367 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1368 if (termios->c_iflag & INPCK)
1369 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1370 S3C2410_UERSTAT_PARITY;
1371 /*
1372 * Which character status flags should we ignore?
1373 */
1374 port->ignore_status_mask = 0;
1375 if (termios->c_iflag & IGNPAR)
1376 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1377 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1378 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1379
1380 /*
1381 * Ignore all characters if CREAD is not set.
1382 */
1383 if ((termios->c_cflag & CREAD) == 0)
1384 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1385
1386 spin_unlock_irqrestore(&port->lock, flags);
1387 }
1388
1389 static const char *s3c24xx_serial_type(struct uart_port *port)
1390 {
1391 switch (port->type) {
1392 case PORT_S3C2410:
1393 return "S3C2410";
1394 case PORT_S3C2440:
1395 return "S3C2440";
1396 case PORT_S3C2412:
1397 return "S3C2412";
1398 case PORT_S3C6400:
1399 return "S3C6400/10";
1400 default:
1401 return NULL;
1402 }
1403 }
1404
1405 #define MAP_SIZE (0x100)
1406
1407 static void s3c24xx_serial_release_port(struct uart_port *port)
1408 {
1409 release_mem_region(port->mapbase, MAP_SIZE);
1410 }
1411
1412 static int s3c24xx_serial_request_port(struct uart_port *port)
1413 {
1414 const char *name = s3c24xx_serial_portname(port);
1415 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1416 }
1417
1418 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1419 {
1420 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1421
1422 if (flags & UART_CONFIG_TYPE &&
1423 s3c24xx_serial_request_port(port) == 0)
1424 port->type = info->type;
1425 }
1426
1427 /*
1428 * verify the new serial_struct (for TIOCSSERIAL).
1429 */
1430 static int
1431 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1432 {
1433 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1434
1435 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1436 return -EINVAL;
1437
1438 return 0;
1439 }
1440
1441
1442 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1443
1444 static struct console s3c24xx_serial_console;
1445
1446 static int __init s3c24xx_serial_console_init(void)
1447 {
1448 register_console(&s3c24xx_serial_console);
1449 return 0;
1450 }
1451 console_initcall(s3c24xx_serial_console_init);
1452
1453 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1454 #else
1455 #define S3C24XX_SERIAL_CONSOLE NULL
1456 #endif
1457
1458 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1459 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1460 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1461 unsigned char c);
1462 #endif
1463
1464 static struct uart_ops s3c24xx_serial_ops = {
1465 .pm = s3c24xx_serial_pm,
1466 .tx_empty = s3c24xx_serial_tx_empty,
1467 .get_mctrl = s3c24xx_serial_get_mctrl,
1468 .set_mctrl = s3c24xx_serial_set_mctrl,
1469 .stop_tx = s3c24xx_serial_stop_tx,
1470 .start_tx = s3c24xx_serial_start_tx,
1471 .stop_rx = s3c24xx_serial_stop_rx,
1472 .break_ctl = s3c24xx_serial_break_ctl,
1473 .startup = s3c24xx_serial_startup,
1474 .shutdown = s3c24xx_serial_shutdown,
1475 .set_termios = s3c24xx_serial_set_termios,
1476 .type = s3c24xx_serial_type,
1477 .release_port = s3c24xx_serial_release_port,
1478 .request_port = s3c24xx_serial_request_port,
1479 .config_port = s3c24xx_serial_config_port,
1480 .verify_port = s3c24xx_serial_verify_port,
1481 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1482 .poll_get_char = s3c24xx_serial_get_poll_char,
1483 .poll_put_char = s3c24xx_serial_put_poll_char,
1484 #endif
1485 };
1486
1487 static struct uart_driver s3c24xx_uart_drv = {
1488 .owner = THIS_MODULE,
1489 .driver_name = "s3c2410_serial",
1490 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1491 .cons = S3C24XX_SERIAL_CONSOLE,
1492 .dev_name = S3C24XX_SERIAL_NAME,
1493 .major = S3C24XX_SERIAL_MAJOR,
1494 .minor = S3C24XX_SERIAL_MINOR,
1495 };
1496
1497 #define __PORT_LOCK_UNLOCKED(i) \
1498 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1499 static struct s3c24xx_uart_port
1500 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1501 [0] = {
1502 .port = {
1503 .lock = __PORT_LOCK_UNLOCKED(0),
1504 .iotype = UPIO_MEM,
1505 .uartclk = 0,
1506 .fifosize = 16,
1507 .ops = &s3c24xx_serial_ops,
1508 .flags = UPF_BOOT_AUTOCONF,
1509 .line = 0,
1510 }
1511 },
1512 [1] = {
1513 .port = {
1514 .lock = __PORT_LOCK_UNLOCKED(1),
1515 .iotype = UPIO_MEM,
1516 .uartclk = 0,
1517 .fifosize = 16,
1518 .ops = &s3c24xx_serial_ops,
1519 .flags = UPF_BOOT_AUTOCONF,
1520 .line = 1,
1521 }
1522 },
1523 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1524
1525 [2] = {
1526 .port = {
1527 .lock = __PORT_LOCK_UNLOCKED(2),
1528 .iotype = UPIO_MEM,
1529 .uartclk = 0,
1530 .fifosize = 16,
1531 .ops = &s3c24xx_serial_ops,
1532 .flags = UPF_BOOT_AUTOCONF,
1533 .line = 2,
1534 }
1535 },
1536 #endif
1537 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1538 [3] = {
1539 .port = {
1540 .lock = __PORT_LOCK_UNLOCKED(3),
1541 .iotype = UPIO_MEM,
1542 .uartclk = 0,
1543 .fifosize = 16,
1544 .ops = &s3c24xx_serial_ops,
1545 .flags = UPF_BOOT_AUTOCONF,
1546 .line = 3,
1547 }
1548 }
1549 #endif
1550 };
1551 #undef __PORT_LOCK_UNLOCKED
1552
1553 /* s3c24xx_serial_resetport
1554 *
1555 * reset the fifos and other the settings.
1556 */
1557
1558 static void s3c24xx_serial_resetport(struct uart_port *port,
1559 struct s3c2410_uartcfg *cfg)
1560 {
1561 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1562 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1563 unsigned int ucon_mask;
1564
1565 ucon_mask = info->clksel_mask;
1566 if (info->type == PORT_S3C2440)
1567 ucon_mask |= S3C2440_UCON0_DIVMASK;
1568
1569 ucon &= ucon_mask;
1570 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1571
1572 /* reset both fifos */
1573 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1574 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1575
1576 /* some delay is required after fifo reset */
1577 udelay(1);
1578 }
1579
1580
1581 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1582
1583 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1584 unsigned long val, void *data)
1585 {
1586 struct s3c24xx_uart_port *port;
1587 struct uart_port *uport;
1588
1589 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1590 uport = &port->port;
1591
1592 /* check to see if port is enabled */
1593
1594 if (port->pm_level != 0)
1595 return 0;
1596
1597 /* try and work out if the baudrate is changing, we can detect
1598 * a change in rate, but we do not have support for detecting
1599 * a disturbance in the clock-rate over the change.
1600 */
1601
1602 if (IS_ERR(port->baudclk))
1603 goto exit;
1604
1605 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1606 goto exit;
1607
1608 if (val == CPUFREQ_PRECHANGE) {
1609 /* we should really shut the port down whilst the
1610 * frequency change is in progress. */
1611
1612 } else if (val == CPUFREQ_POSTCHANGE) {
1613 struct ktermios *termios;
1614 struct tty_struct *tty;
1615
1616 if (uport->state == NULL)
1617 goto exit;
1618
1619 tty = uport->state->port.tty;
1620
1621 if (tty == NULL)
1622 goto exit;
1623
1624 termios = &tty->termios;
1625
1626 if (termios == NULL) {
1627 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1628 goto exit;
1629 }
1630
1631 s3c24xx_serial_set_termios(uport, termios, NULL);
1632 }
1633
1634 exit:
1635 return 0;
1636 }
1637
1638 static inline int
1639 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1640 {
1641 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1642
1643 return cpufreq_register_notifier(&port->freq_transition,
1644 CPUFREQ_TRANSITION_NOTIFIER);
1645 }
1646
1647 static inline void
1648 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1649 {
1650 cpufreq_unregister_notifier(&port->freq_transition,
1651 CPUFREQ_TRANSITION_NOTIFIER);
1652 }
1653
1654 #else
1655 static inline int
1656 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1657 {
1658 return 0;
1659 }
1660
1661 static inline void
1662 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1663 {
1664 }
1665 #endif
1666
1667 /* s3c24xx_serial_init_port
1668 *
1669 * initialise a single serial port from the platform device given
1670 */
1671
1672 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1673 struct platform_device *platdev)
1674 {
1675 struct uart_port *port = &ourport->port;
1676 struct s3c2410_uartcfg *cfg = ourport->cfg;
1677 struct resource *res;
1678 int ret;
1679
1680 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1681
1682 if (platdev == NULL)
1683 return -ENODEV;
1684
1685 if (port->mapbase != 0)
1686 return -EINVAL;
1687
1688 /* setup info for port */
1689 port->dev = &platdev->dev;
1690
1691 /* Startup sequence is different for s3c64xx and higher SoC's */
1692 if (s3c24xx_serial_has_interrupt_mask(port))
1693 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1694
1695 port->uartclk = 1;
1696
1697 if (cfg->uart_flags & UPF_CONS_FLOW) {
1698 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1699 port->flags |= UPF_CONS_FLOW;
1700 }
1701
1702 /* sort our the physical and virtual addresses for each UART */
1703
1704 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1705 if (res == NULL) {
1706 dev_err(port->dev, "failed to find memory resource for uart\n");
1707 return -EINVAL;
1708 }
1709
1710 dbg("resource %pR)\n", res);
1711
1712 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1713 if (!port->membase) {
1714 dev_err(port->dev, "failed to remap controller address\n");
1715 return -EBUSY;
1716 }
1717
1718 port->mapbase = res->start;
1719 ret = platform_get_irq(platdev, 0);
1720 if (ret < 0)
1721 port->irq = 0;
1722 else {
1723 port->irq = ret;
1724 ourport->rx_irq = ret;
1725 ourport->tx_irq = ret + 1;
1726 }
1727
1728 ret = platform_get_irq(platdev, 1);
1729 if (ret > 0)
1730 ourport->tx_irq = ret;
1731 /*
1732 * DMA is currently supported only on DT platforms, if DMA properties
1733 * are specified.
1734 */
1735 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1736 "dmas", NULL)) {
1737 ourport->dma = devm_kzalloc(port->dev,
1738 sizeof(*ourport->dma),
1739 GFP_KERNEL);
1740 if (!ourport->dma) {
1741 ret = -ENOMEM;
1742 goto err;
1743 }
1744 }
1745
1746 ourport->clk = clk_get(&platdev->dev, "uart");
1747 if (IS_ERR(ourport->clk)) {
1748 pr_err("%s: Controller clock not found\n",
1749 dev_name(&platdev->dev));
1750 ret = PTR_ERR(ourport->clk);
1751 goto err;
1752 }
1753
1754 ret = clk_prepare_enable(ourport->clk);
1755 if (ret) {
1756 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1757 clk_put(ourport->clk);
1758 goto err;
1759 }
1760
1761 /* Keep all interrupts masked and cleared */
1762 if (s3c24xx_serial_has_interrupt_mask(port)) {
1763 wr_regl(port, S3C64XX_UINTM, 0xf);
1764 wr_regl(port, S3C64XX_UINTP, 0xf);
1765 wr_regl(port, S3C64XX_UINTSP, 0xf);
1766 }
1767
1768 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1769 &port->mapbase, port->membase, port->irq,
1770 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1771
1772 /* reset the fifos (and setup the uart) */
1773 s3c24xx_serial_resetport(port, cfg);
1774
1775 return 0;
1776
1777 err:
1778 port->mapbase = 0;
1779 return ret;
1780 }
1781
1782 /* Device driver serial port probe */
1783
1784 static const struct of_device_id s3c24xx_uart_dt_match[];
1785 static int probe_index;
1786
1787 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1788 struct platform_device *pdev)
1789 {
1790 #ifdef CONFIG_OF
1791 if (pdev->dev.of_node) {
1792 const struct of_device_id *match;
1793 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1794 return (struct s3c24xx_serial_drv_data *)match->data;
1795 }
1796 #endif
1797 return (struct s3c24xx_serial_drv_data *)
1798 platform_get_device_id(pdev)->driver_data;
1799 }
1800
1801 static int s3c24xx_serial_probe(struct platform_device *pdev)
1802 {
1803 struct device_node *np = pdev->dev.of_node;
1804 struct s3c24xx_uart_port *ourport;
1805 int index = probe_index;
1806 int ret;
1807
1808 if (np) {
1809 ret = of_alias_get_id(np, "serial");
1810 if (ret >= 0)
1811 index = ret;
1812 }
1813
1814 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1815
1816 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1817 dev_err(&pdev->dev, "serial%d out of range\n", index);
1818 return -EINVAL;
1819 }
1820 ourport = &s3c24xx_serial_ports[index];
1821
1822 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1823 if (!ourport->drv_data) {
1824 dev_err(&pdev->dev, "could not find driver data\n");
1825 return -ENODEV;
1826 }
1827
1828 ourport->baudclk = ERR_PTR(-EINVAL);
1829 ourport->info = ourport->drv_data->info;
1830 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1831 dev_get_platdata(&pdev->dev) :
1832 ourport->drv_data->def_cfg;
1833
1834 if (np)
1835 of_property_read_u32(np,
1836 "samsung,uart-fifosize", &ourport->port.fifosize);
1837
1838 if (ourport->drv_data->fifosize[index])
1839 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1840 else if (ourport->info->fifosize)
1841 ourport->port.fifosize = ourport->info->fifosize;
1842
1843 /*
1844 * DMA transfers must be aligned at least to cache line size,
1845 * so find minimal transfer size suitable for DMA mode
1846 */
1847 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1848 dma_get_cache_alignment());
1849
1850 dbg("%s: initialising port %p...\n", __func__, ourport);
1851
1852 ret = s3c24xx_serial_init_port(ourport, pdev);
1853 if (ret < 0)
1854 return ret;
1855
1856 if (!s3c24xx_uart_drv.state) {
1857 ret = uart_register_driver(&s3c24xx_uart_drv);
1858 if (ret < 0) {
1859 pr_err("Failed to register Samsung UART driver\n");
1860 return ret;
1861 }
1862 }
1863
1864 dbg("%s: adding port\n", __func__);
1865 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1866 platform_set_drvdata(pdev, &ourport->port);
1867
1868 /*
1869 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1870 * so that a potential re-enablement through the pm-callback overlaps
1871 * and keeps the clock enabled in this case.
1872 */
1873 clk_disable_unprepare(ourport->clk);
1874
1875 ret = s3c24xx_serial_cpufreq_register(ourport);
1876 if (ret < 0)
1877 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1878
1879 probe_index++;
1880
1881 return 0;
1882 }
1883
1884 static int s3c24xx_serial_remove(struct platform_device *dev)
1885 {
1886 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1887
1888 if (port) {
1889 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1890 uart_remove_one_port(&s3c24xx_uart_drv, port);
1891 }
1892
1893 uart_unregister_driver(&s3c24xx_uart_drv);
1894
1895 return 0;
1896 }
1897
1898 /* UART power management code */
1899 #ifdef CONFIG_PM_SLEEP
1900 static int s3c24xx_serial_suspend(struct device *dev)
1901 {
1902 struct uart_port *port = s3c24xx_dev_to_port(dev);
1903
1904 if (port)
1905 uart_suspend_port(&s3c24xx_uart_drv, port);
1906
1907 return 0;
1908 }
1909
1910 static int s3c24xx_serial_resume(struct device *dev)
1911 {
1912 struct uart_port *port = s3c24xx_dev_to_port(dev);
1913 struct s3c24xx_uart_port *ourport = to_ourport(port);
1914
1915 if (port) {
1916 clk_prepare_enable(ourport->clk);
1917 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1918 clk_disable_unprepare(ourport->clk);
1919
1920 uart_resume_port(&s3c24xx_uart_drv, port);
1921 }
1922
1923 return 0;
1924 }
1925
1926 static int s3c24xx_serial_resume_noirq(struct device *dev)
1927 {
1928 struct uart_port *port = s3c24xx_dev_to_port(dev);
1929
1930 if (port) {
1931 /* restore IRQ mask */
1932 if (s3c24xx_serial_has_interrupt_mask(port)) {
1933 unsigned int uintm = 0xf;
1934 if (tx_enabled(port))
1935 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1936 if (rx_enabled(port))
1937 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1938 wr_regl(port, S3C64XX_UINTM, uintm);
1939 }
1940 }
1941
1942 return 0;
1943 }
1944
1945 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1946 .suspend = s3c24xx_serial_suspend,
1947 .resume = s3c24xx_serial_resume,
1948 .resume_noirq = s3c24xx_serial_resume_noirq,
1949 };
1950 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1951
1952 #else /* !CONFIG_PM_SLEEP */
1953
1954 #define SERIAL_SAMSUNG_PM_OPS NULL
1955 #endif /* CONFIG_PM_SLEEP */
1956
1957 /* Console code */
1958
1959 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1960
1961 static struct uart_port *cons_uart;
1962
1963 static int
1964 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1965 {
1966 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1967 unsigned long ufstat, utrstat;
1968
1969 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1970 /* fifo mode - check amount of data in fifo registers... */
1971
1972 ufstat = rd_regl(port, S3C2410_UFSTAT);
1973 return (ufstat & info->tx_fifofull) ? 0 : 1;
1974 }
1975
1976 /* in non-fifo mode, we go and use the tx buffer empty */
1977
1978 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1979 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1980 }
1981
1982 static bool
1983 s3c24xx_port_configured(unsigned int ucon)
1984 {
1985 /* consider the serial port configured if the tx/rx mode set */
1986 return (ucon & 0xf) != 0;
1987 }
1988
1989 #ifdef CONFIG_CONSOLE_POLL
1990 /*
1991 * Console polling routines for writing and reading from the uart while
1992 * in an interrupt or debug context.
1993 */
1994
1995 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1996 {
1997 struct s3c24xx_uart_port *ourport = to_ourport(port);
1998 unsigned int ufstat;
1999
2000 ufstat = rd_regl(port, S3C2410_UFSTAT);
2001 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2002 return NO_POLL_CHAR;
2003
2004 return rd_regb(port, S3C2410_URXH);
2005 }
2006
2007 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2008 unsigned char c)
2009 {
2010 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2011 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2012
2013 /* not possible to xmit on unconfigured port */
2014 if (!s3c24xx_port_configured(ucon))
2015 return;
2016
2017 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2018 cpu_relax();
2019 wr_regb(port, S3C2410_UTXH, c);
2020 }
2021
2022 #endif /* CONFIG_CONSOLE_POLL */
2023
2024 static void
2025 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2026 {
2027 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2028
2029 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2030 cpu_relax();
2031 wr_regb(port, S3C2410_UTXH, ch);
2032 }
2033
2034 static void
2035 s3c24xx_serial_console_write(struct console *co, const char *s,
2036 unsigned int count)
2037 {
2038 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2039
2040 /* not possible to xmit on unconfigured port */
2041 if (!s3c24xx_port_configured(ucon))
2042 return;
2043
2044 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2045 }
2046
2047 static void __init
2048 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2049 int *parity, int *bits)
2050 {
2051 struct clk *clk;
2052 unsigned int ulcon;
2053 unsigned int ucon;
2054 unsigned int ubrdiv;
2055 unsigned long rate;
2056 unsigned int clk_sel;
2057 char clk_name[MAX_CLK_NAME_LENGTH];
2058
2059 ulcon = rd_regl(port, S3C2410_ULCON);
2060 ucon = rd_regl(port, S3C2410_UCON);
2061 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2062
2063 dbg("s3c24xx_serial_get_options: port=%p\n"
2064 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2065 port, ulcon, ucon, ubrdiv);
2066
2067 if (s3c24xx_port_configured(ucon)) {
2068 switch (ulcon & S3C2410_LCON_CSMASK) {
2069 case S3C2410_LCON_CS5:
2070 *bits = 5;
2071 break;
2072 case S3C2410_LCON_CS6:
2073 *bits = 6;
2074 break;
2075 case S3C2410_LCON_CS7:
2076 *bits = 7;
2077 break;
2078 case S3C2410_LCON_CS8:
2079 default:
2080 *bits = 8;
2081 break;
2082 }
2083
2084 switch (ulcon & S3C2410_LCON_PMASK) {
2085 case S3C2410_LCON_PEVEN:
2086 *parity = 'e';
2087 break;
2088
2089 case S3C2410_LCON_PODD:
2090 *parity = 'o';
2091 break;
2092
2093 case S3C2410_LCON_PNONE:
2094 default:
2095 *parity = 'n';
2096 }
2097
2098 /* now calculate the baud rate */
2099
2100 clk_sel = s3c24xx_serial_getsource(port);
2101 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2102
2103 clk = clk_get(port->dev, clk_name);
2104 if (!IS_ERR(clk))
2105 rate = clk_get_rate(clk);
2106 else
2107 rate = 1;
2108
2109 *baud = rate / (16 * (ubrdiv + 1));
2110 dbg("calculated baud %d\n", *baud);
2111 }
2112
2113 }
2114
2115 static int __init
2116 s3c24xx_serial_console_setup(struct console *co, char *options)
2117 {
2118 struct uart_port *port;
2119 int baud = 9600;
2120 int bits = 8;
2121 int parity = 'n';
2122 int flow = 'n';
2123
2124 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2125 co, co->index, options);
2126
2127 /* is this a valid port */
2128
2129 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2130 co->index = 0;
2131
2132 port = &s3c24xx_serial_ports[co->index].port;
2133
2134 /* is the port configured? */
2135
2136 if (port->mapbase == 0x0)
2137 return -ENODEV;
2138
2139 cons_uart = port;
2140
2141 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2142
2143 /*
2144 * Check whether an invalid uart number has been specified, and
2145 * if so, search for the first available port that does have
2146 * console support.
2147 */
2148 if (options)
2149 uart_parse_options(options, &baud, &parity, &bits, &flow);
2150 else
2151 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2152
2153 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2154
2155 return uart_set_options(port, co, baud, parity, bits, flow);
2156 }
2157
2158 static struct console s3c24xx_serial_console = {
2159 .name = S3C24XX_SERIAL_NAME,
2160 .device = uart_console_device,
2161 .flags = CON_PRINTBUFFER,
2162 .index = -1,
2163 .write = s3c24xx_serial_console_write,
2164 .setup = s3c24xx_serial_console_setup,
2165 .data = &s3c24xx_uart_drv,
2166 };
2167 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2168
2169 #ifdef CONFIG_CPU_S3C2410
2170 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2171 .info = &(struct s3c24xx_uart_info) {
2172 .name = "Samsung S3C2410 UART",
2173 .type = PORT_S3C2410,
2174 .fifosize = 16,
2175 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2176 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2177 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2178 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2179 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2180 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2181 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2182 .num_clks = 2,
2183 .clksel_mask = S3C2410_UCON_CLKMASK,
2184 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2185 },
2186 .def_cfg = &(struct s3c2410_uartcfg) {
2187 .ucon = S3C2410_UCON_DEFAULT,
2188 .ufcon = S3C2410_UFCON_DEFAULT,
2189 },
2190 };
2191 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2192 #else
2193 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2194 #endif
2195
2196 #ifdef CONFIG_CPU_S3C2412
2197 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2198 .info = &(struct s3c24xx_uart_info) {
2199 .name = "Samsung S3C2412 UART",
2200 .type = PORT_S3C2412,
2201 .fifosize = 64,
2202 .has_divslot = 1,
2203 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2204 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2205 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2206 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2207 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2208 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2209 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2210 .num_clks = 4,
2211 .clksel_mask = S3C2412_UCON_CLKMASK,
2212 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2213 },
2214 .def_cfg = &(struct s3c2410_uartcfg) {
2215 .ucon = S3C2410_UCON_DEFAULT,
2216 .ufcon = S3C2410_UFCON_DEFAULT,
2217 },
2218 };
2219 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2220 #else
2221 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2222 #endif
2223
2224 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2225 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2226 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2227 .info = &(struct s3c24xx_uart_info) {
2228 .name = "Samsung S3C2440 UART",
2229 .type = PORT_S3C2440,
2230 .fifosize = 64,
2231 .has_divslot = 1,
2232 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2233 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2234 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2235 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2236 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2237 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2238 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2239 .num_clks = 4,
2240 .clksel_mask = S3C2412_UCON_CLKMASK,
2241 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2242 },
2243 .def_cfg = &(struct s3c2410_uartcfg) {
2244 .ucon = S3C2410_UCON_DEFAULT,
2245 .ufcon = S3C2410_UFCON_DEFAULT,
2246 },
2247 };
2248 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2249 #else
2250 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2251 #endif
2252
2253 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2254 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2255 .info = &(struct s3c24xx_uart_info) {
2256 .name = "Samsung S3C6400 UART",
2257 .type = PORT_S3C6400,
2258 .fifosize = 64,
2259 .has_divslot = 1,
2260 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2261 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2262 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2263 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2264 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2265 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2266 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2267 .num_clks = 4,
2268 .clksel_mask = S3C6400_UCON_CLKMASK,
2269 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2270 },
2271 .def_cfg = &(struct s3c2410_uartcfg) {
2272 .ucon = S3C2410_UCON_DEFAULT,
2273 .ufcon = S3C2410_UFCON_DEFAULT,
2274 },
2275 };
2276 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2277 #else
2278 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2279 #endif
2280
2281 #ifdef CONFIG_CPU_S5PV210
2282 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2283 .info = &(struct s3c24xx_uart_info) {
2284 .name = "Samsung S5PV210 UART",
2285 .type = PORT_S3C6400,
2286 .has_divslot = 1,
2287 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2288 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2289 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2290 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2291 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2292 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2293 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2294 .num_clks = 2,
2295 .clksel_mask = S5PV210_UCON_CLKMASK,
2296 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2297 },
2298 .def_cfg = &(struct s3c2410_uartcfg) {
2299 .ucon = S5PV210_UCON_DEFAULT,
2300 .ufcon = S5PV210_UFCON_DEFAULT,
2301 },
2302 .fifosize = { 256, 64, 16, 16 },
2303 };
2304 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2305 #else
2306 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2307 #endif
2308
2309 #if defined(CONFIG_ARCH_EXYNOS)
2310 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2311 .info = &(struct s3c24xx_uart_info) { \
2312 .name = "Samsung Exynos UART", \
2313 .type = PORT_S3C6400, \
2314 .has_divslot = 1, \
2315 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2316 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2317 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2318 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2319 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2320 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2321 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2322 .num_clks = 1, \
2323 .clksel_mask = 0, \
2324 .clksel_shift = 0, \
2325 }, \
2326 .def_cfg = &(struct s3c2410_uartcfg) { \
2327 .ucon = S5PV210_UCON_DEFAULT, \
2328 .ufcon = S5PV210_UFCON_DEFAULT, \
2329 .has_fracval = 1, \
2330 } \
2331
2332 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2333 EXYNOS_COMMON_SERIAL_DRV_DATA,
2334 .fifosize = { 256, 64, 16, 16 },
2335 };
2336
2337 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2338 EXYNOS_COMMON_SERIAL_DRV_DATA,
2339 .fifosize = { 64, 256, 16, 256 },
2340 };
2341
2342 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2343 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2344 #else
2345 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2346 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2347 #endif
2348
2349 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2350 {
2351 .name = "s3c2410-uart",
2352 .driver_data = S3C2410_SERIAL_DRV_DATA,
2353 }, {
2354 .name = "s3c2412-uart",
2355 .driver_data = S3C2412_SERIAL_DRV_DATA,
2356 }, {
2357 .name = "s3c2440-uart",
2358 .driver_data = S3C2440_SERIAL_DRV_DATA,
2359 }, {
2360 .name = "s3c6400-uart",
2361 .driver_data = S3C6400_SERIAL_DRV_DATA,
2362 }, {
2363 .name = "s5pv210-uart",
2364 .driver_data = S5PV210_SERIAL_DRV_DATA,
2365 }, {
2366 .name = "exynos4210-uart",
2367 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2368 }, {
2369 .name = "exynos5433-uart",
2370 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2371 },
2372 { },
2373 };
2374 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2375
2376 #ifdef CONFIG_OF
2377 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2378 { .compatible = "samsung,s3c2410-uart",
2379 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2380 { .compatible = "samsung,s3c2412-uart",
2381 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2382 { .compatible = "samsung,s3c2440-uart",
2383 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2384 { .compatible = "samsung,s3c6400-uart",
2385 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2386 { .compatible = "samsung,s5pv210-uart",
2387 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2388 { .compatible = "samsung,exynos4210-uart",
2389 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2390 { .compatible = "samsung,exynos5433-uart",
2391 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2392 {},
2393 };
2394 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2395 #endif
2396
2397 static struct platform_driver samsung_serial_driver = {
2398 .probe = s3c24xx_serial_probe,
2399 .remove = s3c24xx_serial_remove,
2400 .id_table = s3c24xx_serial_driver_ids,
2401 .driver = {
2402 .name = "samsung-uart",
2403 .pm = SERIAL_SAMSUNG_PM_OPS,
2404 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2405 },
2406 };
2407
2408 module_platform_driver(samsung_serial_driver);
2409
2410 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2411 /*
2412 * Early console.
2413 */
2414
2415 struct samsung_early_console_data {
2416 u32 txfull_mask;
2417 };
2418
2419 static void samsung_early_busyuart(struct uart_port *port)
2420 {
2421 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2422 ;
2423 }
2424
2425 static void samsung_early_busyuart_fifo(struct uart_port *port)
2426 {
2427 struct samsung_early_console_data *data = port->private_data;
2428
2429 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2430 ;
2431 }
2432
2433 static void samsung_early_putc(struct uart_port *port, int c)
2434 {
2435 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2436 samsung_early_busyuart_fifo(port);
2437 else
2438 samsung_early_busyuart(port);
2439
2440 writeb(c, port->membase + S3C2410_UTXH);
2441 }
2442
2443 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2444 {
2445 struct earlycon_device *dev = con->data;
2446
2447 uart_console_write(&dev->port, s, n, samsung_early_putc);
2448 }
2449
2450 static int __init samsung_early_console_setup(struct earlycon_device *device,
2451 const char *opt)
2452 {
2453 if (!device->port.membase)
2454 return -ENODEV;
2455
2456 device->con->write = samsung_early_write;
2457 return 0;
2458 }
2459
2460 /* S3C2410 */
2461 static struct samsung_early_console_data s3c2410_early_console_data = {
2462 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2463 };
2464
2465 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2466 const char *opt)
2467 {
2468 device->port.private_data = &s3c2410_early_console_data;
2469 return samsung_early_console_setup(device, opt);
2470 }
2471 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2472 s3c2410_early_console_setup);
2473
2474 /* S3C2412, S3C2440, S3C64xx */
2475 static struct samsung_early_console_data s3c2440_early_console_data = {
2476 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2477 };
2478
2479 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2480 const char *opt)
2481 {
2482 device->port.private_data = &s3c2440_early_console_data;
2483 return samsung_early_console_setup(device, opt);
2484 }
2485 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2486 s3c2440_early_console_setup);
2487 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2488 s3c2440_early_console_setup);
2489 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2490 s3c2440_early_console_setup);
2491
2492 /* S5PV210, EXYNOS */
2493 static struct samsung_early_console_data s5pv210_early_console_data = {
2494 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2495 };
2496
2497 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2498 const char *opt)
2499 {
2500 device->port.private_data = &s5pv210_early_console_data;
2501 return samsung_early_console_setup(device, opt);
2502 }
2503 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2504 s5pv210_early_console_setup);
2505 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2506 s5pv210_early_console_setup);
2507 #endif
2508
2509 MODULE_ALIAS("platform:samsung-uart");
2510 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2511 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2512 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support