include/uapi/drm/msm_drm.h

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __MSM_DRM_H__
  19 #define __MSM_DRM_H__
  20
  21 #include <stddef.h>
  22 #include <drm/drm.h>
  23
  24 /* Please note that modifications to all structs defined here are
  25  * subject to backwards-compatibility constraints:
  26  *  1) Do not use pointers, use uint64_t instead for 32 bit / 64 bit
  27  *     user/kernel compatibility
  28  *  2) Keep fields aligned to their size
  29  *  3) Because of how drm_ioctl() works, we can add new fields at
  30  *     the end of an ioctl if some care is taken: drm_ioctl() will
  31  *     zero out the new fields at the tail of the ioctl, so a zero
  32  *     value should have a backwards compatible meaning.  And for
  33  *     output params, userspace won't see the newly added output
  34  *     fields.. so that has to be somehow ok.
  35  */
  36
  37 #define MSM_PIPE_NONE        0x00
  38 #define MSM_PIPE_2D0         0x01
  39 #define MSM_PIPE_2D1         0x02
  40 #define MSM_PIPE_3D0         0x10
  41
  42 /* timeouts are specified in clock-monotonic absolute times (to simplify
  43  * restarting interrupted ioctls).  The following struct is logically the
  44  * same as 'struct timespec' but 32/64b ABI safe.
  45  */
  46 struct drm_msm_timespec {
  47         int64_t tv_sec;          /* seconds */
  48         int64_t tv_nsec;         /* nanoseconds */
  49 };
  50
  51 #define MSM_PARAM_GPU_ID     0x01
  52 #define MSM_PARAM_GMEM_SIZE  0x02
  53
  54 struct drm_msm_param {
  55         uint32_t pipe;           /* in, MSM_PIPE_x */
  56         uint32_t param;          /* in, MSM_PARAM_x */
  57         uint64_t value;          /* out (get_param) or in (set_param) */
  58 };
  59
  60 /*
  61  * GEM buffers:
  62  */
  63
  64 #define MSM_BO_SCANOUT       0x00000001     /* scanout capable */
  65 #define MSM_BO_GPU_READONLY  0x00000002
  66 #define MSM_BO_CACHE_MASK    0x000f0000
  67 /* cache modes */
  68 #define MSM_BO_CACHED        0x00010000
  69 #define MSM_BO_WC            0x00020000
  70 #define MSM_BO_UNCACHED      0x00040000
  71
  72 struct drm_msm_gem_new {
  73         uint64_t size;           /* in */
  74         uint32_t flags;          /* in, mask of MSM_BO_x */
  75         uint32_t handle;         /* out */
  76 };
  77
  78 struct drm_msm_gem_info {
  79         uint32_t handle;         /* in */
  80         uint32_t pad;
  81         uint64_t offset;         /* out, offset to pass to mmap() */
  82 };
  83
  84 #define MSM_PREP_READ        0x01
  85 #define MSM_PREP_WRITE       0x02
  86 #define MSM_PREP_NOSYNC      0x04
  87
  88 struct drm_msm_gem_cpu_prep {
  89         uint32_t handle;         /* in */
  90         uint32_t op;             /* in, mask of MSM_PREP_x */
  91         struct drm_msm_timespec timeout;   /* in */
  92 };
  93
  94 struct drm_msm_gem_cpu_fini {
  95         uint32_t handle;         /* in */
  96 };
  97
  98 /*
  99  * Cmdstream Submission:
 100  */
 101
 102 /* The value written into the cmdstream is logically:
 103  *
 104  *   ((relocbuf->gpuaddr + reloc_offset) << shift) | or
 105  *
 106  * When we have GPU's w/ >32bit ptrs, it should be possible to deal
 107  * with this by emit'ing two reloc entries with appropriate shift
 108  * values.  Or a new MSM_SUBMIT_CMD_x type would also be an option.
 109  *
 110  * NOTE that reloc's must be sorted by order of increasing submit_offset,
 111  * otherwise EINVAL.
 112  */
 113 struct drm_msm_gem_submit_reloc {
 114         uint32_t submit_offset;  /* in, offset from submit_bo */
 115         uint32_t or;             /* in, value OR'd with result */
 116         int32_t  shift;          /* in, amount of left shift (can be negative) */
 117         uint32_t reloc_idx;      /* in, index of reloc_bo buffer */
 118         uint64_t reloc_offset;   /* in, offset from start of reloc_bo */
 119 };
 120
 121 /* submit-types:
 122  *   BUF - this cmd buffer is executed normally.
 123  *   IB_TARGET_BUF - this cmd buffer is an IB target.  Reloc's are
 124  *      processed normally, but the kernel does not setup an IB to
 125  *      this buffer in the first-level ringbuffer
 126  *   CTX_RESTORE_BUF - only executed if there has been a GPU context
 127  *      switch since the last SUBMIT ioctl
 128  */
 129 #define MSM_SUBMIT_CMD_BUF             0x0001
 130 #define MSM_SUBMIT_CMD_IB_TARGET_BUF   0x0002
 131 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
 132 struct drm_msm_gem_submit_cmd {
 133         uint32_t type;           /* in, one of MSM_SUBMIT_CMD_x */
 134         uint32_t submit_idx;     /* in, index of submit_bo cmdstream buffer */
 135         uint32_t submit_offset;  /* in, offset into submit_bo */
 136         uint32_t size;           /* in, cmdstream size */
 137         uint32_t pad;
 138         uint32_t nr_relocs;      /* in, number of submit_reloc's */
 139         uint64_t __user relocs;  /* in, ptr to array of submit_reloc's */
 140 };
 141
 142 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
 143  * cmdstream buffer(s) themselves or reloc entries) has one (and only
 144  * one) entry in the submit->bos[] table.
 145  *
 146  * As a optimization, the current buffer (gpu virtual address) can be
 147  * passed back through the 'presumed' field.  If on a subsequent reloc,
 148  * userspace passes back a 'presumed' address that is still valid,
 149  * then patching the cmdstream for this entry is skipped.  This can
 150  * avoid kernel needing to map/access the cmdstream bo in the common
 151  * case.
 152  */
 153 #define MSM_SUBMIT_BO_READ             0x0001
 154 #define MSM_SUBMIT_BO_WRITE            0x0002
 155 struct drm_msm_gem_submit_bo {
 156         uint32_t flags;          /* in, mask of MSM_SUBMIT_BO_x */
 157         uint32_t handle;         /* in, GEM handle */
 158         uint64_t presumed;       /* in/out, presumed buffer address */
 159 };
 160
 161 /* Each cmdstream submit consists of a table of buffers involved, and
 162  * one or more cmdstream buffers.  This allows for conditional execution
 163  * (context-restore), and IB buffers needed for per tile/bin draw cmds.
 164  */
 165 struct drm_msm_gem_submit {
 166         uint32_t pipe;           /* in, MSM_PIPE_x */
 167         uint32_t fence;          /* out */
 168         uint32_t nr_bos;         /* in, number of submit_bo's */
 169         uint32_t nr_cmds;        /* in, number of submit_cmd's */
 170         uint64_t __user bos;     /* in, ptr to array of submit_bo's */
 171         uint64_t __user cmds;    /* in, ptr to array of submit_cmd's */
 172 };
 173
 174 /* The normal way to synchronize with the GPU is just to CPU_PREP on
 175  * a buffer if you need to access it from the CPU (other cmdstream
 176  * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
 177  * handle the required synchronization under the hood).  This ioctl
 178  * mainly just exists as a way to implement the gallium pipe_fence
 179  * APIs without requiring a dummy bo to synchronize on.
 180  */
 181 struct drm_msm_wait_fence {
 182         uint32_t fence;          /* in */
 183         uint32_t pad;
 184         struct drm_msm_timespec timeout;   /* in */
 185 };
 186
 187 #define DRM_MSM_GET_PARAM              0x00
 188 /* placeholder:
 189 #define DRM_MSM_SET_PARAM              0x01
 190  */
 191 #define DRM_MSM_GEM_NEW                0x02
 192 #define DRM_MSM_GEM_INFO               0x03
 193 #define DRM_MSM_GEM_CPU_PREP           0x04
 194 #define DRM_MSM_GEM_CPU_FINI           0x05
 195 #define DRM_MSM_GEM_SUBMIT             0x06
 196 #define DRM_MSM_WAIT_FENCE             0x07
 197 #define DRM_MSM_NUM_IOCTLS             0x08
 198
 199 #define DRM_IOCTL_MSM_GET_PARAM        DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
 200 #define DRM_IOCTL_MSM_GEM_NEW          DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
 201 #define DRM_IOCTL_MSM_GEM_INFO         DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
 202 #define DRM_IOCTL_MSM_GEM_CPU_PREP     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
 203 #define DRM_IOCTL_MSM_GEM_CPU_FINI     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
 204 #define DRM_IOCTL_MSM_GEM_SUBMIT       DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
 205 #define DRM_IOCTL_MSM_WAIT_FENCE       DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
 206
 207 #endif /* __MSM_DRM_H__ */