include/uapi/drm/tegra_drm.h

   1 /*
   2  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef _UAPI_TEGRA_DRM_H_
  18 #define _UAPI_TEGRA_DRM_H_
  19
  20 #include <drm/drm.h>
  21
  22 struct drm_tegra_gem_create {
  23         __u64 size;
  24         __u32 flags;
  25         __u32 handle;
  26 };
  27
  28 struct drm_tegra_gem_mmap {
  29         __u32 handle;
  30         __u32 offset;
  31 };
  32
  33 struct drm_tegra_syncpt_read {
  34         __u32 id;
  35         __u32 value;
  36 };
  37
  38 struct drm_tegra_syncpt_incr {
  39         __u32 id;
  40         __u32 pad;
  41 };
  42
  43 struct drm_tegra_syncpt_wait {
  44         __u32 id;
  45         __u32 thresh;
  46         __u32 timeout;
  47         __u32 value;
  48 };
  49
  50 #define DRM_TEGRA_NO_TIMEOUT    (0xffffffff)
  51
  52 struct drm_tegra_open_channel {
  53         __u32 client;
  54         __u32 pad;
  55         __u64 context;
  56 };
  57
  58 struct drm_tegra_close_channel {
  59         __u64 context;
  60 };
  61
  62 struct drm_tegra_get_syncpt {
  63         __u64 context;
  64         __u32 index;
  65         __u32 id;
  66 };
  67
  68 struct drm_tegra_syncpt {
  69         __u32 id;
  70         __u32 incrs;
  71 };
  72
  73 struct drm_tegra_cmdbuf {
  74         __u32 handle;
  75         __u32 offset;
  76         __u32 words;
  77         __u32 pad;
  78 };
  79
  80 struct drm_tegra_reloc {
  81         struct {
  82                 __u32 handle;
  83                 __u32 offset;
  84         } cmdbuf;
  85         struct {
  86                 __u32 handle;
  87                 __u32 offset;
  88         } target;
  89         __u32 shift;
  90         __u32 pad;
  91 };
  92
  93 struct drm_tegra_waitchk {
  94         __u32 handle;
  95         __u32 offset;
  96         __u32 syncpt;
  97         __u32 thresh;
  98 };
  99
 100 struct drm_tegra_submit {
 101         __u64 context;
 102         __u32 num_syncpts;
 103         __u32 num_cmdbufs;
 104         __u32 num_relocs;
 105         __u32 num_waitchks;
 106         __u32 waitchk_mask;
 107         __u32 timeout;
 108         __u32 pad;
 109         __u64 syncpts;
 110         __u64 cmdbufs;
 111         __u64 relocs;
 112         __u64 waitchks;
 113         __u32 fence;            /* Return value */
 114
 115         __u32 reserved[5];      /* future expansion */
 116 };
 117
 118 #define DRM_TEGRA_GEM_CREATE    0x00
 119 #define DRM_TEGRA_GEM_MMAP      0x01
 120 #define DRM_TEGRA_SYNCPT_READ   0x02
 121 #define DRM_TEGRA_SYNCPT_INCR   0x03
 122 #define DRM_TEGRA_SYNCPT_WAIT   0x04
 123 #define DRM_TEGRA_OPEN_CHANNEL  0x05
 124 #define DRM_TEGRA_CLOSE_CHANNEL 0x06
 125 #define DRM_TEGRA_GET_SYNCPT    0x07
 126 #define DRM_TEGRA_SUBMIT        0x08
 127
 128 #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
 129 #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
 130 #define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
 131 #define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
 132 #define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
 133 #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
 134 #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
 135 #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
 136 #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
 137
 138 #endif