?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/omap: Fix error handling path in 'omap_dmm_probe()'
[linux/fpc-iii.git] / drivers / gpu / drm / ast / ast_mode.c
blob69d19f3304a5ea67529393200979ae27ba796822
1 /*
2 * Copyright 2012 Red Hat Inc.
3 * Parts based on xf86-video-ast
4 * Copyright (c) 2005 ASPEED Technology Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 *
26 */
27 /*
28 * Authors: Dave Airlie <airlied@redhat.com>
29 */
30 #include <linux/export.h>
31 #include <drm/drmP.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_plane_helper.h>
35 #include "ast_drv.h"
36
37 #include "ast_tables.h"
38
39 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
40 static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
41 static int ast_cursor_set(struct drm_crtc *crtc,
42 struct drm_file *file_priv,
43 uint32_t handle,
44 uint32_t width,
45 uint32_t height);
46 static int ast_cursor_move(struct drm_crtc *crtc,
47 int x, int y);
48
49 static inline void ast_load_palette_index(struct ast_private *ast,
50 u8 index, u8 red, u8 green,
51 u8 blue)
52 {
53 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
54 ast_io_read8(ast, AST_IO_SEQ_PORT);
55 ast_io_write8(ast, AST_IO_DAC_DATA, red);
56 ast_io_read8(ast, AST_IO_SEQ_PORT);
57 ast_io_write8(ast, AST_IO_DAC_DATA, green);
58 ast_io_read8(ast, AST_IO_SEQ_PORT);
59 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
60 ast_io_read8(ast, AST_IO_SEQ_PORT);
61 }
62
63 static void ast_crtc_load_lut(struct drm_crtc *crtc)
64 {
65 struct ast_private *ast = crtc->dev->dev_private;
66 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
67 int i;
68
69 if (!crtc->enabled)
70 return;
71
72 for (i = 0; i < 256; i++)
73 ast_load_palette_index(ast, i, ast_crtc->lut_r[i],
74 ast_crtc->lut_g[i], ast_crtc->lut_b[i]);
75 }
76
77 static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode,
79 struct ast_vbios_mode_info *vbios_mode)
80 {
81 struct ast_private *ast = crtc->dev->dev_private;
82 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate;
83 u32 hborder, vborder;
84 bool check_sync;
85 struct ast_vbios_enhtable *best = NULL;
86
87 switch (crtc->primary->fb->bits_per_pixel) {
88 case 8:
89 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
90 color_index = VGAModeIndex - 1;
91 break;
92 case 16:
93 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
94 color_index = HiCModeIndex;
95 break;
96 case 24:
97 case 32:
98 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
99 color_index = TrueCModeIndex;
100 break;
101 default:
102 return false;
103 }
104
105 switch (crtc->mode.crtc_hdisplay) {
106 case 640:
107 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
108 break;
109 case 800:
110 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
111 break;
112 case 1024:
113 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
114 break;
115 case 1280:
116 if (crtc->mode.crtc_vdisplay == 800)
117 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
118 else
119 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
120 break;
121 case 1360:
122 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
123 break;
124 case 1440:
125 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
126 break;
127 case 1600:
128 if (crtc->mode.crtc_vdisplay == 900)
129 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
130 else
131 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
132 break;
133 case 1680:
134 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
135 break;
136 case 1920:
137 if (crtc->mode.crtc_vdisplay == 1080)
138 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
139 else
140 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
141 break;
142 default:
143 return false;
144 }
145
146 refresh_rate = drm_mode_vrefresh(mode);
147 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
148 do {
149 struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
150
151 while (loop->refresh_rate != 0xff) {
152 if ((check_sync) &&
153 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
154 (loop->flags & PVSync)) ||
155 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
156 (loop->flags & NVSync)) ||
157 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
158 (loop->flags & PHSync)) ||
159 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
160 (loop->flags & NHSync)))) {
161 loop++;
162 continue;
163 }
164 if (loop->refresh_rate <= refresh_rate
165 && (!best || loop->refresh_rate > best->refresh_rate))
166 best = loop;
167 loop++;
168 }
169 if (best || !check_sync)
170 break;
171 check_sync = 0;
172 } while (1);
173 if (best)
174 vbios_mode->enh_table = best;
175
176 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
177 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
178
179 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
180 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
181 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
182 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
183 vbios_mode->enh_table->hfp;
184 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
185 vbios_mode->enh_table->hfp +
186 vbios_mode->enh_table->hsync);
187
188 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
189 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
190 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
191 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
192 vbios_mode->enh_table->vfp;
193 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
194 vbios_mode->enh_table->vfp +
195 vbios_mode->enh_table->vsync);
196
197 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
198 mode_id = vbios_mode->enh_table->mode_id;
199
200 if (ast->chip == AST1180) {
201 /* TODO 1180 */
202 } else {
203 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4));
204 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
205 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
206
207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
208 if (vbios_mode->enh_table->flags & NewModeInfo) {
209 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
210 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, crtc->primary->fb->bits_per_pixel);
211 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
212 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
213 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
214
215 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
216 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
217 }
218 }
219
220 return true;
221
222
223 }
224 static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
225 struct ast_vbios_mode_info *vbios_mode)
226 {
227 struct ast_private *ast = crtc->dev->dev_private;
228 struct ast_vbios_stdtable *stdtable;
229 u32 i;
230 u8 jreg;
231
232 stdtable = vbios_mode->std_table;
233
234 jreg = stdtable->misc;
235 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
236
237 /* Set SEQ */
238 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
239 for (i = 0; i < 4; i++) {
240 jreg = stdtable->seq[i];
241 if (!i)
242 jreg |= 0x20;
243 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
244 }
245
246 /* Set CRTC */
247 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
248 for (i = 0; i < 25; i++)
249 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
250
251 /* set AR */
252 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
253 for (i = 0; i < 20; i++) {
254 jreg = stdtable->ar[i];
255 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
256 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
257 }
258 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
259 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
260
261 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
262 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
263
264 /* Set GR */
265 for (i = 0; i < 9; i++)
266 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
267 }
268
269 static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
270 struct ast_vbios_mode_info *vbios_mode)
271 {
272 struct ast_private *ast = crtc->dev->dev_private;
273 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
274 u16 temp;
275
276 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
277
278 temp = (mode->crtc_htotal >> 3) - 5;
279 if (temp & 0x100)
280 jregAC |= 0x01; /* HT D[8] */
281 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
282
283 temp = (mode->crtc_hdisplay >> 3) - 1;
284 if (temp & 0x100)
285 jregAC |= 0x04; /* HDE D[8] */
286 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
287
288 temp = (mode->crtc_hblank_start >> 3) - 1;
289 if (temp & 0x100)
290 jregAC |= 0x10; /* HBS D[8] */
291 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
292
293 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
294 if (temp & 0x20)
295 jreg05 |= 0x80; /* HBE D[5] */
296 if (temp & 0x40)
297 jregAD |= 0x01; /* HBE D[5] */
298 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
299
300 temp = (mode->crtc_hsync_start >> 3) - 1;
301 if (temp & 0x100)
302 jregAC |= 0x40; /* HRS D[5] */
303 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
304
305 temp = ((mode->crtc_hsync_end >> 3) - 1) & 0x3f;
306 if (temp & 0x20)
307 jregAD |= 0x04; /* HRE D[5] */
308 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
309
310 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
311 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
312
313 /* vert timings */
314 temp = (mode->crtc_vtotal) - 2;
315 if (temp & 0x100)
316 jreg07 |= 0x01;
317 if (temp & 0x200)
318 jreg07 |= 0x20;
319 if (temp & 0x400)
320 jregAE |= 0x01;
321 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
322
323 temp = (mode->crtc_vsync_start) - 1;
324 if (temp & 0x100)
325 jreg07 |= 0x04;
326 if (temp & 0x200)
327 jreg07 |= 0x80;
328 if (temp & 0x400)
329 jregAE |= 0x08;
330 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
331
332 temp = (mode->crtc_vsync_end - 1) & 0x3f;
333 if (temp & 0x10)
334 jregAE |= 0x20;
335 if (temp & 0x20)
336 jregAE |= 0x40;
337 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
338
339 temp = mode->crtc_vdisplay - 1;
340 if (temp & 0x100)
341 jreg07 |= 0x02;
342 if (temp & 0x200)
343 jreg07 |= 0x40;
344 if (temp & 0x400)
345 jregAE |= 0x02;
346 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
347
348 temp = mode->crtc_vblank_start - 1;
349 if (temp & 0x100)
350 jreg07 |= 0x08;
351 if (temp & 0x200)
352 jreg09 |= 0x20;
353 if (temp & 0x400)
354 jregAE |= 0x04;
355 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
356
357 temp = mode->crtc_vblank_end - 1;
358 if (temp & 0x100)
359 jregAE |= 0x10;
360 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
361
362 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
363 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
365
366 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
367 }
368
369 static void ast_set_offset_reg(struct drm_crtc *crtc)
370 {
371 struct ast_private *ast = crtc->dev->dev_private;
372
373 u16 offset;
374
375 offset = crtc->primary->fb->pitches[0] >> 3;
376 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
377 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
378 }
379
380 static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode,
381 struct ast_vbios_mode_info *vbios_mode)
382 {
383 struct ast_private *ast = dev->dev_private;
384 struct ast_vbios_dclk_info *clk_info;
385
386 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
387
388 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
389 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
390 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
391 (clk_info->param3 & 0x80) | ((clk_info->param3 & 0x3) << 4));
392 }
393
394 static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
395 struct ast_vbios_mode_info *vbios_mode)
396 {
397 struct ast_private *ast = crtc->dev->dev_private;
398 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
399
400 switch (crtc->primary->fb->bits_per_pixel) {
401 case 8:
402 jregA0 = 0x70;
403 jregA3 = 0x01;
404 jregA8 = 0x00;
405 break;
406 case 15:
407 case 16:
408 jregA0 = 0x70;
409 jregA3 = 0x04;
410 jregA8 = 0x02;
411 break;
412 case 32:
413 jregA0 = 0x70;
414 jregA3 = 0x08;
415 jregA8 = 0x02;
416 break;
417 }
418
419 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
420 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
421 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
422
423 /* Set Threshold */
424 if (ast->chip == AST2300 || ast->chip == AST2400) {
425 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
426 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
427 } else if (ast->chip == AST2100 ||
428 ast->chip == AST1100 ||
429 ast->chip == AST2200 ||
430 ast->chip == AST2150) {
431 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
432 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
433 } else {
434 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
435 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
436 }
437 }
438
439 static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode,
440 struct ast_vbios_mode_info *vbios_mode)
441 {
442 struct ast_private *ast = dev->dev_private;
443 u8 jreg;
444
445 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
446 jreg &= ~0xC0;
447 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80;
448 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40;
449 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
450 }
451
452 static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
453 struct ast_vbios_mode_info *vbios_mode)
454 {
455 switch (crtc->primary->fb->bits_per_pixel) {
456 case 8:
457 break;
458 default:
459 return false;
460 }
461 return true;
462 }
463
464 static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset)
465 {
466 struct ast_private *ast = crtc->dev->dev_private;
467 u32 addr;
468
469 addr = offset >> 2;
470 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
471 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
472 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
473
474 }
475
476 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
477 {
478 struct ast_private *ast = crtc->dev->dev_private;
479
480 if (ast->chip == AST1180)
481 return;
482
483 switch (mode) {
484 case DRM_MODE_DPMS_ON:
485 case DRM_MODE_DPMS_STANDBY:
486 case DRM_MODE_DPMS_SUSPEND:
487 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
488 if (ast->tx_chip_type == AST_TX_DP501)
489 ast_set_dp501_video_output(crtc->dev, 1);
490 ast_crtc_load_lut(crtc);
491 break;
492 case DRM_MODE_DPMS_OFF:
493 if (ast->tx_chip_type == AST_TX_DP501)
494 ast_set_dp501_video_output(crtc->dev, 0);
495 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
496 break;
497 }
498 }
499
500 static bool ast_crtc_mode_fixup(struct drm_crtc *crtc,
501 const struct drm_display_mode *mode,
502 struct drm_display_mode *adjusted_mode)
503 {
504 return true;
505 }
506
507 /* ast is different - we will force move buffers out of VRAM */
508 static int ast_crtc_do_set_base(struct drm_crtc *crtc,
509 struct drm_framebuffer *fb,
510 int x, int y, int atomic)
511 {
512 struct ast_private *ast = crtc->dev->dev_private;
513 struct drm_gem_object *obj;
514 struct ast_framebuffer *ast_fb;
515 struct ast_bo *bo;
516 int ret;
517 u64 gpu_addr;
518
519 /* push the previous fb to system ram */
520 if (!atomic && fb) {
521 ast_fb = to_ast_framebuffer(fb);
522 obj = ast_fb->obj;
523 bo = gem_to_ast_bo(obj);
524 ret = ast_bo_reserve(bo, false);
525 if (ret)
526 return ret;
527 ast_bo_push_sysram(bo);
528 ast_bo_unreserve(bo);
529 }
530
531 ast_fb = to_ast_framebuffer(crtc->primary->fb);
532 obj = ast_fb->obj;
533 bo = gem_to_ast_bo(obj);
534
535 ret = ast_bo_reserve(bo, false);
536 if (ret)
537 return ret;
538
539 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
540 if (ret) {
541 ast_bo_unreserve(bo);
542 return ret;
543 }
544
545 if (&ast->fbdev->afb == ast_fb) {
546 /* if pushing console in kmap it */
547 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
548 if (ret)
549 DRM_ERROR("failed to kmap fbcon\n");
550 else
551 ast_fbdev_set_base(ast, gpu_addr);
552 }
553 ast_bo_unreserve(bo);
554
555 ast_set_start_address_crt1(crtc, (u32)gpu_addr);
556
557 return 0;
558 }
559
560 static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
561 struct drm_framebuffer *old_fb)
562 {
563 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0);
564 }
565
566 static int ast_crtc_mode_set(struct drm_crtc *crtc,
567 struct drm_display_mode *mode,
568 struct drm_display_mode *adjusted_mode,
569 int x, int y,
570 struct drm_framebuffer *old_fb)
571 {
572 struct drm_device *dev = crtc->dev;
573 struct ast_private *ast = crtc->dev->dev_private;
574 struct ast_vbios_mode_info vbios_mode;
575 bool ret;
576 if (ast->chip == AST1180) {
577 DRM_ERROR("AST 1180 modesetting not supported\n");
578 return -EINVAL;
579 }
580
581 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode);
582 if (ret == false)
583 return -EINVAL;
584 ast_open_key(ast);
585
586 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
587
588 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode);
589 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode);
590 ast_set_offset_reg(crtc);
591 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode);
592 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode);
593 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode);
594 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode);
595
596 ast_crtc_mode_set_base(crtc, x, y, old_fb);
597
598 return 0;
599 }
600
601 static void ast_crtc_disable(struct drm_crtc *crtc)
602 {
603
604 }
605
606 static void ast_crtc_prepare(struct drm_crtc *crtc)
607 {
608
609 }
610
611 static void ast_crtc_commit(struct drm_crtc *crtc)
612 {
613 struct ast_private *ast = crtc->dev->dev_private;
614 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
615 }
616
617
618 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
619 .dpms = ast_crtc_dpms,
620 .mode_fixup = ast_crtc_mode_fixup,
621 .mode_set = ast_crtc_mode_set,
622 .mode_set_base = ast_crtc_mode_set_base,
623 .disable = ast_crtc_disable,
624 .load_lut = ast_crtc_load_lut,
625 .prepare = ast_crtc_prepare,
626 .commit = ast_crtc_commit,
627
628 };
629
630 static void ast_crtc_reset(struct drm_crtc *crtc)
631 {
632
633 }
634
635 static void ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
636 u16 *blue, uint32_t start, uint32_t size)
637 {
638 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
639 int end = (start + size > 256) ? 256 : start + size, i;
640
641 /* userspace palettes are always correct as is */
642 for (i = start; i < end; i++) {
643 ast_crtc->lut_r[i] = red[i] >> 8;
644 ast_crtc->lut_g[i] = green[i] >> 8;
645 ast_crtc->lut_b[i] = blue[i] >> 8;
646 }
647 ast_crtc_load_lut(crtc);
648 }
649
650
651 static void ast_crtc_destroy(struct drm_crtc *crtc)
652 {
653 drm_crtc_cleanup(crtc);
654 kfree(crtc);
655 }
656
657 static const struct drm_crtc_funcs ast_crtc_funcs = {
658 .cursor_set = ast_cursor_set,
659 .cursor_move = ast_cursor_move,
660 .reset = ast_crtc_reset,
661 .set_config = drm_crtc_helper_set_config,
662 .gamma_set = ast_crtc_gamma_set,
663 .destroy = ast_crtc_destroy,
664 };
665
666 static int ast_crtc_init(struct drm_device *dev)
667 {
668 struct ast_crtc *crtc;
669 int i;
670
671 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL);
672 if (!crtc)
673 return -ENOMEM;
674
675 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs);
676 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
677 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs);
678
679 for (i = 0; i < 256; i++) {
680 crtc->lut_r[i] = i;
681 crtc->lut_g[i] = i;
682 crtc->lut_b[i] = i;
683 }
684 return 0;
685 }
686
687 static void ast_encoder_destroy(struct drm_encoder *encoder)
688 {
689 drm_encoder_cleanup(encoder);
690 kfree(encoder);
691 }
692
693
694 static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector)
695 {
696 int enc_id = connector->encoder_ids[0];
697 /* pick the encoder ids */
698 if (enc_id)
699 return drm_encoder_find(connector->dev, enc_id);
700 return NULL;
701 }
702
703
704 static const struct drm_encoder_funcs ast_enc_funcs = {
705 .destroy = ast_encoder_destroy,
706 };
707
708 static void ast_encoder_dpms(struct drm_encoder *encoder, int mode)
709 {
710
711 }
712
713 static bool ast_mode_fixup(struct drm_encoder *encoder,
714 const struct drm_display_mode *mode,
715 struct drm_display_mode *adjusted_mode)
716 {
717 return true;
718 }
719
720 static void ast_encoder_mode_set(struct drm_encoder *encoder,
721 struct drm_display_mode *mode,
722 struct drm_display_mode *adjusted_mode)
723 {
724 }
725
726 static void ast_encoder_prepare(struct drm_encoder *encoder)
727 {
728
729 }
730
731 static void ast_encoder_commit(struct drm_encoder *encoder)
732 {
733
734 }
735
736
737 static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = {
738 .dpms = ast_encoder_dpms,
739 .mode_fixup = ast_mode_fixup,
740 .prepare = ast_encoder_prepare,
741 .commit = ast_encoder_commit,
742 .mode_set = ast_encoder_mode_set,
743 };
744
745 static int ast_encoder_init(struct drm_device *dev)
746 {
747 struct ast_encoder *ast_encoder;
748
749 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL);
750 if (!ast_encoder)
751 return -ENOMEM;
752
753 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs,
754 DRM_MODE_ENCODER_DAC);
755 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs);
756
757 ast_encoder->base.possible_crtcs = 1;
758 return 0;
759 }
760
761 static int ast_get_modes(struct drm_connector *connector)
762 {
763 struct ast_connector *ast_connector = to_ast_connector(connector);
764 struct ast_private *ast = connector->dev->dev_private;
765 struct edid *edid;
766 int ret;
767 bool flags = false;
768 if (ast->tx_chip_type == AST_TX_DP501) {
769 ast->dp501_maxclk = 0xff;
770 edid = kmalloc(128, GFP_KERNEL);
771 if (!edid)
772 return -ENOMEM;
773
774 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
775 if (flags)
776 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
777 else
778 kfree(edid);
779 }
780 if (!flags)
781 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
782 if (edid) {
783 drm_mode_connector_update_edid_property(&ast_connector->base, edid);
784 ret = drm_add_edid_modes(connector, edid);
785 kfree(edid);
786 return ret;
787 } else
788 drm_mode_connector_update_edid_property(&ast_connector->base, NULL);
789 return 0;
790 }
791
792 static int ast_mode_valid(struct drm_connector *connector,
793 struct drm_display_mode *mode)
794 {
795 struct ast_private *ast = connector->dev->dev_private;
796 int flags = MODE_NOMODE;
797 uint32_t jtemp;
798
799 if (ast->support_wide_screen) {
800 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
801 return MODE_OK;
802 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
803 return MODE_OK;
804 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
805 return MODE_OK;
806 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
807 return MODE_OK;
808 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
809 return MODE_OK;
810
811 if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) {
812 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
813 return MODE_OK;
814
815 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
816 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
817 if (jtemp & 0x01)
818 return MODE_NOMODE;
819 else
820 return MODE_OK;
821 }
822 }
823 }
824 switch (mode->hdisplay) {
825 case 640:
826 if (mode->vdisplay == 480) flags = MODE_OK;
827 break;
828 case 800:
829 if (mode->vdisplay == 600) flags = MODE_OK;
830 break;
831 case 1024:
832 if (mode->vdisplay == 768) flags = MODE_OK;
833 break;
834 case 1280:
835 if (mode->vdisplay == 1024) flags = MODE_OK;
836 break;
837 case 1600:
838 if (mode->vdisplay == 1200) flags = MODE_OK;
839 break;
840 default:
841 return flags;
842 }
843
844 return flags;
845 }
846
847 static void ast_connector_destroy(struct drm_connector *connector)
848 {
849 struct ast_connector *ast_connector = to_ast_connector(connector);
850 ast_i2c_destroy(ast_connector->i2c);
851 drm_connector_unregister(connector);
852 drm_connector_cleanup(connector);
853 kfree(connector);
854 }
855
856 static enum drm_connector_status
857 ast_connector_detect(struct drm_connector *connector, bool force)
858 {
859 return connector_status_connected;
860 }
861
862 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
863 .mode_valid = ast_mode_valid,
864 .get_modes = ast_get_modes,
865 .best_encoder = ast_best_single_encoder,
866 };
867
868 static const struct drm_connector_funcs ast_connector_funcs = {
869 .dpms = drm_helper_connector_dpms,
870 .detect = ast_connector_detect,
871 .fill_modes = drm_helper_probe_single_connector_modes,
872 .destroy = ast_connector_destroy,
873 };
874
875 static int ast_connector_init(struct drm_device *dev)
876 {
877 struct ast_connector *ast_connector;
878 struct drm_connector *connector;
879 struct drm_encoder *encoder;
880
881 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL);
882 if (!ast_connector)
883 return -ENOMEM;
884
885 connector = &ast_connector->base;
886 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA);
887
888 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
889
890 connector->interlace_allowed = 0;
891 connector->doublescan_allowed = 0;
892
893 drm_connector_register(connector);
894
895 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
896
897 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head);
898 drm_mode_connector_attach_encoder(connector, encoder);
899
900 ast_connector->i2c = ast_i2c_create(dev);
901 if (!ast_connector->i2c)
902 DRM_ERROR("failed to add ddc bus for connector\n");
903
904 return 0;
905 }
906
907 /* allocate cursor cache and pin at start of VRAM */
908 static int ast_cursor_init(struct drm_device *dev)
909 {
910 struct ast_private *ast = dev->dev_private;
911 int size;
912 int ret;
913 struct drm_gem_object *obj;
914 struct ast_bo *bo;
915 uint64_t gpu_addr;
916
917 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM;
918
919 ret = ast_gem_create(dev, size, true, &obj);
920 if (ret)
921 return ret;
922 bo = gem_to_ast_bo(obj);
923 ret = ast_bo_reserve(bo, false);
924 if (unlikely(ret != 0))
925 goto fail;
926
927 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
928 ast_bo_unreserve(bo);
929 if (ret)
930 goto fail;
931
932 /* kmap the object */
933 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap);
934 if (ret)
935 goto fail;
936
937 ast->cursor_cache = obj;
938 ast->cursor_cache_gpu_addr = gpu_addr;
939 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr);
940 return 0;
941 fail:
942 return ret;
943 }
944
945 static void ast_cursor_fini(struct drm_device *dev)
946 {
947 struct ast_private *ast = dev->dev_private;
948 ttm_bo_kunmap(&ast->cache_kmap);
949 drm_gem_object_unreference_unlocked(ast->cursor_cache);
950 }
951
952 int ast_mode_init(struct drm_device *dev)
953 {
954 ast_cursor_init(dev);
955 ast_crtc_init(dev);
956 ast_encoder_init(dev);
957 ast_connector_init(dev);
958 return 0;
959 }
960
961 void ast_mode_fini(struct drm_device *dev)
962 {
963 ast_cursor_fini(dev);
964 }
965
966 static int get_clock(void *i2c_priv)
967 {
968 struct ast_i2c_chan *i2c = i2c_priv;
969 struct ast_private *ast = i2c->dev->dev_private;
970 uint32_t val;
971
972 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4;
973 return val & 1 ? 1 : 0;
974 }
975
976 static int get_data(void *i2c_priv)
977 {
978 struct ast_i2c_chan *i2c = i2c_priv;
979 struct ast_private *ast = i2c->dev->dev_private;
980 uint32_t val;
981
982 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5;
983 return val & 1 ? 1 : 0;
984 }
985
986 static void set_clock(void *i2c_priv, int clock)
987 {
988 struct ast_i2c_chan *i2c = i2c_priv;
989 struct ast_private *ast = i2c->dev->dev_private;
990 int i;
991 u8 ujcrb7, jtemp;
992
993 for (i = 0; i < 0x10000; i++) {
994 ujcrb7 = ((clock & 0x01) ? 0 : 1);
995 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7);
996 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
997 if (ujcrb7 == jtemp)
998 break;
999 }
1000 }
1001
1002 static void set_data(void *i2c_priv, int data)
1003 {
1004 struct ast_i2c_chan *i2c = i2c_priv;
1005 struct ast_private *ast = i2c->dev->dev_private;
1006 int i;
1007 u8 ujcrb7, jtemp;
1008
1009 for (i = 0; i < 0x10000; i++) {
1010 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1011 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7);
1012 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1013 if (ujcrb7 == jtemp)
1014 break;
1015 }
1016 }
1017
1018 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1019 {
1020 struct ast_i2c_chan *i2c;
1021 int ret;
1022
1023 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1024 if (!i2c)
1025 return NULL;
1026
1027 i2c->adapter.owner = THIS_MODULE;
1028 i2c->adapter.class = I2C_CLASS_DDC;
1029 i2c->adapter.dev.parent = &dev->pdev->dev;
1030 i2c->dev = dev;
1031 i2c_set_adapdata(&i2c->adapter, i2c);
1032 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1033 "AST i2c bit bus");
1034 i2c->adapter.algo_data = &i2c->bit;
1035
1036 i2c->bit.udelay = 20;
1037 i2c->bit.timeout = 2;
1038 i2c->bit.data = i2c;
1039 i2c->bit.setsda = set_data;
1040 i2c->bit.setscl = set_clock;
1041 i2c->bit.getsda = get_data;
1042 i2c->bit.getscl = get_clock;
1043 ret = i2c_bit_add_bus(&i2c->adapter);
1044 if (ret) {
1045 DRM_ERROR("Failed to register bit i2c\n");
1046 goto out_free;
1047 }
1048
1049 return i2c;
1050 out_free:
1051 kfree(i2c);
1052 return NULL;
1053 }
1054
1055 static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1056 {
1057 if (!i2c)
1058 return;
1059 i2c_del_adapter(&i2c->adapter);
1060 kfree(i2c);
1061 }
1062
1063 static void ast_show_cursor(struct drm_crtc *crtc)
1064 {
1065 struct ast_private *ast = crtc->dev->dev_private;
1066 u8 jreg;
1067
1068 jreg = 0x2;
1069 /* enable ARGB cursor */
1070 jreg |= 1;
1071 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
1072 }
1073
1074 static void ast_hide_cursor(struct drm_crtc *crtc)
1075 {
1076 struct ast_private *ast = crtc->dev->dev_private;
1077 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
1078 }
1079
1080 static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height)
1081 {
1082 union {
1083 u32 ul;
1084 u8 b[4];
1085 } srcdata32[2], data32;
1086 union {
1087 u16 us;
1088 u8 b[2];
1089 } data16;
1090 u32 csum = 0;
1091 s32 alpha_dst_delta, last_alpha_dst_delta;
1092 u8 *srcxor, *dstxor;
1093 int i, j;
1094 u32 per_pixel_copy, two_pixel_copy;
1095
1096 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
1097 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
1098
1099 srcxor = src;
1100 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
1101 per_pixel_copy = width & 1;
1102 two_pixel_copy = width >> 1;
1103
1104 for (j = 0; j < height; j++) {
1105 for (i = 0; i < two_pixel_copy; i++) {
1106 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1107 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
1108 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1109 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1110 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
1111 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
1112
1113 writel(data32.ul, dstxor);
1114 csum += data32.ul;
1115
1116 dstxor += 4;
1117 srcxor += 8;
1118
1119 }
1120
1121 for (i = 0; i < per_pixel_copy; i++) {
1122 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1123 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1124 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1125 writew(data16.us, dstxor);
1126 csum += (u32)data16.us;
1127
1128 dstxor += 2;
1129 srcxor += 4;
1130 }
1131 dstxor += last_alpha_dst_delta;
1132 }
1133 return csum;
1134 }
1135
1136 static int ast_cursor_set(struct drm_crtc *crtc,
1137 struct drm_file *file_priv,
1138 uint32_t handle,
1139 uint32_t width,
1140 uint32_t height)
1141 {
1142 struct ast_private *ast = crtc->dev->dev_private;
1143 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1144 struct drm_gem_object *obj;
1145 struct ast_bo *bo;
1146 uint64_t gpu_addr;
1147 u32 csum;
1148 int ret;
1149 struct ttm_bo_kmap_obj uobj_map;
1150 u8 *src, *dst;
1151 bool src_isiomem, dst_isiomem;
1152 if (!handle) {
1153 ast_hide_cursor(crtc);
1154 return 0;
1155 }
1156
1157 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT)
1158 return -EINVAL;
1159
1160 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
1161 if (!obj) {
1162 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle);
1163 return -ENOENT;
1164 }
1165 bo = gem_to_ast_bo(obj);
1166
1167 ret = ast_bo_reserve(bo, false);
1168 if (ret)
1169 goto fail;
1170
1171 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map);
1172
1173 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem);
1174 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem);
1175
1176 if (src_isiomem == true)
1177 DRM_ERROR("src cursor bo should be in main memory\n");
1178 if (dst_isiomem == false)
1179 DRM_ERROR("dst bo should be in VRAM\n");
1180
1181 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1182
1183 /* do data transfer to cursor cache */
1184 csum = copy_cursor_image(src, dst, width, height);
1185
1186 /* write checksum + signature */
1187 ttm_bo_kunmap(&uobj_map);
1188 ast_bo_unreserve(bo);
1189 {
1190 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1191 writel(csum, dst);
1192 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
1193 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
1194 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
1195 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
1196
1197 /* set pattern offset */
1198 gpu_addr = ast->cursor_cache_gpu_addr;
1199 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1200 gpu_addr >>= 3;
1201 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff);
1202 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff);
1203 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff);
1204 }
1205 ast_crtc->cursor_width = width;
1206 ast_crtc->cursor_height = height;
1207 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width;
1208 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height;
1209
1210 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM;
1211
1212 ast_show_cursor(crtc);
1213
1214 drm_gem_object_unreference_unlocked(obj);
1215 return 0;
1216 fail:
1217 drm_gem_object_unreference_unlocked(obj);
1218 return ret;
1219 }
1220
1221 static int ast_cursor_move(struct drm_crtc *crtc,
1222 int x, int y)
1223 {
1224 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1225 struct ast_private *ast = crtc->dev->dev_private;
1226 int x_offset, y_offset;
1227 u8 *sig;
1228
1229 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1230 writel(x, sig + AST_HWC_SIGNATURE_X);
1231 writel(y, sig + AST_HWC_SIGNATURE_Y);
1232
1233 x_offset = ast_crtc->offset_x;
1234 y_offset = ast_crtc->offset_y;
1235 if (x < 0) {
1236 x_offset = (-x) + ast_crtc->offset_x;
1237 x = 0;
1238 }
1239
1240 if (y < 0) {
1241 y_offset = (-y) + ast_crtc->offset_y;
1242 y = 0;
1243 }
1244 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
1245 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
1246 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
1247 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
1248 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
1249 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
1250
1251 /* dummy write to fire HWC */
1252 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00);
1253
1254 return 0;
1255 }
Linux with added FPC-III support