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drm/omap: Fix error handling path in 'omap_dmm_probe()'
[linux/fpc-iii.git] / drivers / gpu / drm / exynos / exynos7_drm_decon.c
blobead2b16e237d5558a47ac820fbb4d5dd66f2f86c
1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c
2 *
3 * Copyright (C) 2014 Samsung Electronics Co.Ltd
4 * Authors:
5 * Akshu Agarwal <akshua@gmail.com>
6 * Ajay Kumar <ajaykumar.rs@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15 #include <drm/exynos_drm.h>
16
17 #include <linux/clk.h>
18 #include <linux/component.h>
19 #include <linux/kernel.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/exynos7_decon.h>
29
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_plane.h"
32 #include "exynos_drm_drv.h"
33 #include "exynos_drm_fbdev.h"
34 #include "exynos_drm_iommu.h"
35
36 /*
37 * DECON stands for Display and Enhancement controller.
38 */
39
40 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
41
42 #define WINDOWS_NR 2
43 #define CURSOR_WIN 1
44
45 struct decon_context {
46 struct device *dev;
47 struct drm_device *drm_dev;
48 struct exynos_drm_crtc *crtc;
49 struct exynos_drm_plane planes[WINDOWS_NR];
50 struct clk *pclk;
51 struct clk *aclk;
52 struct clk *eclk;
53 struct clk *vclk;
54 void __iomem *regs;
55 unsigned long irq_flags;
56 bool i80_if;
57 bool suspended;
58 int pipe;
59 wait_queue_head_t wait_vsync_queue;
60 atomic_t wait_vsync_event;
61
62 struct exynos_drm_panel_info panel;
63 struct drm_encoder *encoder;
64 };
65
66 static const struct of_device_id decon_driver_dt_match[] = {
67 {.compatible = "samsung,exynos7-decon"},
68 {},
69 };
70 MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
71
72 static const uint32_t decon_formats[] = {
73 DRM_FORMAT_RGB565,
74 DRM_FORMAT_XRGB8888,
75 DRM_FORMAT_XBGR8888,
76 DRM_FORMAT_RGBX8888,
77 DRM_FORMAT_BGRX8888,
78 DRM_FORMAT_ARGB8888,
79 DRM_FORMAT_ABGR8888,
80 DRM_FORMAT_RGBA8888,
81 DRM_FORMAT_BGRA8888,
82 };
83
84 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
85 {
86 struct decon_context *ctx = crtc->ctx;
87
88 if (ctx->suspended)
89 return;
90
91 atomic_set(&ctx->wait_vsync_event, 1);
92
93 /*
94 * wait for DECON to signal VSYNC interrupt or return after
95 * timeout which is set to 50ms (refresh rate of 20).
96 */
97 if (!wait_event_timeout(ctx->wait_vsync_queue,
98 !atomic_read(&ctx->wait_vsync_event),
99 HZ/20))
100 DRM_DEBUG_KMS("vblank wait timed out.\n");
101 }
102
103 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
104 {
105 struct decon_context *ctx = crtc->ctx;
106 unsigned int win, ch_enabled = 0;
107
108 DRM_DEBUG_KMS("%s\n", __FILE__);
109
110 /* Check if any channel is enabled. */
111 for (win = 0; win < WINDOWS_NR; win++) {
112 u32 val = readl(ctx->regs + WINCON(win));
113
114 if (val & WINCONx_ENWIN) {
115 val &= ~WINCONx_ENWIN;
116 writel(val, ctx->regs + WINCON(win));
117 ch_enabled = 1;
118 }
119 }
120
121 /* Wait for vsync, as disable channel takes effect at next vsync */
122 if (ch_enabled) {
123 unsigned int state = ctx->suspended;
124
125 ctx->suspended = 0;
126 decon_wait_for_vblank(ctx->crtc);
127 ctx->suspended = state;
128 }
129 }
130
131 static int decon_ctx_initialize(struct decon_context *ctx,
132 struct drm_device *drm_dev)
133 {
134 struct exynos_drm_private *priv = drm_dev->dev_private;
135 int ret;
136
137 ctx->drm_dev = drm_dev;
138 ctx->pipe = priv->pipe++;
139
140 decon_clear_channels(ctx->crtc);
141
142 ret = drm_iommu_attach_device(drm_dev, ctx->dev);
143 if (ret)
144 priv->pipe--;
145
146 return ret;
147 }
148
149 static void decon_ctx_remove(struct decon_context *ctx)
150 {
151 /* detach this sub driver from iommu mapping if supported. */
152 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
153 }
154
155 static u32 decon_calc_clkdiv(struct decon_context *ctx,
156 const struct drm_display_mode *mode)
157 {
158 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
159 u32 clkdiv;
160
161 /* Find the clock divider value that gets us closest to ideal_clk */
162 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
163
164 return (clkdiv < 0x100) ? clkdiv : 0xff;
165 }
166
167 static void decon_commit(struct exynos_drm_crtc *crtc)
168 {
169 struct decon_context *ctx = crtc->ctx;
170 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
171 u32 val, clkdiv;
172
173 if (ctx->suspended)
174 return;
175
176 /* nothing to do if we haven't set the mode yet */
177 if (mode->htotal == 0 || mode->vtotal == 0)
178 return;
179
180 if (!ctx->i80_if) {
181 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
182 /* setup vertical timing values. */
183 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
184 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
185 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
186
187 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
188 writel(val, ctx->regs + VIDTCON0);
189
190 val = VIDTCON1_VSPW(vsync_len - 1);
191 writel(val, ctx->regs + VIDTCON1);
192
193 /* setup horizontal timing values. */
194 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
195 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
196 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
197
198 /* setup horizontal timing values. */
199 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
200 writel(val, ctx->regs + VIDTCON2);
201
202 val = VIDTCON3_HSPW(hsync_len - 1);
203 writel(val, ctx->regs + VIDTCON3);
204 }
205
206 /* setup horizontal and vertical display size. */
207 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
208 VIDTCON4_HOZVAL(mode->hdisplay - 1);
209 writel(val, ctx->regs + VIDTCON4);
210
211 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
212
213 /*
214 * fields of register with prefix '_F' would be updated
215 * at vsync(same as dma start)
216 */
217 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
218 writel(val, ctx->regs + VIDCON0);
219
220 clkdiv = decon_calc_clkdiv(ctx, mode);
221 if (clkdiv > 1) {
222 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
223 writel(val, ctx->regs + VCLKCON1);
224 writel(val, ctx->regs + VCLKCON2);
225 }
226
227 val = readl(ctx->regs + DECON_UPDATE);
228 val |= DECON_UPDATE_STANDALONE_F;
229 writel(val, ctx->regs + DECON_UPDATE);
230 }
231
232 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
233 {
234 struct decon_context *ctx = crtc->ctx;
235 u32 val;
236
237 if (ctx->suspended)
238 return -EPERM;
239
240 if (!test_and_set_bit(0, &ctx->irq_flags)) {
241 val = readl(ctx->regs + VIDINTCON0);
242
243 val |= VIDINTCON0_INT_ENABLE;
244
245 if (!ctx->i80_if) {
246 val |= VIDINTCON0_INT_FRAME;
247 val &= ~VIDINTCON0_FRAMESEL0_MASK;
248 val |= VIDINTCON0_FRAMESEL0_VSYNC;
249 }
250
251 writel(val, ctx->regs + VIDINTCON0);
252 }
253
254 return 0;
255 }
256
257 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
258 {
259 struct decon_context *ctx = crtc->ctx;
260 u32 val;
261
262 if (ctx->suspended)
263 return;
264
265 if (test_and_clear_bit(0, &ctx->irq_flags)) {
266 val = readl(ctx->regs + VIDINTCON0);
267
268 val &= ~VIDINTCON0_INT_ENABLE;
269 if (!ctx->i80_if)
270 val &= ~VIDINTCON0_INT_FRAME;
271
272 writel(val, ctx->regs + VIDINTCON0);
273 }
274 }
275
276 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
277 struct drm_framebuffer *fb)
278 {
279 unsigned long val;
280 int padding;
281
282 val = readl(ctx->regs + WINCON(win));
283 val &= ~WINCONx_BPPMODE_MASK;
284
285 switch (fb->pixel_format) {
286 case DRM_FORMAT_RGB565:
287 val |= WINCONx_BPPMODE_16BPP_565;
288 val |= WINCONx_BURSTLEN_16WORD;
289 break;
290 case DRM_FORMAT_XRGB8888:
291 val |= WINCONx_BPPMODE_24BPP_xRGB;
292 val |= WINCONx_BURSTLEN_16WORD;
293 break;
294 case DRM_FORMAT_XBGR8888:
295 val |= WINCONx_BPPMODE_24BPP_xBGR;
296 val |= WINCONx_BURSTLEN_16WORD;
297 break;
298 case DRM_FORMAT_RGBX8888:
299 val |= WINCONx_BPPMODE_24BPP_RGBx;
300 val |= WINCONx_BURSTLEN_16WORD;
301 break;
302 case DRM_FORMAT_BGRX8888:
303 val |= WINCONx_BPPMODE_24BPP_BGRx;
304 val |= WINCONx_BURSTLEN_16WORD;
305 break;
306 case DRM_FORMAT_ARGB8888:
307 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
308 WINCONx_ALPHA_SEL;
309 val |= WINCONx_BURSTLEN_16WORD;
310 break;
311 case DRM_FORMAT_ABGR8888:
312 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
313 WINCONx_ALPHA_SEL;
314 val |= WINCONx_BURSTLEN_16WORD;
315 break;
316 case DRM_FORMAT_RGBA8888:
317 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
318 WINCONx_ALPHA_SEL;
319 val |= WINCONx_BURSTLEN_16WORD;
320 break;
321 case DRM_FORMAT_BGRA8888:
322 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
323 WINCONx_ALPHA_SEL;
324 val |= WINCONx_BURSTLEN_16WORD;
325 break;
326 default:
327 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
328
329 val |= WINCONx_BPPMODE_24BPP_xRGB;
330 val |= WINCONx_BURSTLEN_16WORD;
331 break;
332 }
333
334 DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel);
335
336 /*
337 * In case of exynos, setting dma-burst to 16Word causes permanent
338 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
339 * switching which is based on plane size is not recommended as
340 * plane size varies a lot towards the end of the screen and rapid
341 * movement causes unstable DMA which results into iommu crash/tear.
342 */
343
344 padding = (fb->pitches[0] / (fb->bits_per_pixel >> 3)) - fb->width;
345 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
346 val &= ~WINCONx_BURSTLEN_MASK;
347 val |= WINCONx_BURSTLEN_8WORD;
348 }
349
350 writel(val, ctx->regs + WINCON(win));
351 }
352
353 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
354 {
355 unsigned int keycon0 = 0, keycon1 = 0;
356
357 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
358 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
359
360 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
361
362 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
363 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
364 }
365
366 /**
367 * shadow_protect_win() - disable updating values from shadow registers at vsync
368 *
369 * @win: window to protect registers for
370 * @protect: 1 to protect (disable updates)
371 */
372 static void decon_shadow_protect_win(struct decon_context *ctx,
373 unsigned int win, bool protect)
374 {
375 u32 bits, val;
376
377 bits = SHADOWCON_WINx_PROTECT(win);
378
379 val = readl(ctx->regs + SHADOWCON);
380 if (protect)
381 val |= bits;
382 else
383 val &= ~bits;
384 writel(val, ctx->regs + SHADOWCON);
385 }
386
387 static void decon_atomic_begin(struct exynos_drm_crtc *crtc,
388 struct exynos_drm_plane *plane)
389 {
390 struct decon_context *ctx = crtc->ctx;
391
392 if (ctx->suspended)
393 return;
394
395 decon_shadow_protect_win(ctx, plane->zpos, true);
396 }
397
398 static void decon_update_plane(struct exynos_drm_crtc *crtc,
399 struct exynos_drm_plane *plane)
400 {
401 struct decon_context *ctx = crtc->ctx;
402 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
403 struct drm_plane_state *state = plane->base.state;
404 int padding;
405 unsigned long val, alpha;
406 unsigned int last_x;
407 unsigned int last_y;
408 unsigned int win = plane->zpos;
409 unsigned int bpp = state->fb->bits_per_pixel >> 3;
410 unsigned int pitch = state->fb->pitches[0];
411
412 if (ctx->suspended)
413 return;
414
415 /*
416 * SHADOWCON/PRTCON register is used for enabling timing.
417 *
418 * for example, once only width value of a register is set,
419 * if the dma is started then decon hardware could malfunction so
420 * with protect window setting, the register fields with prefix '_F'
421 * wouldn't be updated at vsync also but updated once unprotect window
422 * is set.
423 */
424
425 /* buffer start address */
426 val = (unsigned long)plane->dma_addr[0];
427 writel(val, ctx->regs + VIDW_BUF_START(win));
428
429 padding = (pitch / bpp) - state->fb->width;
430
431 /* buffer size */
432 writel(state->fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
433 writel(state->fb->height, ctx->regs + VIDW_WHOLE_Y(win));
434
435 /* offset from the start of the buffer to read */
436 writel(plane->src_x, ctx->regs + VIDW_OFFSET_X(win));
437 writel(plane->src_y, ctx->regs + VIDW_OFFSET_Y(win));
438
439 DRM_DEBUG_KMS("start addr = 0x%lx\n",
440 (unsigned long)val);
441 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
442 plane->crtc_w, plane->crtc_h);
443
444 /*
445 * OSD position.
446 * In case the window layout goes of LCD layout, DECON fails.
447 */
448 if ((plane->crtc_x + plane->crtc_w) > mode->hdisplay)
449 plane->crtc_x = mode->hdisplay - plane->crtc_w;
450 if ((plane->crtc_y + plane->crtc_h) > mode->vdisplay)
451 plane->crtc_y = mode->vdisplay - plane->crtc_h;
452
453 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) |
454 VIDOSDxA_TOPLEFT_Y(plane->crtc_y);
455 writel(val, ctx->regs + VIDOSD_A(win));
456
457 last_x = plane->crtc_x + plane->crtc_w;
458 if (last_x)
459 last_x--;
460 last_y = plane->crtc_y + plane->crtc_h;
461 if (last_y)
462 last_y--;
463
464 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
465
466 writel(val, ctx->regs + VIDOSD_B(win));
467
468 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
469 plane->crtc_x, plane->crtc_y, last_x, last_y);
470
471 /* OSD alpha */
472 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
473 VIDOSDxC_ALPHA0_G_F(0x0) |
474 VIDOSDxC_ALPHA0_B_F(0x0);
475
476 writel(alpha, ctx->regs + VIDOSD_C(win));
477
478 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
479 VIDOSDxD_ALPHA1_G_F(0xff) |
480 VIDOSDxD_ALPHA1_B_F(0xff);
481
482 writel(alpha, ctx->regs + VIDOSD_D(win));
483
484 decon_win_set_pixfmt(ctx, win, state->fb);
485
486 /* hardware window 0 doesn't support color key. */
487 if (win != 0)
488 decon_win_set_colkey(ctx, win);
489
490 /* wincon */
491 val = readl(ctx->regs + WINCON(win));
492 val |= WINCONx_TRIPLE_BUF_MODE;
493 val |= WINCONx_ENWIN;
494 writel(val, ctx->regs + WINCON(win));
495
496 /* Enable DMA channel and unprotect windows */
497 decon_shadow_protect_win(ctx, win, false);
498
499 val = readl(ctx->regs + DECON_UPDATE);
500 val |= DECON_UPDATE_STANDALONE_F;
501 writel(val, ctx->regs + DECON_UPDATE);
502 }
503
504 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
505 struct exynos_drm_plane *plane)
506 {
507 struct decon_context *ctx = crtc->ctx;
508 unsigned int win = plane->zpos;
509 u32 val;
510
511 if (ctx->suspended)
512 return;
513
514 /* protect windows */
515 decon_shadow_protect_win(ctx, win, true);
516
517 /* wincon */
518 val = readl(ctx->regs + WINCON(win));
519 val &= ~WINCONx_ENWIN;
520 writel(val, ctx->regs + WINCON(win));
521
522 val = readl(ctx->regs + DECON_UPDATE);
523 val |= DECON_UPDATE_STANDALONE_F;
524 writel(val, ctx->regs + DECON_UPDATE);
525 }
526
527 static void decon_atomic_flush(struct exynos_drm_crtc *crtc,
528 struct exynos_drm_plane *plane)
529 {
530 struct decon_context *ctx = crtc->ctx;
531
532 if (ctx->suspended)
533 return;
534
535 decon_shadow_protect_win(ctx, plane->zpos, false);
536 }
537
538 static void decon_init(struct decon_context *ctx)
539 {
540 u32 val;
541
542 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
543
544 val = VIDOUTCON0_DISP_IF_0_ON;
545 if (!ctx->i80_if)
546 val |= VIDOUTCON0_RGBIF;
547 writel(val, ctx->regs + VIDOUTCON0);
548
549 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
550
551 if (!ctx->i80_if)
552 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
553 }
554
555 static void decon_enable(struct exynos_drm_crtc *crtc)
556 {
557 struct decon_context *ctx = crtc->ctx;
558 int ret;
559
560 if (!ctx->suspended)
561 return;
562
563 ctx->suspended = false;
564
565 pm_runtime_get_sync(ctx->dev);
566
567 ret = clk_prepare_enable(ctx->pclk);
568 if (ret < 0) {
569 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
570 return;
571 }
572
573 ret = clk_prepare_enable(ctx->aclk);
574 if (ret < 0) {
575 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
576 return;
577 }
578
579 ret = clk_prepare_enable(ctx->eclk);
580 if (ret < 0) {
581 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
582 return;
583 }
584
585 ret = clk_prepare_enable(ctx->vclk);
586 if (ret < 0) {
587 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
588 return;
589 }
590
591 decon_init(ctx);
592
593 /* if vblank was enabled status, enable it again. */
594 if (test_and_clear_bit(0, &ctx->irq_flags))
595 decon_enable_vblank(ctx->crtc);
596
597 decon_commit(ctx->crtc);
598 }
599
600 static void decon_disable(struct exynos_drm_crtc *crtc)
601 {
602 struct decon_context *ctx = crtc->ctx;
603 int i;
604
605 if (ctx->suspended)
606 return;
607
608 /*
609 * We need to make sure that all windows are disabled before we
610 * suspend that connector. Otherwise we might try to scan from
611 * a destroyed buffer later.
612 */
613 for (i = 0; i < WINDOWS_NR; i++)
614 decon_disable_plane(crtc, &ctx->planes[i]);
615
616 clk_disable_unprepare(ctx->vclk);
617 clk_disable_unprepare(ctx->eclk);
618 clk_disable_unprepare(ctx->aclk);
619 clk_disable_unprepare(ctx->pclk);
620
621 pm_runtime_put_sync(ctx->dev);
622
623 ctx->suspended = true;
624 }
625
626 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
627 .enable = decon_enable,
628 .disable = decon_disable,
629 .commit = decon_commit,
630 .enable_vblank = decon_enable_vblank,
631 .disable_vblank = decon_disable_vblank,
632 .wait_for_vblank = decon_wait_for_vblank,
633 .atomic_begin = decon_atomic_begin,
634 .update_plane = decon_update_plane,
635 .disable_plane = decon_disable_plane,
636 .atomic_flush = decon_atomic_flush,
637 };
638
639
640 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
641 {
642 struct decon_context *ctx = (struct decon_context *)dev_id;
643 u32 val, clear_bit;
644 int win;
645
646 val = readl(ctx->regs + VIDINTCON1);
647
648 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
649 if (val & clear_bit)
650 writel(clear_bit, ctx->regs + VIDINTCON1);
651
652 /* check the crtc is detached already from encoder */
653 if (ctx->pipe < 0 || !ctx->drm_dev)
654 goto out;
655
656 if (!ctx->i80_if) {
657 drm_crtc_handle_vblank(&ctx->crtc->base);
658 for (win = 0 ; win < WINDOWS_NR ; win++) {
659 struct exynos_drm_plane *plane = &ctx->planes[win];
660
661 if (!plane->pending_fb)
662 continue;
663
664 exynos_drm_crtc_finish_update(ctx->crtc, plane);
665 }
666
667 /* set wait vsync event to zero and wake up queue. */
668 if (atomic_read(&ctx->wait_vsync_event)) {
669 atomic_set(&ctx->wait_vsync_event, 0);
670 wake_up(&ctx->wait_vsync_queue);
671 }
672 }
673 out:
674 return IRQ_HANDLED;
675 }
676
677 static int decon_bind(struct device *dev, struct device *master, void *data)
678 {
679 struct decon_context *ctx = dev_get_drvdata(dev);
680 struct drm_device *drm_dev = data;
681 struct exynos_drm_plane *exynos_plane;
682 enum drm_plane_type type;
683 unsigned int zpos;
684 int ret;
685
686 ret = decon_ctx_initialize(ctx, drm_dev);
687 if (ret) {
688 DRM_ERROR("decon_ctx_initialize failed.\n");
689 return ret;
690 }
691
692 for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
693 type = exynos_plane_get_type(zpos, CURSOR_WIN);
694 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
695 1 << ctx->pipe, type, decon_formats,
696 ARRAY_SIZE(decon_formats), zpos);
697 if (ret)
698 return ret;
699 }
700
701 exynos_plane = &ctx->planes[DEFAULT_WIN];
702 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
703 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
704 &decon_crtc_ops, ctx);
705 if (IS_ERR(ctx->crtc)) {
706 decon_ctx_remove(ctx);
707 return PTR_ERR(ctx->crtc);
708 }
709
710 if (ctx->encoder)
711 exynos_dpi_bind(drm_dev, ctx->encoder);
712
713 return 0;
714
715 }
716
717 static void decon_unbind(struct device *dev, struct device *master,
718 void *data)
719 {
720 struct decon_context *ctx = dev_get_drvdata(dev);
721
722 decon_disable(ctx->crtc);
723
724 if (ctx->encoder)
725 exynos_dpi_remove(ctx->encoder);
726
727 decon_ctx_remove(ctx);
728 }
729
730 static const struct component_ops decon_component_ops = {
731 .bind = decon_bind,
732 .unbind = decon_unbind,
733 };
734
735 static int decon_probe(struct platform_device *pdev)
736 {
737 struct device *dev = &pdev->dev;
738 struct decon_context *ctx;
739 struct device_node *i80_if_timings;
740 struct resource *res;
741 int ret;
742
743 if (!dev->of_node)
744 return -ENODEV;
745
746 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
747 if (!ctx)
748 return -ENOMEM;
749
750 ctx->dev = dev;
751 ctx->suspended = true;
752
753 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
754 if (i80_if_timings)
755 ctx->i80_if = true;
756 of_node_put(i80_if_timings);
757
758 ctx->regs = of_iomap(dev->of_node, 0);
759 if (!ctx->regs)
760 return -ENOMEM;
761
762 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
763 if (IS_ERR(ctx->pclk)) {
764 dev_err(dev, "failed to get bus clock pclk\n");
765 ret = PTR_ERR(ctx->pclk);
766 goto err_iounmap;
767 }
768
769 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
770 if (IS_ERR(ctx->aclk)) {
771 dev_err(dev, "failed to get bus clock aclk\n");
772 ret = PTR_ERR(ctx->aclk);
773 goto err_iounmap;
774 }
775
776 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
777 if (IS_ERR(ctx->eclk)) {
778 dev_err(dev, "failed to get eclock\n");
779 ret = PTR_ERR(ctx->eclk);
780 goto err_iounmap;
781 }
782
783 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
784 if (IS_ERR(ctx->vclk)) {
785 dev_err(dev, "failed to get vclock\n");
786 ret = PTR_ERR(ctx->vclk);
787 goto err_iounmap;
788 }
789
790 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
791 ctx->i80_if ? "lcd_sys" : "vsync");
792 if (!res) {
793 dev_err(dev, "irq request failed.\n");
794 ret = -ENXIO;
795 goto err_iounmap;
796 }
797
798 ret = devm_request_irq(dev, res->start, decon_irq_handler,
799 0, "drm_decon", ctx);
800 if (ret) {
801 dev_err(dev, "irq request failed.\n");
802 goto err_iounmap;
803 }
804
805 init_waitqueue_head(&ctx->wait_vsync_queue);
806 atomic_set(&ctx->wait_vsync_event, 0);
807
808 platform_set_drvdata(pdev, ctx);
809
810 ctx->encoder = exynos_dpi_probe(dev);
811 if (IS_ERR(ctx->encoder)) {
812 ret = PTR_ERR(ctx->encoder);
813 goto err_iounmap;
814 }
815
816 pm_runtime_enable(dev);
817
818 ret = component_add(dev, &decon_component_ops);
819 if (ret)
820 goto err_disable_pm_runtime;
821
822 return ret;
823
824 err_disable_pm_runtime:
825 pm_runtime_disable(dev);
826
827 err_iounmap:
828 iounmap(ctx->regs);
829
830 return ret;
831 }
832
833 static int decon_remove(struct platform_device *pdev)
834 {
835 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
836
837 pm_runtime_disable(&pdev->dev);
838
839 iounmap(ctx->regs);
840
841 component_del(&pdev->dev, &decon_component_ops);
842
843 return 0;
844 }
845
846 struct platform_driver decon_driver = {
847 .probe = decon_probe,
848 .remove = decon_remove,
849 .driver = {
850 .name = "exynos-decon",
851 .of_match_table = decon_driver_dt_match,
852 },
853 };
Linux with added FPC-III support