2 * drivers/net/phy/davicom.c
4 * Driver for Davicom PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/string.h>
18 #include <linux/errno.h>
19 #include <linux/unistd.h>
20 #include <linux/interrupt.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/skbuff.h>
26 #include <linux/spinlock.h>
28 #include <linux/module.h>
29 #include <linux/mii.h>
30 #include <linux/ethtool.h>
31 #include <linux/phy.h>
35 #include <asm/uaccess.h>
37 #define MII_DM9161_SCR 0x10
38 #define MII_DM9161_SCR_INIT 0x0610
39 #define MII_DM9161_SCR_RMII 0x0100
41 /* DM9161 Interrupt Register */
42 #define MII_DM9161_INTR 0x15
43 #define MII_DM9161_INTR_PEND 0x8000
44 #define MII_DM9161_INTR_DPLX_MASK 0x0800
45 #define MII_DM9161_INTR_SPD_MASK 0x0400
46 #define MII_DM9161_INTR_LINK_MASK 0x0200
47 #define MII_DM9161_INTR_MASK 0x0100
48 #define MII_DM9161_INTR_DPLX_CHANGE 0x0010
49 #define MII_DM9161_INTR_SPD_CHANGE 0x0008
50 #define MII_DM9161_INTR_LINK_CHANGE 0x0004
51 #define MII_DM9161_INTR_INIT 0x0000
52 #define MII_DM9161_INTR_STOP \
53 (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
54 | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
56 /* DM9161 10BT Configuration/Status */
57 #define MII_DM9161_10BTCSR 0x12
58 #define MII_DM9161_10BTCSR_INIT 0x7800
60 MODULE_DESCRIPTION("Davicom PHY driver");
61 MODULE_AUTHOR("Andy Fleming");
62 MODULE_LICENSE("GPL");
65 #define DM9161_DELAY 1
66 static int dm9161_config_intr(struct phy_device
*phydev
)
70 temp
= phy_read(phydev
, MII_DM9161_INTR
);
75 if (PHY_INTERRUPT_ENABLED
== phydev
->interrupts
)
76 temp
&= ~(MII_DM9161_INTR_STOP
);
78 temp
|= MII_DM9161_INTR_STOP
;
80 temp
= phy_write(phydev
, MII_DM9161_INTR
, temp
);
85 static int dm9161_config_aneg(struct phy_device
*phydev
)
90 err
= phy_write(phydev
, MII_BMCR
, BMCR_ISOLATE
);
95 /* Configure the new settings */
96 err
= genphy_config_aneg(phydev
);
104 static int dm9161_config_init(struct phy_device
*phydev
)
108 /* Isolate the PHY */
109 err
= phy_write(phydev
, MII_BMCR
, BMCR_ISOLATE
);
114 switch (phydev
->interface
) {
115 case PHY_INTERFACE_MODE_MII
:
116 temp
= MII_DM9161_SCR_INIT
;
118 case PHY_INTERFACE_MODE_RMII
:
119 temp
= MII_DM9161_SCR_INIT
| MII_DM9161_SCR_RMII
;
125 /* Do not bypass the scrambler/descrambler */
126 err
= phy_write(phydev
, MII_DM9161_SCR
, temp
);
130 /* Clear 10BTCSR to default */
131 err
= phy_write(phydev
, MII_DM9161_10BTCSR
, MII_DM9161_10BTCSR_INIT
);
136 /* Reconnect the PHY, and enable Autonegotiation */
137 return phy_write(phydev
, MII_BMCR
, BMCR_ANENABLE
);
140 static int dm9161_ack_interrupt(struct phy_device
*phydev
)
142 int err
= phy_read(phydev
, MII_DM9161_INTR
);
144 return (err
< 0) ? err
: 0;
147 static struct phy_driver dm91xx_driver
[] = {
149 .phy_id
= 0x0181b880,
150 .name
= "Davicom DM9161E",
151 .phy_id_mask
= 0x0ffffff0,
152 .features
= PHY_BASIC_FEATURES
,
153 .flags
= PHY_HAS_INTERRUPT
,
154 .config_init
= dm9161_config_init
,
155 .config_aneg
= dm9161_config_aneg
,
156 .read_status
= genphy_read_status
,
157 .ack_interrupt
= dm9161_ack_interrupt
,
158 .config_intr
= dm9161_config_intr
,
159 .driver
= { .owner
= THIS_MODULE
,},
161 .phy_id
= 0x0181b8b0,
162 .name
= "Davicom DM9161B/C",
163 .phy_id_mask
= 0x0ffffff0,
164 .features
= PHY_BASIC_FEATURES
,
165 .flags
= PHY_HAS_INTERRUPT
,
166 .config_init
= dm9161_config_init
,
167 .config_aneg
= dm9161_config_aneg
,
168 .read_status
= genphy_read_status
,
169 .ack_interrupt
= dm9161_ack_interrupt
,
170 .config_intr
= dm9161_config_intr
,
171 .driver
= { .owner
= THIS_MODULE
,},
173 .phy_id
= 0x0181b8a0,
174 .name
= "Davicom DM9161A",
175 .phy_id_mask
= 0x0ffffff0,
176 .features
= PHY_BASIC_FEATURES
,
177 .flags
= PHY_HAS_INTERRUPT
,
178 .config_init
= dm9161_config_init
,
179 .config_aneg
= dm9161_config_aneg
,
180 .read_status
= genphy_read_status
,
181 .ack_interrupt
= dm9161_ack_interrupt
,
182 .config_intr
= dm9161_config_intr
,
183 .driver
= { .owner
= THIS_MODULE
,},
185 .phy_id
= 0x00181b80,
186 .name
= "Davicom DM9131",
187 .phy_id_mask
= 0x0ffffff0,
188 .features
= PHY_BASIC_FEATURES
,
189 .flags
= PHY_HAS_INTERRUPT
,
190 .config_aneg
= genphy_config_aneg
,
191 .read_status
= genphy_read_status
,
192 .ack_interrupt
= dm9161_ack_interrupt
,
193 .config_intr
= dm9161_config_intr
,
194 .driver
= { .owner
= THIS_MODULE
,},
197 module_phy_driver(dm91xx_driver
);
199 static struct mdio_device_id __maybe_unused davicom_tbl
[] = {
200 { 0x0181b880, 0x0ffffff0 },
201 { 0x0181b8b0, 0x0ffffff0 },
202 { 0x0181b8a0, 0x0ffffff0 },
203 { 0x00181b80, 0x0ffffff0 },
207 MODULE_DEVICE_TABLE(mdio
, davicom_tbl
);