drivers/mfd/stmpe.h

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License Terms: GNU General Public License, version 2
   5  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   6  */
   7
   8 #ifndef __STMPE_H
   9 #define __STMPE_H
  10
  11 #ifdef STMPE_DUMP_BYTES
  12 static inline void stmpe_dump_bytes(const char *str, const void *buf,
  13                                     size_t len)
  14 {
  15         print_hex_dump_bytes(str, DUMP_PREFIX_OFFSET, buf, len);
  16 }
  17 #else
  18 static inline void stmpe_dump_bytes(const char *str, const void *buf,
  19                                     size_t len)
  20 {
  21 }
  22 #endif
  23
  24 /**
  25  * struct stmpe_variant_block - information about block
  26  * @cell:       base mfd cell
  27  * @irq:        interrupt number to be added to each IORESOURCE_IRQ
  28  *              in the cell
  29  * @block:      block id; used for identification with platform data and for
  30  *              enable and altfunc callbacks
  31  */
  32 struct stmpe_variant_block {
  33         struct mfd_cell         *cell;
  34         int                     irq;
  35         enum stmpe_block        block;
  36 };
  37
  38 /**
  39  * struct stmpe_variant_info - variant-specific information
  40  * @name:       part name
  41  * @id_val:     content of CHIPID register
  42  * @id_mask:    bits valid in CHIPID register for comparison with id_val
  43  * @num_gpios:  number of GPIOS
  44  * @af_bits:    number of bits used to specify the alternate function
  45  * @blocks:     list of blocks present on this device
  46  * @num_blocks: number of blocks present on this device
  47  * @num_irqs:   number of internal IRQs available on this device
  48  * @enable:     callback to enable the specified blocks.
  49  *              Called with the I/O lock held.
  50  * @get_altfunc: callback to get the alternate function number for the
  51  *               specific block
  52  * @enable_autosleep: callback to configure autosleep with specified timeout
  53  */
  54 struct stmpe_variant_info {
  55         const char *name;
  56         u16 id_val;
  57         u16 id_mask;
  58         int num_gpios;
  59         int af_bits;
  60         const u8 *regs;
  61         struct stmpe_variant_block *blocks;
  62         int num_blocks;
  63         int num_irqs;
  64         int (*enable)(struct stmpe *stmpe, unsigned int blocks, bool enable);
  65         int (*get_altfunc)(struct stmpe *stmpe, enum stmpe_block block);
  66         int (*enable_autosleep)(struct stmpe *stmpe, int autosleep_timeout);
  67 };
  68
  69 #define STMPE_ICR_LSB_HIGH      (1 << 2)
  70 #define STMPE_ICR_LSB_EDGE      (1 << 1)
  71 #define STMPE_ICR_LSB_GIM       (1 << 0)
  72
  73 /*
  74  * STMPE811
  75  */
  76
  77 #define STMPE811_IRQ_TOUCH_DET          0
  78 #define STMPE811_IRQ_FIFO_TH            1
  79 #define STMPE811_IRQ_FIFO_OFLOW         2
  80 #define STMPE811_IRQ_FIFO_FULL          3
  81 #define STMPE811_IRQ_FIFO_EMPTY         4
  82 #define STMPE811_IRQ_TEMP_SENS          5
  83 #define STMPE811_IRQ_ADC                6
  84 #define STMPE811_IRQ_GPIOC              7
  85 #define STMPE811_NR_INTERNAL_IRQS       8
  86
  87 #define STMPE811_REG_CHIP_ID            0x00
  88 #define STMPE811_REG_SYS_CTRL2          0x04
  89 #define STMPE811_REG_INT_CTRL           0x09
  90 #define STMPE811_REG_INT_EN             0x0A
  91 #define STMPE811_REG_INT_STA            0x0B
  92 #define STMPE811_REG_GPIO_INT_EN        0x0C
  93 #define STMPE811_REG_GPIO_INT_STA       0x0D
  94 #define STMPE811_REG_GPIO_SET_PIN       0x10
  95 #define STMPE811_REG_GPIO_CLR_PIN       0x11
  96 #define STMPE811_REG_GPIO_MP_STA        0x12
  97 #define STMPE811_REG_GPIO_DIR           0x13
  98 #define STMPE811_REG_GPIO_ED            0x14
  99 #define STMPE811_REG_GPIO_RE            0x15
 100 #define STMPE811_REG_GPIO_FE            0x16
 101 #define STMPE811_REG_GPIO_AF            0x17
 102
 103 #define STMPE811_SYS_CTRL2_ADC_OFF      (1 << 0)
 104 #define STMPE811_SYS_CTRL2_TSC_OFF      (1 << 1)
 105 #define STMPE811_SYS_CTRL2_GPIO_OFF     (1 << 2)
 106 #define STMPE811_SYS_CTRL2_TS_OFF       (1 << 3)
 107
 108 /*
 109  * STMPE1601
 110  */
 111
 112 #define STMPE1601_IRQ_GPIOC             8
 113 #define STMPE1601_IRQ_PWM3              7
 114 #define STMPE1601_IRQ_PWM2              6
 115 #define STMPE1601_IRQ_PWM1              5
 116 #define STMPE1601_IRQ_PWM0              4
 117 #define STMPE1601_IRQ_KEYPAD_OVER       2
 118 #define STMPE1601_IRQ_KEYPAD            1
 119 #define STMPE1601_IRQ_WAKEUP            0
 120 #define STMPE1601_NR_INTERNAL_IRQS      9
 121
 122 #define STMPE1601_REG_SYS_CTRL                  0x02
 123 #define STMPE1601_REG_SYS_CTRL2                 0x03
 124 #define STMPE1601_REG_ICR_LSB                   0x11
 125 #define STMPE1601_REG_IER_LSB                   0x13
 126 #define STMPE1601_REG_ISR_MSB                   0x14
 127 #define STMPE1601_REG_CHIP_ID                   0x80
 128 #define STMPE1601_REG_INT_EN_GPIO_MASK_LSB      0x17
 129 #define STMPE1601_REG_INT_STA_GPIO_MSB          0x18
 130 #define STMPE1601_REG_GPIO_MP_LSB               0x87
 131 #define STMPE1601_REG_GPIO_SET_LSB              0x83
 132 #define STMPE1601_REG_GPIO_CLR_LSB              0x85
 133 #define STMPE1601_REG_GPIO_SET_DIR_LSB          0x89
 134 #define STMPE1601_REG_GPIO_ED_MSB               0x8A
 135 #define STMPE1601_REG_GPIO_RE_LSB               0x8D
 136 #define STMPE1601_REG_GPIO_FE_LSB               0x8F
 137 #define STMPE1601_REG_GPIO_AF_U_MSB             0x92
 138
 139 #define STMPE1601_SYS_CTRL_ENABLE_GPIO          (1 << 3)
 140 #define STMPE1601_SYS_CTRL_ENABLE_KPC           (1 << 1)
 141 #define STMPE1601_SYSCON_ENABLE_SPWM            (1 << 0)
 142
 143 /* The 1601/2403 share the same masks */
 144 #define STMPE1601_AUTOSLEEP_TIMEOUT_MASK        (0x7)
 145 #define STPME1601_AUTOSLEEP_ENABLE              (1 << 3)
 146
 147 /*
 148  * STMPE24xx
 149  */
 150
 151 #define STMPE24XX_IRQ_GPIOC             8
 152 #define STMPE24XX_IRQ_PWM2              7
 153 #define STMPE24XX_IRQ_PWM1              6
 154 #define STMPE24XX_IRQ_PWM0              5
 155 #define STMPE24XX_IRQ_ROT_OVER          4
 156 #define STMPE24XX_IRQ_ROT               3
 157 #define STMPE24XX_IRQ_KEYPAD_OVER       2
 158 #define STMPE24XX_IRQ_KEYPAD            1
 159 #define STMPE24XX_IRQ_WAKEUP            0
 160 #define STMPE24XX_NR_INTERNAL_IRQS      9
 161
 162 #define STMPE24XX_REG_SYS_CTRL          0x02
 163 #define STMPE24XX_REG_ICR_LSB           0x11
 164 #define STMPE24XX_REG_IER_LSB           0x13
 165 #define STMPE24XX_REG_ISR_MSB           0x14
 166 #define STMPE24XX_REG_CHIP_ID           0x80
 167 #define STMPE24XX_REG_IEGPIOR_LSB       0x18
 168 #define STMPE24XX_REG_ISGPIOR_MSB       0x19
 169 #define STMPE24XX_REG_GPMR_LSB          0xA5
 170 #define STMPE24XX_REG_GPSR_LSB          0x85
 171 #define STMPE24XX_REG_GPCR_LSB          0x88
 172 #define STMPE24XX_REG_GPDR_LSB          0x8B
 173 #define STMPE24XX_REG_GPEDR_MSB         0x8C
 174 #define STMPE24XX_REG_GPRER_LSB         0x91
 175 #define STMPE24XX_REG_GPFER_LSB         0x94
 176 #define STMPE24XX_REG_GPAFR_U_MSB       0x9B
 177
 178 #define STMPE24XX_SYS_CTRL_ENABLE_GPIO          (1 << 3)
 179 #define STMPE24XX_SYSCON_ENABLE_PWM             (1 << 2)
 180 #define STMPE24XX_SYS_CTRL_ENABLE_KPC           (1 << 1)
 181 #define STMPE24XX_SYSCON_ENABLE_ROT             (1 << 0)
 182
 183 #endif