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i2c: gpio: fault-injector: refactor incomplete transfer
[linux/fpc-iii.git] / drivers / edac / altera_edac.c
blobd0d5c4dbe09739450255955c46046a86d4433ac4
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
6 */
7
8 #include <asm/cacheflush.h>
9 #include <linux/ctype.h>
10 #include <linux/delay.h>
11 #include <linux/edac.h>
12 #include <linux/genalloc.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/notifier.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_platform.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/types.h>
24 #include <linux/uaccess.h>
25
26 #include "altera_edac.h"
27 #include "edac_module.h"
28
29 #define EDAC_MOD_STR "altera_edac"
30 #define EDAC_DEVICE "Altera"
31
32 static const struct altr_sdram_prv_data c5_data = {
33 .ecc_ctrl_offset = CV_CTLCFG_OFST,
34 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
35 .ecc_stat_offset = CV_DRAMSTS_OFST,
36 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
37 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
38 .ecc_saddr_offset = CV_ERRADDR_OFST,
39 .ecc_daddr_offset = CV_ERRADDR_OFST,
40 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
41 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
42 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
43 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
44 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
45 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
46 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
47 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
48 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
49 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
50 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
51 };
52
53 static const struct altr_sdram_prv_data a10_data = {
54 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
55 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
56 .ecc_stat_offset = A10_INTSTAT_OFST,
57 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
58 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
59 .ecc_saddr_offset = A10_SERRADDR_OFST,
60 .ecc_daddr_offset = A10_DERRADDR_OFST,
61 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
62 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
63 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
64 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
65 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
66 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
67 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
68 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
69 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
70 };
71
72 static const struct altr_sdram_prv_data s10_data = {
73 .ecc_ctrl_offset = S10_ECCCTRL1_OFST,
74 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
75 .ecc_stat_offset = S10_INTSTAT_OFST,
76 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
77 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
78 .ecc_saddr_offset = S10_SERRADDR_OFST,
79 .ecc_daddr_offset = S10_DERRADDR_OFST,
80 .ecc_irq_en_offset = S10_ERRINTEN_OFST,
81 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
82 .ecc_irq_clr_offset = S10_INTSTAT_OFST,
83 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
84 .ecc_cnt_rst_offset = S10_ECCCTRL1_OFST,
85 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
86 .ce_ue_trgr_offset = S10_DIAGINTTEST_OFST,
87 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
88 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
89 };
90
91 /*********************** EDAC Memory Controller Functions ****************/
92
93 /* The SDRAM controller uses the EDAC Memory Controller framework. */
94
95 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
96 {
97 struct mem_ctl_info *mci = dev_id;
98 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
99 const struct altr_sdram_prv_data *priv = drvdata->data;
100 u32 status, err_count = 1, err_addr;
101
102 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
103
104 if (status & priv->ecc_stat_ue_mask) {
105 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
106 &err_addr);
107 if (priv->ecc_uecnt_offset)
108 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
109 &err_count);
110 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
111 err_count, err_addr);
112 }
113 if (status & priv->ecc_stat_ce_mask) {
114 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
115 &err_addr);
116 if (priv->ecc_uecnt_offset)
117 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
118 &err_count);
119 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
120 err_addr >> PAGE_SHIFT,
121 err_addr & ~PAGE_MASK, 0,
122 0, 0, -1, mci->ctl_name, "");
123 /* Clear IRQ to resume */
124 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
125 priv->ecc_irq_clr_mask);
126
127 return IRQ_HANDLED;
128 }
129 return IRQ_NONE;
130 }
131
132 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
133 const char __user *data,
134 size_t count, loff_t *ppos)
135 {
136 struct mem_ctl_info *mci = file->private_data;
137 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
138 const struct altr_sdram_prv_data *priv = drvdata->data;
139 u32 *ptemp;
140 dma_addr_t dma_handle;
141 u32 reg, read_reg;
142
143 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
144 if (!ptemp) {
145 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
146 edac_printk(KERN_ERR, EDAC_MC,
147 "Inject: Buffer Allocation error\n");
148 return -ENOMEM;
149 }
150
151 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
152 &read_reg);
153 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
154
155 /* Error are injected by writing a word while the SBE or DBE
156 * bit in the CTLCFG register is set. Reading the word will
157 * trigger the SBE or DBE error and the corresponding IRQ.
158 */
159 if (count == 3) {
160 edac_printk(KERN_ALERT, EDAC_MC,
161 "Inject Double bit error\n");
162 local_irq_disable();
163 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
164 (read_reg | priv->ue_set_mask));
165 local_irq_enable();
166 } else {
167 edac_printk(KERN_ALERT, EDAC_MC,
168 "Inject Single bit error\n");
169 local_irq_disable();
170 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
171 (read_reg | priv->ce_set_mask));
172 local_irq_enable();
173 }
174
175 ptemp[0] = 0x5A5A5A5A;
176 ptemp[1] = 0xA5A5A5A5;
177
178 /* Clear the error injection bits */
179 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
180 /* Ensure it has been written out */
181 wmb();
182
183 /*
184 * To trigger the error, we need to read the data back
185 * (the data was written with errors above).
186 * The READ_ONCE macros and printk are used to prevent the
187 * the compiler optimizing these reads out.
188 */
189 reg = READ_ONCE(ptemp[0]);
190 read_reg = READ_ONCE(ptemp[1]);
191 /* Force Read */
192 rmb();
193
194 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
195 reg, read_reg);
196
197 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
198
199 return count;
200 }
201
202 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
203 .open = simple_open,
204 .write = altr_sdr_mc_err_inject_write,
205 .llseek = generic_file_llseek,
206 };
207
208 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
209 {
210 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
211 return;
212
213 if (!mci->debugfs)
214 return;
215
216 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
217 &altr_sdr_mc_debug_inject_fops);
218 }
219
220 /* Get total memory size from Open Firmware DTB */
221 static unsigned long get_total_mem(void)
222 {
223 struct device_node *np = NULL;
224 struct resource res;
225 int ret;
226 unsigned long total_mem = 0;
227
228 for_each_node_by_type(np, "memory") {
229 ret = of_address_to_resource(np, 0, &res);
230 if (ret)
231 continue;
232
233 total_mem += resource_size(&res);
234 }
235 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
236 return total_mem;
237 }
238
239 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
240 { .compatible = "altr,sdram-edac", .data = &c5_data},
241 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
242 { .compatible = "altr,sdram-edac-s10", .data = &s10_data},
243 {},
244 };
245 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
246
247 static int a10_init(struct regmap *mc_vbase)
248 {
249 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
250 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
251 edac_printk(KERN_ERR, EDAC_MC,
252 "Error setting SB IRQ mode\n");
253 return -ENODEV;
254 }
255
256 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
257 edac_printk(KERN_ERR, EDAC_MC,
258 "Error setting trigger count\n");
259 return -ENODEV;
260 }
261
262 return 0;
263 }
264
265 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
266 {
267 void __iomem *sm_base;
268 int ret = 0;
269
270 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
271 dev_name(&pdev->dev))) {
272 edac_printk(KERN_ERR, EDAC_MC,
273 "Unable to request mem region\n");
274 return -EBUSY;
275 }
276
277 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
278 if (!sm_base) {
279 edac_printk(KERN_ERR, EDAC_MC,
280 "Unable to ioremap device\n");
281
282 ret = -ENOMEM;
283 goto release;
284 }
285
286 iowrite32(mask, sm_base);
287
288 iounmap(sm_base);
289
290 release:
291 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
292
293 return ret;
294 }
295
296 static int altr_sdram_probe(struct platform_device *pdev)
297 {
298 const struct of_device_id *id;
299 struct edac_mc_layer layers[2];
300 struct mem_ctl_info *mci;
301 struct altr_sdram_mc_data *drvdata;
302 const struct altr_sdram_prv_data *priv;
303 struct regmap *mc_vbase;
304 struct dimm_info *dimm;
305 u32 read_reg;
306 int irq, irq2, res = 0;
307 unsigned long mem_size, irqflags = 0;
308
309 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
310 if (!id)
311 return -ENODEV;
312
313 /* Grab the register range from the sdr controller in device tree */
314 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
315 "altr,sdr-syscon");
316 if (IS_ERR(mc_vbase)) {
317 edac_printk(KERN_ERR, EDAC_MC,
318 "regmap for altr,sdr-syscon lookup failed.\n");
319 return -ENODEV;
320 }
321
322 /* Check specific dependencies for the module */
323 priv = of_match_node(altr_sdram_ctrl_of_match,
324 pdev->dev.of_node)->data;
325
326 /* Validate the SDRAM controller has ECC enabled */
327 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
328 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
329 edac_printk(KERN_ERR, EDAC_MC,
330 "No ECC/ECC disabled [0x%08X]\n", read_reg);
331 return -ENODEV;
332 }
333
334 /* Grab memory size from device tree. */
335 mem_size = get_total_mem();
336 if (!mem_size) {
337 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
338 return -ENODEV;
339 }
340
341 /* Ensure the SDRAM Interrupt is disabled */
342 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
343 priv->ecc_irq_en_mask, 0)) {
344 edac_printk(KERN_ERR, EDAC_MC,
345 "Error disabling SDRAM ECC IRQ\n");
346 return -ENODEV;
347 }
348
349 /* Toggle to clear the SDRAM Error count */
350 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
351 priv->ecc_cnt_rst_mask,
352 priv->ecc_cnt_rst_mask)) {
353 edac_printk(KERN_ERR, EDAC_MC,
354 "Error clearing SDRAM ECC count\n");
355 return -ENODEV;
356 }
357
358 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
359 priv->ecc_cnt_rst_mask, 0)) {
360 edac_printk(KERN_ERR, EDAC_MC,
361 "Error clearing SDRAM ECC count\n");
362 return -ENODEV;
363 }
364
365 irq = platform_get_irq(pdev, 0);
366 if (irq < 0) {
367 edac_printk(KERN_ERR, EDAC_MC,
368 "No irq %d in DT\n", irq);
369 return -ENODEV;
370 }
371
372 /* Arria10 has a 2nd IRQ */
373 irq2 = platform_get_irq(pdev, 1);
374
375 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
376 layers[0].size = 1;
377 layers[0].is_virt_csrow = true;
378 layers[1].type = EDAC_MC_LAYER_CHANNEL;
379 layers[1].size = 1;
380 layers[1].is_virt_csrow = false;
381 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
382 sizeof(struct altr_sdram_mc_data));
383 if (!mci)
384 return -ENOMEM;
385
386 mci->pdev = &pdev->dev;
387 drvdata = mci->pvt_info;
388 drvdata->mc_vbase = mc_vbase;
389 drvdata->data = priv;
390 platform_set_drvdata(pdev, mci);
391
392 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
393 edac_printk(KERN_ERR, EDAC_MC,
394 "Unable to get managed device resource\n");
395 res = -ENOMEM;
396 goto free;
397 }
398
399 mci->mtype_cap = MEM_FLAG_DDR3;
400 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
401 mci->edac_cap = EDAC_FLAG_SECDED;
402 mci->mod_name = EDAC_MOD_STR;
403 mci->ctl_name = dev_name(&pdev->dev);
404 mci->scrub_mode = SCRUB_SW_SRC;
405 mci->dev_name = dev_name(&pdev->dev);
406
407 dimm = *mci->dimms;
408 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
409 dimm->grain = 8;
410 dimm->dtype = DEV_X8;
411 dimm->mtype = MEM_DDR3;
412 dimm->edac_mode = EDAC_SECDED;
413
414 res = edac_mc_add_mc(mci);
415 if (res < 0)
416 goto err;
417
418 /* Only the Arria10 has separate IRQs */
419 if (irq2 > 0) {
420 /* Arria10 specific initialization */
421 res = a10_init(mc_vbase);
422 if (res < 0)
423 goto err2;
424
425 res = devm_request_irq(&pdev->dev, irq2,
426 altr_sdram_mc_err_handler,
427 IRQF_SHARED, dev_name(&pdev->dev), mci);
428 if (res < 0) {
429 edac_mc_printk(mci, KERN_ERR,
430 "Unable to request irq %d\n", irq2);
431 res = -ENODEV;
432 goto err2;
433 }
434
435 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
436 if (res < 0)
437 goto err2;
438
439 irqflags = IRQF_SHARED;
440 }
441
442 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
443 irqflags, dev_name(&pdev->dev), mci);
444 if (res < 0) {
445 edac_mc_printk(mci, KERN_ERR,
446 "Unable to request irq %d\n", irq);
447 res = -ENODEV;
448 goto err2;
449 }
450
451 /* Infrastructure ready - enable the IRQ */
452 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
453 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
454 edac_mc_printk(mci, KERN_ERR,
455 "Error enabling SDRAM ECC IRQ\n");
456 res = -ENODEV;
457 goto err2;
458 }
459
460 altr_sdr_mc_create_debugfs_nodes(mci);
461
462 devres_close_group(&pdev->dev, NULL);
463
464 return 0;
465
466 err2:
467 edac_mc_del_mc(&pdev->dev);
468 err:
469 devres_release_group(&pdev->dev, NULL);
470 free:
471 edac_mc_free(mci);
472 edac_printk(KERN_ERR, EDAC_MC,
473 "EDAC Probe Failed; Error %d\n", res);
474
475 return res;
476 }
477
478 static int altr_sdram_remove(struct platform_device *pdev)
479 {
480 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
481
482 edac_mc_del_mc(&pdev->dev);
483 edac_mc_free(mci);
484 platform_set_drvdata(pdev, NULL);
485
486 return 0;
487 }
488
489 /**************** Stratix 10 EDAC Memory Controller Functions ************/
490
491 /**
492 * s10_protected_reg_write
493 * Write to a protected SMC register.
494 * @context: Not used.
495 * @reg: Address of register
496 * @value: Value to write
497 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
498 * INTEL_SIP_SMC_REG_ERROR on error
499 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
500 */
501 static int s10_protected_reg_write(void *context, unsigned int reg,
502 unsigned int val)
503 {
504 struct arm_smccc_res result;
505
506 arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, reg, val, 0, 0,
507 0, 0, 0, &result);
508
509 return (int)result.a0;
510 }
511
512 /**
513 * s10_protected_reg_read
514 * Read the status of a protected SMC register
515 * @context: Not used.
516 * @reg: Address of register
517 * @value: Value read.
518 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
519 * INTEL_SIP_SMC_REG_ERROR on error
520 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
521 */
522 static int s10_protected_reg_read(void *context, unsigned int reg,
523 unsigned int *val)
524 {
525 struct arm_smccc_res result;
526
527 arm_smccc_smc(INTEL_SIP_SMC_REG_READ, reg, 0, 0, 0,
528 0, 0, 0, &result);
529
530 *val = (unsigned int)result.a1;
531
532 return (int)result.a0;
533 }
534
535 static bool s10_sdram_writeable_reg(struct device *dev, unsigned int reg)
536 {
537 switch (reg) {
538 case S10_ECCCTRL1_OFST:
539 case S10_ERRINTEN_OFST:
540 case S10_INTMODE_OFST:
541 case S10_INTSTAT_OFST:
542 case S10_DIAGINTTEST_OFST:
543 case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
544 case S10_SYSMGR_ECC_INTMASK_SET_OFST:
545 case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
546 return true;
547 }
548 return false;
549 }
550
551 static bool s10_sdram_readable_reg(struct device *dev, unsigned int reg)
552 {
553 switch (reg) {
554 case S10_ECCCTRL1_OFST:
555 case S10_ERRINTEN_OFST:
556 case S10_INTMODE_OFST:
557 case S10_INTSTAT_OFST:
558 case S10_DERRADDR_OFST:
559 case S10_SERRADDR_OFST:
560 case S10_DIAGINTTEST_OFST:
561 case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
562 case S10_SYSMGR_ECC_INTMASK_SET_OFST:
563 case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
564 case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
565 case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
566 return true;
567 }
568 return false;
569 }
570
571 static bool s10_sdram_volatile_reg(struct device *dev, unsigned int reg)
572 {
573 switch (reg) {
574 case S10_ECCCTRL1_OFST:
575 case S10_ERRINTEN_OFST:
576 case S10_INTMODE_OFST:
577 case S10_INTSTAT_OFST:
578 case S10_DERRADDR_OFST:
579 case S10_SERRADDR_OFST:
580 case S10_DIAGINTTEST_OFST:
581 case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
582 case S10_SYSMGR_ECC_INTMASK_SET_OFST:
583 case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
584 case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
585 case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
586 return true;
587 }
588 return false;
589 }
590
591 static const struct regmap_config s10_sdram_regmap_cfg = {
592 .name = "s10_ddr",
593 .reg_bits = 32,
594 .reg_stride = 4,
595 .val_bits = 32,
596 .max_register = 0xffffffff,
597 .writeable_reg = s10_sdram_writeable_reg,
598 .readable_reg = s10_sdram_readable_reg,
599 .volatile_reg = s10_sdram_volatile_reg,
600 .reg_read = s10_protected_reg_read,
601 .reg_write = s10_protected_reg_write,
602 .use_single_rw = true,
603 };
604
605 static int altr_s10_sdram_probe(struct platform_device *pdev)
606 {
607 const struct of_device_id *id;
608 struct edac_mc_layer layers[2];
609 struct mem_ctl_info *mci;
610 struct altr_sdram_mc_data *drvdata;
611 const struct altr_sdram_prv_data *priv;
612 struct regmap *regmap;
613 struct dimm_info *dimm;
614 u32 read_reg;
615 int irq, ret = 0;
616 unsigned long mem_size;
617
618 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
619 if (!id)
620 return -ENODEV;
621
622 /* Grab specific offsets and masks for Stratix10 */
623 priv = of_match_node(altr_sdram_ctrl_of_match,
624 pdev->dev.of_node)->data;
625
626 regmap = devm_regmap_init(&pdev->dev, NULL, (void *)priv,
627 &s10_sdram_regmap_cfg);
628 if (IS_ERR(regmap))
629 return PTR_ERR(regmap);
630
631 /* Validate the SDRAM controller has ECC enabled */
632 if (regmap_read(regmap, priv->ecc_ctrl_offset, &read_reg) ||
633 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
634 edac_printk(KERN_ERR, EDAC_MC,
635 "No ECC/ECC disabled [0x%08X]\n", read_reg);
636 return -ENODEV;
637 }
638
639 /* Grab memory size from device tree. */
640 mem_size = get_total_mem();
641 if (!mem_size) {
642 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
643 return -ENODEV;
644 }
645
646 /* Ensure the SDRAM Interrupt is disabled */
647 if (regmap_update_bits(regmap, priv->ecc_irq_en_offset,
648 priv->ecc_irq_en_mask, 0)) {
649 edac_printk(KERN_ERR, EDAC_MC,
650 "Error disabling SDRAM ECC IRQ\n");
651 return -ENODEV;
652 }
653
654 /* Toggle to clear the SDRAM Error count */
655 if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
656 priv->ecc_cnt_rst_mask,
657 priv->ecc_cnt_rst_mask)) {
658 edac_printk(KERN_ERR, EDAC_MC,
659 "Error clearing SDRAM ECC count\n");
660 return -ENODEV;
661 }
662
663 if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
664 priv->ecc_cnt_rst_mask, 0)) {
665 edac_printk(KERN_ERR, EDAC_MC,
666 "Error clearing SDRAM ECC count\n");
667 return -ENODEV;
668 }
669
670 irq = platform_get_irq(pdev, 0);
671 if (irq < 0) {
672 edac_printk(KERN_ERR, EDAC_MC,
673 "No irq %d in DT\n", irq);
674 return -ENODEV;
675 }
676
677 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
678 layers[0].size = 1;
679 layers[0].is_virt_csrow = true;
680 layers[1].type = EDAC_MC_LAYER_CHANNEL;
681 layers[1].size = 1;
682 layers[1].is_virt_csrow = false;
683 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
684 sizeof(struct altr_sdram_mc_data));
685 if (!mci)
686 return -ENOMEM;
687
688 mci->pdev = &pdev->dev;
689 drvdata = mci->pvt_info;
690 drvdata->mc_vbase = regmap;
691 drvdata->data = priv;
692 platform_set_drvdata(pdev, mci);
693
694 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
695 edac_printk(KERN_ERR, EDAC_MC,
696 "Unable to get managed device resource\n");
697 ret = -ENOMEM;
698 goto free;
699 }
700
701 mci->mtype_cap = MEM_FLAG_DDR3;
702 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
703 mci->edac_cap = EDAC_FLAG_SECDED;
704 mci->mod_name = EDAC_MOD_STR;
705 mci->ctl_name = dev_name(&pdev->dev);
706 mci->scrub_mode = SCRUB_SW_SRC;
707 mci->dev_name = dev_name(&pdev->dev);
708
709 dimm = *mci->dimms;
710 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
711 dimm->grain = 8;
712 dimm->dtype = DEV_X8;
713 dimm->mtype = MEM_DDR3;
714 dimm->edac_mode = EDAC_SECDED;
715
716 ret = edac_mc_add_mc(mci);
717 if (ret < 0)
718 goto err;
719
720 ret = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
721 IRQF_SHARED, dev_name(&pdev->dev), mci);
722 if (ret < 0) {
723 edac_mc_printk(mci, KERN_ERR,
724 "Unable to request irq %d\n", irq);
725 ret = -ENODEV;
726 goto err2;
727 }
728
729 if (regmap_write(regmap, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
730 S10_DDR0_IRQ_MASK)) {
731 edac_printk(KERN_ERR, EDAC_MC,
732 "Error clearing SDRAM ECC count\n");
733 return -ENODEV;
734 }
735
736 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
737 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
738 edac_mc_printk(mci, KERN_ERR,
739 "Error enabling SDRAM ECC IRQ\n");
740 ret = -ENODEV;
741 goto err2;
742 }
743
744 altr_sdr_mc_create_debugfs_nodes(mci);
745
746 devres_close_group(&pdev->dev, NULL);
747
748 return 0;
749
750 err2:
751 edac_mc_del_mc(&pdev->dev);
752 err:
753 devres_release_group(&pdev->dev, NULL);
754 free:
755 edac_mc_free(mci);
756 edac_printk(KERN_ERR, EDAC_MC,
757 "EDAC Probe Failed; Error %d\n", ret);
758
759 return ret;
760 }
761
762 static int altr_s10_sdram_remove(struct platform_device *pdev)
763 {
764 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
765
766 edac_mc_del_mc(&pdev->dev);
767 edac_mc_free(mci);
768 platform_set_drvdata(pdev, NULL);
769
770 return 0;
771 }
772
773 /************** </Stratix10 EDAC Memory Controller Functions> ***********/
774
775 /*
776 * If you want to suspend, need to disable EDAC by removing it
777 * from the device tree or defconfig.
778 */
779 #ifdef CONFIG_PM
780 static int altr_sdram_prepare(struct device *dev)
781 {
782 pr_err("Suspend not allowed when EDAC is enabled.\n");
783
784 return -EPERM;
785 }
786
787 static const struct dev_pm_ops altr_sdram_pm_ops = {
788 .prepare = altr_sdram_prepare,
789 };
790 #endif
791
792 static struct platform_driver altr_sdram_edac_driver = {
793 .probe = altr_sdram_probe,
794 .remove = altr_sdram_remove,
795 .driver = {
796 .name = "altr_sdram_edac",
797 #ifdef CONFIG_PM
798 .pm = &altr_sdram_pm_ops,
799 #endif
800 .of_match_table = altr_sdram_ctrl_of_match,
801 },
802 };
803
804 module_platform_driver(altr_sdram_edac_driver);
805
806 static struct platform_driver altr_s10_sdram_edac_driver = {
807 .probe = altr_s10_sdram_probe,
808 .remove = altr_s10_sdram_remove,
809 .driver = {
810 .name = "altr_s10_sdram_edac",
811 #ifdef CONFIG_PM
812 .pm = &altr_sdram_pm_ops,
813 #endif
814 .of_match_table = altr_sdram_ctrl_of_match,
815 },
816 };
817
818 module_platform_driver(altr_s10_sdram_edac_driver);
819
820 /************************* EDAC Parent Probe *************************/
821
822 static const struct of_device_id altr_edac_device_of_match[];
823
824 static const struct of_device_id altr_edac_of_match[] = {
825 { .compatible = "altr,socfpga-ecc-manager" },
826 {},
827 };
828 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
829
830 static int altr_edac_probe(struct platform_device *pdev)
831 {
832 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
833 NULL, &pdev->dev);
834 return 0;
835 }
836
837 static struct platform_driver altr_edac_driver = {
838 .probe = altr_edac_probe,
839 .driver = {
840 .name = "socfpga_ecc_manager",
841 .of_match_table = altr_edac_of_match,
842 },
843 };
844 module_platform_driver(altr_edac_driver);
845
846 /************************* EDAC Device Functions *************************/
847
848 /*
849 * EDAC Device Functions (shared between various IPs).
850 * The discrete memories use the EDAC Device framework. The probe
851 * and error handling functions are very similar between memories
852 * so they are shared. The memory allocation and freeing for EDAC
853 * trigger testing are different for each memory.
854 */
855
856 static const struct edac_device_prv_data ocramecc_data;
857 static const struct edac_device_prv_data l2ecc_data;
858 static const struct edac_device_prv_data a10_ocramecc_data;
859 static const struct edac_device_prv_data a10_l2ecc_data;
860
861 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
862 {
863 irqreturn_t ret_value = IRQ_NONE;
864 struct edac_device_ctl_info *dci = dev_id;
865 struct altr_edac_device_dev *drvdata = dci->pvt_info;
866 const struct edac_device_prv_data *priv = drvdata->data;
867
868 if (irq == drvdata->sb_irq) {
869 if (priv->ce_clear_mask)
870 writel(priv->ce_clear_mask, drvdata->base);
871 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
872 ret_value = IRQ_HANDLED;
873 } else if (irq == drvdata->db_irq) {
874 if (priv->ue_clear_mask)
875 writel(priv->ue_clear_mask, drvdata->base);
876 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
877 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
878 ret_value = IRQ_HANDLED;
879 } else {
880 WARN_ON(1);
881 }
882
883 return ret_value;
884 }
885
886 static ssize_t altr_edac_device_trig(struct file *file,
887 const char __user *user_buf,
888 size_t count, loff_t *ppos)
889
890 {
891 u32 *ptemp, i, error_mask;
892 int result = 0;
893 u8 trig_type;
894 unsigned long flags;
895 struct edac_device_ctl_info *edac_dci = file->private_data;
896 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
897 const struct edac_device_prv_data *priv = drvdata->data;
898 void *generic_ptr = edac_dci->dev;
899
900 if (!user_buf || get_user(trig_type, user_buf))
901 return -EFAULT;
902
903 if (!priv->alloc_mem)
904 return -ENOMEM;
905
906 /*
907 * Note that generic_ptr is initialized to the device * but in
908 * some alloc_functions, this is overridden and returns data.
909 */
910 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
911 if (!ptemp) {
912 edac_printk(KERN_ERR, EDAC_DEVICE,
913 "Inject: Buffer Allocation error\n");
914 return -ENOMEM;
915 }
916
917 if (trig_type == ALTR_UE_TRIGGER_CHAR)
918 error_mask = priv->ue_set_mask;
919 else
920 error_mask = priv->ce_set_mask;
921
922 edac_printk(KERN_ALERT, EDAC_DEVICE,
923 "Trigger Error Mask (0x%X)\n", error_mask);
924
925 local_irq_save(flags);
926 /* write ECC corrupted data out. */
927 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
928 /* Read data so we're in the correct state */
929 rmb();
930 if (READ_ONCE(ptemp[i]))
931 result = -1;
932 /* Toggle Error bit (it is latched), leave ECC enabled */
933 writel(error_mask, (drvdata->base + priv->set_err_ofst));
934 writel(priv->ecc_enable_mask, (drvdata->base +
935 priv->set_err_ofst));
936 ptemp[i] = i;
937 }
938 /* Ensure it has been written out */
939 wmb();
940 local_irq_restore(flags);
941
942 if (result)
943 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
944
945 /* Read out written data. ECC error caused here */
946 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
947 if (READ_ONCE(ptemp[i]) != i)
948 edac_printk(KERN_ERR, EDAC_DEVICE,
949 "Read doesn't match written data\n");
950
951 if (priv->free_mem)
952 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
953
954 return count;
955 }
956
957 static const struct file_operations altr_edac_device_inject_fops = {
958 .open = simple_open,
959 .write = altr_edac_device_trig,
960 .llseek = generic_file_llseek,
961 };
962
963 static ssize_t altr_edac_a10_device_trig(struct file *file,
964 const char __user *user_buf,
965 size_t count, loff_t *ppos);
966
967 static const struct file_operations altr_edac_a10_device_inject_fops = {
968 .open = simple_open,
969 .write = altr_edac_a10_device_trig,
970 .llseek = generic_file_llseek,
971 };
972
973 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
974 const struct edac_device_prv_data *priv)
975 {
976 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
977
978 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
979 return;
980
981 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
982 if (!drvdata->debugfs_dir)
983 return;
984
985 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
986 drvdata->debugfs_dir, edac_dci,
987 priv->inject_fops))
988 debugfs_remove_recursive(drvdata->debugfs_dir);
989 }
990
991 static const struct of_device_id altr_edac_device_of_match[] = {
992 #ifdef CONFIG_EDAC_ALTERA_L2C
993 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
994 #endif
995 #ifdef CONFIG_EDAC_ALTERA_OCRAM
996 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
997 #endif
998 {},
999 };
1000 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
1001
1002 /*
1003 * altr_edac_device_probe()
1004 * This is a generic EDAC device driver that will support
1005 * various Altera memory devices such as the L2 cache ECC and
1006 * OCRAM ECC as well as the memories for other peripherals.
1007 * Module specific initialization is done by passing the
1008 * function index in the device tree.
1009 */
1010 static int altr_edac_device_probe(struct platform_device *pdev)
1011 {
1012 struct edac_device_ctl_info *dci;
1013 struct altr_edac_device_dev *drvdata;
1014 struct resource *r;
1015 int res = 0;
1016 struct device_node *np = pdev->dev.of_node;
1017 char *ecc_name = (char *)np->name;
1018 static int dev_instance;
1019
1020 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
1021 edac_printk(KERN_ERR, EDAC_DEVICE,
1022 "Unable to open devm\n");
1023 return -ENOMEM;
1024 }
1025
1026 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1027 if (!r) {
1028 edac_printk(KERN_ERR, EDAC_DEVICE,
1029 "Unable to get mem resource\n");
1030 res = -ENODEV;
1031 goto fail;
1032 }
1033
1034 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
1035 dev_name(&pdev->dev))) {
1036 edac_printk(KERN_ERR, EDAC_DEVICE,
1037 "%s:Error requesting mem region\n", ecc_name);
1038 res = -EBUSY;
1039 goto fail;
1040 }
1041
1042 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
1043 1, ecc_name, 1, 0, NULL, 0,
1044 dev_instance++);
1045
1046 if (!dci) {
1047 edac_printk(KERN_ERR, EDAC_DEVICE,
1048 "%s: Unable to allocate EDAC device\n", ecc_name);
1049 res = -ENOMEM;
1050 goto fail;
1051 }
1052
1053 drvdata = dci->pvt_info;
1054 dci->dev = &pdev->dev;
1055 platform_set_drvdata(pdev, dci);
1056 drvdata->edac_dev_name = ecc_name;
1057
1058 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
1059 if (!drvdata->base) {
1060 res = -ENOMEM;
1061 goto fail1;
1062 }
1063
1064 /* Get driver specific data for this EDAC device */
1065 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
1066
1067 /* Check specific dependencies for the module */
1068 if (drvdata->data->setup) {
1069 res = drvdata->data->setup(drvdata);
1070 if (res)
1071 goto fail1;
1072 }
1073
1074 drvdata->sb_irq = platform_get_irq(pdev, 0);
1075 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
1076 altr_edac_device_handler,
1077 0, dev_name(&pdev->dev), dci);
1078 if (res)
1079 goto fail1;
1080
1081 drvdata->db_irq = platform_get_irq(pdev, 1);
1082 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
1083 altr_edac_device_handler,
1084 0, dev_name(&pdev->dev), dci);
1085 if (res)
1086 goto fail1;
1087
1088 dci->mod_name = "Altera ECC Manager";
1089 dci->dev_name = drvdata->edac_dev_name;
1090
1091 res = edac_device_add_device(dci);
1092 if (res)
1093 goto fail1;
1094
1095 altr_create_edacdev_dbgfs(dci, drvdata->data);
1096
1097 devres_close_group(&pdev->dev, NULL);
1098
1099 return 0;
1100
1101 fail1:
1102 edac_device_free_ctl_info(dci);
1103 fail:
1104 devres_release_group(&pdev->dev, NULL);
1105 edac_printk(KERN_ERR, EDAC_DEVICE,
1106 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
1107
1108 return res;
1109 }
1110
1111 static int altr_edac_device_remove(struct platform_device *pdev)
1112 {
1113 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
1114 struct altr_edac_device_dev *drvdata = dci->pvt_info;
1115
1116 debugfs_remove_recursive(drvdata->debugfs_dir);
1117 edac_device_del_device(&pdev->dev);
1118 edac_device_free_ctl_info(dci);
1119
1120 return 0;
1121 }
1122
1123 static struct platform_driver altr_edac_device_driver = {
1124 .probe = altr_edac_device_probe,
1125 .remove = altr_edac_device_remove,
1126 .driver = {
1127 .name = "altr_edac_device",
1128 .of_match_table = altr_edac_device_of_match,
1129 },
1130 };
1131 module_platform_driver(altr_edac_device_driver);
1132
1133 /******************* Arria10 Device ECC Shared Functions *****************/
1134
1135 /*
1136 * Test for memory's ECC dependencies upon entry because platform specific
1137 * startup should have initialized the memory and enabled the ECC.
1138 * Can't turn on ECC here because accessing un-initialized memory will
1139 * cause CE/UE errors possibly causing an ABORT.
1140 */
1141 static int __maybe_unused
1142 altr_check_ecc_deps(struct altr_edac_device_dev *device)
1143 {
1144 void __iomem *base = device->base;
1145 const struct edac_device_prv_data *prv = device->data;
1146
1147 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
1148 return 0;
1149
1150 edac_printk(KERN_ERR, EDAC_DEVICE,
1151 "%s: No ECC present or ECC disabled.\n",
1152 device->edac_dev_name);
1153 return -ENODEV;
1154 }
1155
1156 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
1157 {
1158 struct altr_edac_device_dev *dci = dev_id;
1159 void __iomem *base = dci->base;
1160
1161 if (irq == dci->sb_irq) {
1162 writel(ALTR_A10_ECC_SERRPENA,
1163 base + ALTR_A10_ECC_INTSTAT_OFST);
1164 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1165
1166 return IRQ_HANDLED;
1167 } else if (irq == dci->db_irq) {
1168 writel(ALTR_A10_ECC_DERRPENA,
1169 base + ALTR_A10_ECC_INTSTAT_OFST);
1170 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1171 if (dci->data->panic)
1172 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1173
1174 return IRQ_HANDLED;
1175 }
1176
1177 WARN_ON(1);
1178
1179 return IRQ_NONE;
1180 }
1181
1182 /******************* Arria10 Memory Buffer Functions *********************/
1183
1184 static inline int a10_get_irq_mask(struct device_node *np)
1185 {
1186 int irq;
1187 const u32 *handle = of_get_property(np, "interrupts", NULL);
1188
1189 if (!handle)
1190 return -ENODEV;
1191 irq = be32_to_cpup(handle);
1192 return irq;
1193 }
1194
1195 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
1196 {
1197 u32 value = readl(ioaddr);
1198
1199 value |= bit_mask;
1200 writel(value, ioaddr);
1201 }
1202
1203 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
1204 {
1205 u32 value = readl(ioaddr);
1206
1207 value &= ~bit_mask;
1208 writel(value, ioaddr);
1209 }
1210
1211 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
1212 {
1213 u32 value = readl(ioaddr);
1214
1215 return (value & bit_mask) ? 1 : 0;
1216 }
1217
1218 /*
1219 * This function uses the memory initialization block in the Arria10 ECC
1220 * controller to initialize/clear the entire memory data and ECC data.
1221 */
1222 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
1223 {
1224 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
1225 u32 init_mask, stat_mask, clear_mask;
1226 int ret = 0;
1227
1228 if (port) {
1229 init_mask = ALTR_A10_ECC_INITB;
1230 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
1231 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
1232 } else {
1233 init_mask = ALTR_A10_ECC_INITA;
1234 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
1235 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
1236 }
1237
1238 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
1239 while (limit--) {
1240 if (ecc_test_bits(stat_mask,
1241 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
1242 break;
1243 udelay(1);
1244 }
1245 if (limit < 0)
1246 ret = -EBUSY;
1247
1248 /* Clear any pending ECC interrupts */
1249 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
1250
1251 return ret;
1252 }
1253
1254 static __init int __maybe_unused
1255 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
1256 u32 ecc_ctrl_en_mask, bool dual_port)
1257 {
1258 int ret = 0;
1259 void __iomem *ecc_block_base;
1260 struct regmap *ecc_mgr_map;
1261 char *ecc_name;
1262 struct device_node *np_eccmgr;
1263
1264 ecc_name = (char *)np->name;
1265
1266 /* Get the ECC Manager - parent of the device EDACs */
1267 np_eccmgr = of_get_parent(np);
1268 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
1269 "altr,sysmgr-syscon");
1270 of_node_put(np_eccmgr);
1271 if (IS_ERR(ecc_mgr_map)) {
1272 edac_printk(KERN_ERR, EDAC_DEVICE,
1273 "Unable to get syscon altr,sysmgr-syscon\n");
1274 return -ENODEV;
1275 }
1276
1277 /* Map the ECC Block */
1278 ecc_block_base = of_iomap(np, 0);
1279 if (!ecc_block_base) {
1280 edac_printk(KERN_ERR, EDAC_DEVICE,
1281 "Unable to map %s ECC block\n", ecc_name);
1282 return -ENODEV;
1283 }
1284
1285 /* Disable ECC */
1286 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
1287 writel(ALTR_A10_ECC_SERRINTEN,
1288 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
1289 ecc_clear_bits(ecc_ctrl_en_mask,
1290 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
1291 /* Ensure all writes complete */
1292 wmb();
1293 /* Use HW initialization block to initialize memory for ECC */
1294 ret = altr_init_memory_port(ecc_block_base, 0);
1295 if (ret) {
1296 edac_printk(KERN_ERR, EDAC_DEVICE,
1297 "ECC: cannot init %s PORTA memory\n", ecc_name);
1298 goto out;
1299 }
1300
1301 if (dual_port) {
1302 ret = altr_init_memory_port(ecc_block_base, 1);
1303 if (ret) {
1304 edac_printk(KERN_ERR, EDAC_DEVICE,
1305 "ECC: cannot init %s PORTB memory\n",
1306 ecc_name);
1307 goto out;
1308 }
1309 }
1310
1311 /* Interrupt mode set to every SBERR */
1312 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1313 ALTR_A10_ECC_INTMODE);
1314 /* Enable ECC */
1315 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1316 ALTR_A10_ECC_CTRL_OFST));
1317 writel(ALTR_A10_ECC_SERRINTEN,
1318 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1319 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1320 /* Ensure all writes complete */
1321 wmb();
1322 out:
1323 iounmap(ecc_block_base);
1324 return ret;
1325 }
1326
1327 static int socfpga_is_a10(void)
1328 {
1329 return of_machine_is_compatible("altr,socfpga-arria10");
1330 }
1331
1332 static int validate_parent_available(struct device_node *np);
1333 static const struct of_device_id altr_edac_a10_device_of_match[];
1334 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1335 {
1336 int irq;
1337 struct device_node *child, *np;
1338
1339 if (!socfpga_is_a10())
1340 return -ENODEV;
1341
1342 np = of_find_compatible_node(NULL, NULL,
1343 "altr,socfpga-a10-ecc-manager");
1344 if (!np) {
1345 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1346 return -ENODEV;
1347 }
1348
1349 for_each_child_of_node(np, child) {
1350 const struct of_device_id *pdev_id;
1351 const struct edac_device_prv_data *prv;
1352
1353 if (!of_device_is_available(child))
1354 continue;
1355 if (!of_device_is_compatible(child, compat))
1356 continue;
1357
1358 if (validate_parent_available(child))
1359 continue;
1360
1361 irq = a10_get_irq_mask(child);
1362 if (irq < 0)
1363 continue;
1364
1365 /* Get matching node and check for valid result */
1366 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1367 if (IS_ERR_OR_NULL(pdev_id))
1368 continue;
1369
1370 /* Validate private data pointer before dereferencing */
1371 prv = pdev_id->data;
1372 if (!prv)
1373 continue;
1374
1375 altr_init_a10_ecc_block(child, BIT(irq),
1376 prv->ecc_enable_mask, 0);
1377 }
1378
1379 of_node_put(np);
1380 return 0;
1381 }
1382
1383 /*********************** OCRAM EDAC Device Functions *********************/
1384
1385 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1386
1387 static void *ocram_alloc_mem(size_t size, void **other)
1388 {
1389 struct device_node *np;
1390 struct gen_pool *gp;
1391 void *sram_addr;
1392
1393 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1394 if (!np)
1395 return NULL;
1396
1397 gp = of_gen_pool_get(np, "iram", 0);
1398 of_node_put(np);
1399 if (!gp)
1400 return NULL;
1401
1402 sram_addr = (void *)gen_pool_alloc(gp, size);
1403 if (!sram_addr)
1404 return NULL;
1405
1406 memset(sram_addr, 0, size);
1407 /* Ensure data is written out */
1408 wmb();
1409
1410 /* Remember this handle for freeing later */
1411 *other = gp;
1412
1413 return sram_addr;
1414 }
1415
1416 static void ocram_free_mem(void *p, size_t size, void *other)
1417 {
1418 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1419 }
1420
1421 static const struct edac_device_prv_data ocramecc_data = {
1422 .setup = altr_check_ecc_deps,
1423 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1424 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1425 .alloc_mem = ocram_alloc_mem,
1426 .free_mem = ocram_free_mem,
1427 .ecc_enable_mask = ALTR_OCR_ECC_EN,
1428 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1429 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1430 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1431 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1432 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1433 .inject_fops = &altr_edac_device_inject_fops,
1434 };
1435
1436 static const struct edac_device_prv_data a10_ocramecc_data = {
1437 .setup = altr_check_ecc_deps,
1438 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1439 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1440 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1441 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1442 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1443 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1444 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1445 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1446 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1447 .inject_fops = &altr_edac_a10_device_inject_fops,
1448 /*
1449 * OCRAM panic on uncorrectable error because sleep/resume
1450 * functions and FPGA contents are stored in OCRAM. Prefer
1451 * a kernel panic over executing/loading corrupted data.
1452 */
1453 .panic = true,
1454 };
1455
1456 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1457
1458 /********************* L2 Cache EDAC Device Functions ********************/
1459
1460 #ifdef CONFIG_EDAC_ALTERA_L2C
1461
1462 static void *l2_alloc_mem(size_t size, void **other)
1463 {
1464 struct device *dev = *other;
1465 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1466
1467 if (!ptemp)
1468 return NULL;
1469
1470 /* Make sure everything is written out */
1471 wmb();
1472
1473 /*
1474 * Clean all cache levels up to LoC (includes L2)
1475 * This ensures the corrupted data is written into
1476 * L2 cache for readback test (which causes ECC error).
1477 */
1478 flush_cache_all();
1479
1480 return ptemp;
1481 }
1482
1483 static void l2_free_mem(void *p, size_t size, void *other)
1484 {
1485 struct device *dev = other;
1486
1487 if (dev && p)
1488 devm_kfree(dev, p);
1489 }
1490
1491 /*
1492 * altr_l2_check_deps()
1493 * Test for L2 cache ECC dependencies upon entry because
1494 * platform specific startup should have initialized the L2
1495 * memory and enabled the ECC.
1496 * Bail if ECC is not enabled.
1497 * Note that L2 Cache Enable is forced at build time.
1498 */
1499 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1500 {
1501 void __iomem *base = device->base;
1502 const struct edac_device_prv_data *prv = device->data;
1503
1504 if ((readl(base) & prv->ecc_enable_mask) ==
1505 prv->ecc_enable_mask)
1506 return 0;
1507
1508 edac_printk(KERN_ERR, EDAC_DEVICE,
1509 "L2: No ECC present, or ECC disabled\n");
1510 return -ENODEV;
1511 }
1512
1513 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1514 {
1515 struct altr_edac_device_dev *dci = dev_id;
1516
1517 if (irq == dci->sb_irq) {
1518 regmap_write(dci->edac->ecc_mgr_map,
1519 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1520 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1521 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1522
1523 return IRQ_HANDLED;
1524 } else if (irq == dci->db_irq) {
1525 regmap_write(dci->edac->ecc_mgr_map,
1526 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1527 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1528 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1529 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1530
1531 return IRQ_HANDLED;
1532 }
1533
1534 WARN_ON(1);
1535
1536 return IRQ_NONE;
1537 }
1538
1539 static const struct edac_device_prv_data l2ecc_data = {
1540 .setup = altr_l2_check_deps,
1541 .ce_clear_mask = 0,
1542 .ue_clear_mask = 0,
1543 .alloc_mem = l2_alloc_mem,
1544 .free_mem = l2_free_mem,
1545 .ecc_enable_mask = ALTR_L2_ECC_EN,
1546 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1547 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1548 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1549 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1550 .inject_fops = &altr_edac_device_inject_fops,
1551 };
1552
1553 static const struct edac_device_prv_data a10_l2ecc_data = {
1554 .setup = altr_l2_check_deps,
1555 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1556 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1557 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1558 .alloc_mem = l2_alloc_mem,
1559 .free_mem = l2_free_mem,
1560 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1561 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1562 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1563 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1564 .ecc_irq_handler = altr_edac_a10_l2_irq,
1565 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1566 .inject_fops = &altr_edac_device_inject_fops,
1567 };
1568
1569 #endif /* CONFIG_EDAC_ALTERA_L2C */
1570
1571 /********************* Ethernet Device Functions ********************/
1572
1573 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1574
1575 static const struct edac_device_prv_data a10_enetecc_data = {
1576 .setup = altr_check_ecc_deps,
1577 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1578 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1579 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1580 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1581 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1582 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1583 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1584 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1585 .inject_fops = &altr_edac_a10_device_inject_fops,
1586 };
1587
1588 static int __init socfpga_init_ethernet_ecc(void)
1589 {
1590 return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1591 }
1592
1593 early_initcall(socfpga_init_ethernet_ecc);
1594
1595 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1596
1597 /********************** NAND Device Functions **********************/
1598
1599 #ifdef CONFIG_EDAC_ALTERA_NAND
1600
1601 static const struct edac_device_prv_data a10_nandecc_data = {
1602 .setup = altr_check_ecc_deps,
1603 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1604 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1605 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1606 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1607 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1608 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1609 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1610 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1611 .inject_fops = &altr_edac_a10_device_inject_fops,
1612 };
1613
1614 static int __init socfpga_init_nand_ecc(void)
1615 {
1616 return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1617 }
1618
1619 early_initcall(socfpga_init_nand_ecc);
1620
1621 #endif /* CONFIG_EDAC_ALTERA_NAND */
1622
1623 /********************** DMA Device Functions **********************/
1624
1625 #ifdef CONFIG_EDAC_ALTERA_DMA
1626
1627 static const struct edac_device_prv_data a10_dmaecc_data = {
1628 .setup = altr_check_ecc_deps,
1629 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1630 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1631 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1632 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1633 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1634 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1635 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1636 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1637 .inject_fops = &altr_edac_a10_device_inject_fops,
1638 };
1639
1640 static int __init socfpga_init_dma_ecc(void)
1641 {
1642 return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1643 }
1644
1645 early_initcall(socfpga_init_dma_ecc);
1646
1647 #endif /* CONFIG_EDAC_ALTERA_DMA */
1648
1649 /********************** USB Device Functions **********************/
1650
1651 #ifdef CONFIG_EDAC_ALTERA_USB
1652
1653 static const struct edac_device_prv_data a10_usbecc_data = {
1654 .setup = altr_check_ecc_deps,
1655 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1656 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1657 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1658 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1659 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1660 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1661 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1662 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1663 .inject_fops = &altr_edac_a10_device_inject_fops,
1664 };
1665
1666 static int __init socfpga_init_usb_ecc(void)
1667 {
1668 return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1669 }
1670
1671 early_initcall(socfpga_init_usb_ecc);
1672
1673 #endif /* CONFIG_EDAC_ALTERA_USB */
1674
1675 /********************** QSPI Device Functions **********************/
1676
1677 #ifdef CONFIG_EDAC_ALTERA_QSPI
1678
1679 static const struct edac_device_prv_data a10_qspiecc_data = {
1680 .setup = altr_check_ecc_deps,
1681 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1682 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1683 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1684 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1685 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1686 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1687 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1688 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1689 .inject_fops = &altr_edac_a10_device_inject_fops,
1690 };
1691
1692 static int __init socfpga_init_qspi_ecc(void)
1693 {
1694 return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1695 }
1696
1697 early_initcall(socfpga_init_qspi_ecc);
1698
1699 #endif /* CONFIG_EDAC_ALTERA_QSPI */
1700
1701 /********************* SDMMC Device Functions **********************/
1702
1703 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1704
1705 static const struct edac_device_prv_data a10_sdmmceccb_data;
1706 static int altr_portb_setup(struct altr_edac_device_dev *device)
1707 {
1708 struct edac_device_ctl_info *dci;
1709 struct altr_edac_device_dev *altdev;
1710 char *ecc_name = "sdmmcb-ecc";
1711 int edac_idx, rc;
1712 struct device_node *np;
1713 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1714
1715 rc = altr_check_ecc_deps(device);
1716 if (rc)
1717 return rc;
1718
1719 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1720 if (!np) {
1721 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1722 return -ENODEV;
1723 }
1724
1725 /* Create the PortB EDAC device */
1726 edac_idx = edac_device_alloc_index();
1727 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1728 ecc_name, 1, 0, NULL, 0, edac_idx);
1729 if (!dci) {
1730 edac_printk(KERN_ERR, EDAC_DEVICE,
1731 "%s: Unable to allocate PortB EDAC device\n",
1732 ecc_name);
1733 return -ENOMEM;
1734 }
1735
1736 /* Initialize the PortB EDAC device structure from PortA structure */
1737 altdev = dci->pvt_info;
1738 *altdev = *device;
1739
1740 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1741 return -ENOMEM;
1742
1743 /* Update PortB specific values */
1744 altdev->edac_dev_name = ecc_name;
1745 altdev->edac_idx = edac_idx;
1746 altdev->edac_dev = dci;
1747 altdev->data = prv;
1748 dci->dev = &altdev->ddev;
1749 dci->ctl_name = "Altera ECC Manager";
1750 dci->mod_name = ecc_name;
1751 dci->dev_name = ecc_name;
1752
1753 /* Update the IRQs for PortB */
1754 altdev->sb_irq = irq_of_parse_and_map(np, 2);
1755 if (!altdev->sb_irq) {
1756 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1757 rc = -ENODEV;
1758 goto err_release_group_1;
1759 }
1760 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1761 prv->ecc_irq_handler,
1762 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1763 ecc_name, altdev);
1764 if (rc) {
1765 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1766 goto err_release_group_1;
1767 }
1768
1769 altdev->db_irq = irq_of_parse_and_map(np, 3);
1770 if (!altdev->db_irq) {
1771 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1772 rc = -ENODEV;
1773 goto err_release_group_1;
1774 }
1775 rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1776 prv->ecc_irq_handler,
1777 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1778 ecc_name, altdev);
1779 if (rc) {
1780 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1781 goto err_release_group_1;
1782 }
1783
1784 rc = edac_device_add_device(dci);
1785 if (rc) {
1786 edac_printk(KERN_ERR, EDAC_DEVICE,
1787 "edac_device_add_device portB failed\n");
1788 rc = -ENOMEM;
1789 goto err_release_group_1;
1790 }
1791 altr_create_edacdev_dbgfs(dci, prv);
1792
1793 list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1794
1795 devres_remove_group(&altdev->ddev, altr_portb_setup);
1796
1797 return 0;
1798
1799 err_release_group_1:
1800 edac_device_free_ctl_info(dci);
1801 devres_release_group(&altdev->ddev, altr_portb_setup);
1802 edac_printk(KERN_ERR, EDAC_DEVICE,
1803 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1804 return rc;
1805 }
1806
1807 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1808 {
1809 struct altr_edac_device_dev *ad = dev_id;
1810 void __iomem *base = ad->base;
1811 const struct edac_device_prv_data *priv = ad->data;
1812
1813 if (irq == ad->sb_irq) {
1814 writel(priv->ce_clear_mask,
1815 base + ALTR_A10_ECC_INTSTAT_OFST);
1816 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1817 return IRQ_HANDLED;
1818 } else if (irq == ad->db_irq) {
1819 writel(priv->ue_clear_mask,
1820 base + ALTR_A10_ECC_INTSTAT_OFST);
1821 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1822 return IRQ_HANDLED;
1823 }
1824
1825 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1826
1827 return IRQ_NONE;
1828 }
1829
1830 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1831 .setup = altr_portb_setup,
1832 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1833 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1834 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1835 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1836 .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1837 .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1838 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1839 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1840 .inject_fops = &altr_edac_a10_device_inject_fops,
1841 };
1842
1843 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1844 .setup = altr_portb_setup,
1845 .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1846 .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1847 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1848 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1849 .ce_set_mask = ALTR_A10_ECC_TSERRB,
1850 .ue_set_mask = ALTR_A10_ECC_TDERRB,
1851 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1852 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1853 .inject_fops = &altr_edac_a10_device_inject_fops,
1854 };
1855
1856 static int __init socfpga_init_sdmmc_ecc(void)
1857 {
1858 int rc = -ENODEV;
1859 struct device_node *child;
1860
1861 if (!socfpga_is_a10())
1862 return -ENODEV;
1863
1864 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1865 if (!child) {
1866 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1867 return -ENODEV;
1868 }
1869
1870 if (!of_device_is_available(child))
1871 goto exit;
1872
1873 if (validate_parent_available(child))
1874 goto exit;
1875
1876 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1877 a10_sdmmcecca_data.ecc_enable_mask, 1);
1878 exit:
1879 of_node_put(child);
1880 return rc;
1881 }
1882
1883 early_initcall(socfpga_init_sdmmc_ecc);
1884
1885 #endif /* CONFIG_EDAC_ALTERA_SDMMC */
1886
1887 /********************* Arria10 EDAC Device Functions *************************/
1888 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1889 #ifdef CONFIG_EDAC_ALTERA_L2C
1890 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1891 #endif
1892 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1893 { .compatible = "altr,socfpga-a10-ocram-ecc",
1894 .data = &a10_ocramecc_data },
1895 #endif
1896 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1897 { .compatible = "altr,socfpga-eth-mac-ecc",
1898 .data = &a10_enetecc_data },
1899 #endif
1900 #ifdef CONFIG_EDAC_ALTERA_NAND
1901 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1902 #endif
1903 #ifdef CONFIG_EDAC_ALTERA_DMA
1904 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1905 #endif
1906 #ifdef CONFIG_EDAC_ALTERA_USB
1907 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1908 #endif
1909 #ifdef CONFIG_EDAC_ALTERA_QSPI
1910 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1911 #endif
1912 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1913 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1914 #endif
1915 {},
1916 };
1917 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1918
1919 /*
1920 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1921 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1922 * manager manages the IRQs and the children.
1923 * Based on xgene_edac.c peripheral code.
1924 */
1925
1926 static ssize_t altr_edac_a10_device_trig(struct file *file,
1927 const char __user *user_buf,
1928 size_t count, loff_t *ppos)
1929 {
1930 struct edac_device_ctl_info *edac_dci = file->private_data;
1931 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1932 const struct edac_device_prv_data *priv = drvdata->data;
1933 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1934 unsigned long flags;
1935 u8 trig_type;
1936
1937 if (!user_buf || get_user(trig_type, user_buf))
1938 return -EFAULT;
1939
1940 local_irq_save(flags);
1941 if (trig_type == ALTR_UE_TRIGGER_CHAR)
1942 writel(priv->ue_set_mask, set_addr);
1943 else
1944 writel(priv->ce_set_mask, set_addr);
1945 /* Ensure the interrupt test bits are set */
1946 wmb();
1947 local_irq_restore(flags);
1948
1949 return count;
1950 }
1951
1952 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1953 {
1954 int dberr, bit, sm_offset, irq_status;
1955 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1956 struct irq_chip *chip = irq_desc_get_chip(desc);
1957 int irq = irq_desc_get_irq(desc);
1958
1959 dberr = (irq == edac->db_irq) ? 1 : 0;
1960 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1961 A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1962
1963 chained_irq_enter(chip, desc);
1964
1965 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1966
1967 for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
1968 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1969 if (irq)
1970 generic_handle_irq(irq);
1971 }
1972
1973 chained_irq_exit(chip, desc);
1974 }
1975
1976 static int validate_parent_available(struct device_node *np)
1977 {
1978 struct device_node *parent;
1979 int ret = 0;
1980
1981 /* Ensure parent device is enabled if parent node exists */
1982 parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1983 if (parent && !of_device_is_available(parent))
1984 ret = -ENODEV;
1985
1986 of_node_put(parent);
1987 return ret;
1988 }
1989
1990 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1991 struct device_node *np)
1992 {
1993 struct edac_device_ctl_info *dci;
1994 struct altr_edac_device_dev *altdev;
1995 char *ecc_name = (char *)np->name;
1996 struct resource res;
1997 int edac_idx;
1998 int rc = 0;
1999 const struct edac_device_prv_data *prv;
2000 /* Get matching node and check for valid result */
2001 const struct of_device_id *pdev_id =
2002 of_match_node(altr_edac_a10_device_of_match, np);
2003 if (IS_ERR_OR_NULL(pdev_id))
2004 return -ENODEV;
2005
2006 /* Get driver specific data for this EDAC device */
2007 prv = pdev_id->data;
2008 if (IS_ERR_OR_NULL(prv))
2009 return -ENODEV;
2010
2011 if (validate_parent_available(np))
2012 return -ENODEV;
2013
2014 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
2015 return -ENOMEM;
2016
2017 rc = of_address_to_resource(np, 0, &res);
2018 if (rc < 0) {
2019 edac_printk(KERN_ERR, EDAC_DEVICE,
2020 "%s: no resource address\n", ecc_name);
2021 goto err_release_group;
2022 }
2023
2024 edac_idx = edac_device_alloc_index();
2025 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
2026 1, ecc_name, 1, 0, NULL, 0,
2027 edac_idx);
2028
2029 if (!dci) {
2030 edac_printk(KERN_ERR, EDAC_DEVICE,
2031 "%s: Unable to allocate EDAC device\n", ecc_name);
2032 rc = -ENOMEM;
2033 goto err_release_group;
2034 }
2035
2036 altdev = dci->pvt_info;
2037 dci->dev = edac->dev;
2038 altdev->edac_dev_name = ecc_name;
2039 altdev->edac_idx = edac_idx;
2040 altdev->edac = edac;
2041 altdev->edac_dev = dci;
2042 altdev->data = prv;
2043 altdev->ddev = *edac->dev;
2044 dci->dev = &altdev->ddev;
2045 dci->ctl_name = "Altera ECC Manager";
2046 dci->mod_name = ecc_name;
2047 dci->dev_name = ecc_name;
2048
2049 altdev->base = devm_ioremap_resource(edac->dev, &res);
2050 if (IS_ERR(altdev->base)) {
2051 rc = PTR_ERR(altdev->base);
2052 goto err_release_group1;
2053 }
2054
2055 /* Check specific dependencies for the module */
2056 if (altdev->data->setup) {
2057 rc = altdev->data->setup(altdev);
2058 if (rc)
2059 goto err_release_group1;
2060 }
2061
2062 altdev->sb_irq = irq_of_parse_and_map(np, 0);
2063 if (!altdev->sb_irq) {
2064 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
2065 rc = -ENODEV;
2066 goto err_release_group1;
2067 }
2068 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
2069 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
2070 ecc_name, altdev);
2071 if (rc) {
2072 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
2073 goto err_release_group1;
2074 }
2075
2076 altdev->db_irq = irq_of_parse_and_map(np, 1);
2077 if (!altdev->db_irq) {
2078 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
2079 rc = -ENODEV;
2080 goto err_release_group1;
2081 }
2082 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
2083 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
2084 ecc_name, altdev);
2085 if (rc) {
2086 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
2087 goto err_release_group1;
2088 }
2089
2090 rc = edac_device_add_device(dci);
2091 if (rc) {
2092 dev_err(edac->dev, "edac_device_add_device failed\n");
2093 rc = -ENOMEM;
2094 goto err_release_group1;
2095 }
2096
2097 altr_create_edacdev_dbgfs(dci, prv);
2098
2099 list_add(&altdev->next, &edac->a10_ecc_devices);
2100
2101 devres_remove_group(edac->dev, altr_edac_a10_device_add);
2102
2103 return 0;
2104
2105 err_release_group1:
2106 edac_device_free_ctl_info(dci);
2107 err_release_group:
2108 devres_release_group(edac->dev, NULL);
2109 edac_printk(KERN_ERR, EDAC_DEVICE,
2110 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
2111
2112 return rc;
2113 }
2114
2115 static void a10_eccmgr_irq_mask(struct irq_data *d)
2116 {
2117 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2118
2119 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2120 BIT(d->hwirq));
2121 }
2122
2123 static void a10_eccmgr_irq_unmask(struct irq_data *d)
2124 {
2125 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2126
2127 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
2128 BIT(d->hwirq));
2129 }
2130
2131 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2132 irq_hw_number_t hwirq)
2133 {
2134 struct altr_arria10_edac *edac = d->host_data;
2135
2136 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2137 irq_set_chip_data(irq, edac);
2138 irq_set_noprobe(irq);
2139
2140 return 0;
2141 }
2142
2143 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2144 .map = a10_eccmgr_irqdomain_map,
2145 .xlate = irq_domain_xlate_twocell,
2146 };
2147
2148 static int altr_edac_a10_probe(struct platform_device *pdev)
2149 {
2150 struct altr_arria10_edac *edac;
2151 struct device_node *child;
2152
2153 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2154 if (!edac)
2155 return -ENOMEM;
2156
2157 edac->dev = &pdev->dev;
2158 platform_set_drvdata(pdev, edac);
2159 INIT_LIST_HEAD(&edac->a10_ecc_devices);
2160
2161 edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2162 "altr,sysmgr-syscon");
2163 if (IS_ERR(edac->ecc_mgr_map)) {
2164 edac_printk(KERN_ERR, EDAC_DEVICE,
2165 "Unable to get syscon altr,sysmgr-syscon\n");
2166 return PTR_ERR(edac->ecc_mgr_map);
2167 }
2168
2169 edac->irq_chip.name = pdev->dev.of_node->name;
2170 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2171 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2172 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2173 &a10_eccmgr_ic_ops, edac);
2174 if (!edac->domain) {
2175 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2176 return -ENOMEM;
2177 }
2178
2179 edac->sb_irq = platform_get_irq(pdev, 0);
2180 if (edac->sb_irq < 0) {
2181 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2182 return edac->sb_irq;
2183 }
2184
2185 irq_set_chained_handler_and_data(edac->sb_irq,
2186 altr_edac_a10_irq_handler,
2187 edac);
2188
2189 edac->db_irq = platform_get_irq(pdev, 1);
2190 if (edac->db_irq < 0) {
2191 dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2192 return edac->db_irq;
2193 }
2194 irq_set_chained_handler_and_data(edac->db_irq,
2195 altr_edac_a10_irq_handler,
2196 edac);
2197
2198 for_each_child_of_node(pdev->dev.of_node, child) {
2199 if (!of_device_is_available(child))
2200 continue;
2201
2202 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") ||
2203 of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") ||
2204 of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") ||
2205 of_device_is_compatible(child, "altr,socfpga-nand-ecc") ||
2206 of_device_is_compatible(child, "altr,socfpga-dma-ecc") ||
2207 of_device_is_compatible(child, "altr,socfpga-usb-ecc") ||
2208 of_device_is_compatible(child, "altr,socfpga-qspi-ecc") ||
2209 of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc"))
2210
2211 altr_edac_a10_device_add(edac, child);
2212
2213 else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2214 of_platform_populate(pdev->dev.of_node,
2215 altr_sdram_ctrl_of_match,
2216 NULL, &pdev->dev);
2217 }
2218
2219 return 0;
2220 }
2221
2222 static const struct of_device_id altr_edac_a10_of_match[] = {
2223 { .compatible = "altr,socfpga-a10-ecc-manager" },
2224 {},
2225 };
2226 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2227
2228 static struct platform_driver altr_edac_a10_driver = {
2229 .probe = altr_edac_a10_probe,
2230 .driver = {
2231 .name = "socfpga_a10_ecc_manager",
2232 .of_match_table = altr_edac_a10_of_match,
2233 },
2234 };
2235 module_platform_driver(altr_edac_a10_driver);
2236
2237 /************** Stratix 10 EDAC Device Controller Functions> ************/
2238
2239 #define to_s10edac(p, m) container_of(p, struct altr_stratix10_edac, m)
2240
2241 /*
2242 * The double bit error is handled through SError which is fatal. This is
2243 * called as a panic notifier to printout ECC error info as part of the panic.
2244 */
2245 static int s10_edac_dberr_handler(struct notifier_block *this,
2246 unsigned long event, void *ptr)
2247 {
2248 struct altr_stratix10_edac *edac = to_s10edac(this, panic_notifier);
2249 int err_addr, dberror;
2250
2251 s10_protected_reg_read(edac, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2252 &dberror);
2253 /* Remember the UE Errors for a reboot */
2254 s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, dberror);
2255 if (dberror & S10_DDR0_IRQ_MASK) {
2256 s10_protected_reg_read(edac, S10_DERRADDR_OFST, &err_addr);
2257 /* Remember the UE Error address */
2258 s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST,
2259 err_addr);
2260 edac_printk(KERN_ERR, EDAC_MC,
2261 "EDAC: [Uncorrectable errors @ 0x%08X]\n\n",
2262 err_addr);
2263 }
2264
2265 return NOTIFY_DONE;
2266 }
2267
2268 static void altr_edac_s10_irq_handler(struct irq_desc *desc)
2269 {
2270 struct altr_stratix10_edac *edac = irq_desc_get_handler_data(desc);
2271 struct irq_chip *chip = irq_desc_get_chip(desc);
2272 int irq = irq_desc_get_irq(desc);
2273 int bit, sm_offset, irq_status;
2274
2275 sm_offset = S10_SYSMGR_ECC_INTSTAT_SERR_OFST;
2276
2277 chained_irq_enter(chip, desc);
2278
2279 s10_protected_reg_read(NULL, sm_offset, &irq_status);
2280
2281 for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
2282 irq = irq_linear_revmap(edac->domain, bit);
2283 if (irq)
2284 generic_handle_irq(irq);
2285 }
2286
2287 chained_irq_exit(chip, desc);
2288 }
2289
2290 static void s10_eccmgr_irq_mask(struct irq_data *d)
2291 {
2292 struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d);
2293
2294 s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_SET_OFST,
2295 BIT(d->hwirq));
2296 }
2297
2298 static void s10_eccmgr_irq_unmask(struct irq_data *d)
2299 {
2300 struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d);
2301
2302 s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
2303 BIT(d->hwirq));
2304 }
2305
2306 static int s10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2307 irq_hw_number_t hwirq)
2308 {
2309 struct altr_stratix10_edac *edac = d->host_data;
2310
2311 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2312 irq_set_chip_data(irq, edac);
2313 irq_set_noprobe(irq);
2314
2315 return 0;
2316 }
2317
2318 static const struct irq_domain_ops s10_eccmgr_ic_ops = {
2319 .map = s10_eccmgr_irqdomain_map,
2320 .xlate = irq_domain_xlate_twocell,
2321 };
2322
2323 static int altr_edac_s10_probe(struct platform_device *pdev)
2324 {
2325 struct altr_stratix10_edac *edac;
2326 struct device_node *child;
2327 int dberror, err_addr;
2328
2329 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2330 if (!edac)
2331 return -ENOMEM;
2332
2333 edac->dev = &pdev->dev;
2334 platform_set_drvdata(pdev, edac);
2335 INIT_LIST_HEAD(&edac->s10_ecc_devices);
2336
2337 edac->irq_chip.name = pdev->dev.of_node->name;
2338 edac->irq_chip.irq_mask = s10_eccmgr_irq_mask;
2339 edac->irq_chip.irq_unmask = s10_eccmgr_irq_unmask;
2340 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2341 &s10_eccmgr_ic_ops, edac);
2342 if (!edac->domain) {
2343 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2344 return -ENOMEM;
2345 }
2346
2347 edac->sb_irq = platform_get_irq(pdev, 0);
2348 if (edac->sb_irq < 0) {
2349 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2350 return edac->sb_irq;
2351 }
2352
2353 irq_set_chained_handler_and_data(edac->sb_irq,
2354 altr_edac_s10_irq_handler,
2355 edac);
2356
2357 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2358 atomic_notifier_chain_register(&panic_notifier_list,
2359 &edac->panic_notifier);
2360
2361 /* Printout a message if uncorrectable error previously. */
2362 s10_protected_reg_read(edac, S10_SYSMGR_UE_VAL_OFST, &dberror);
2363 if (dberror) {
2364 s10_protected_reg_read(edac, S10_SYSMGR_UE_ADDR_OFST,
2365 &err_addr);
2366 edac_printk(KERN_ERR, EDAC_DEVICE,
2367 "Previous Boot UE detected[0x%X] @ 0x%X\n",
2368 dberror, err_addr);
2369 /* Reset the sticky registers */
2370 s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, 0);
2371 s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST, 0);
2372 }
2373
2374 for_each_child_of_node(pdev->dev.of_node, child) {
2375 if (!of_device_is_available(child))
2376 continue;
2377
2378 if (of_device_is_compatible(child, "altr,sdram-edac-s10"))
2379 of_platform_populate(pdev->dev.of_node,
2380 altr_sdram_ctrl_of_match,
2381 NULL, &pdev->dev);
2382 }
2383
2384 return 0;
2385 }
2386
2387 static const struct of_device_id altr_edac_s10_of_match[] = {
2388 { .compatible = "altr,socfpga-s10-ecc-manager" },
2389 {},
2390 };
2391 MODULE_DEVICE_TABLE(of, altr_edac_s10_of_match);
2392
2393 static struct platform_driver altr_edac_s10_driver = {
2394 .probe = altr_edac_s10_probe,
2395 .driver = {
2396 .name = "socfpga_s10_ecc_manager",
2397 .of_match_table = altr_edac_s10_of_match,
2398 },
2399 };
2400 module_platform_driver(altr_edac_s10_driver);
2401
2402 MODULE_LICENSE("GPL v2");
2403 MODULE_AUTHOR("Thor Thayer");
2404 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
Linux with added FPC-III support