drivers/gpio/gpio-mxs.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   4 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   5 //
   6 // Based on code from Freescale,
   7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   8
   9 #include <linux/err.h>
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/irq.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/slab.h>
  20 #include <linux/gpio/driver.h>
  21 /* FIXME: for gpio_get_value(), replace this by direct register read */
  22 #include <linux/gpio.h>
  23 #include <linux/module.h>
  24
  25 #define MXS_SET         0x4
  26 #define MXS_CLR         0x8
  27
  28 #define PINCTRL_DOUT(p)         ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
  29 #define PINCTRL_DIN(p)          ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
  30 #define PINCTRL_DOE(p)          ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
  31 #define PINCTRL_PIN2IRQ(p)      ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
  32 #define PINCTRL_IRQEN(p)        ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
  33 #define PINCTRL_IRQLEV(p)       ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
  34 #define PINCTRL_IRQPOL(p)       ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
  35 #define PINCTRL_IRQSTAT(p)      ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
  36
  37 #define GPIO_INT_FALL_EDGE      0x0
  38 #define GPIO_INT_LOW_LEV        0x1
  39 #define GPIO_INT_RISE_EDGE      0x2
  40 #define GPIO_INT_HIGH_LEV       0x3
  41 #define GPIO_INT_LEV_MASK       (1 << 0)
  42 #define GPIO_INT_POL_MASK       (1 << 1)
  43
  44 enum mxs_gpio_id {
  45         IMX23_GPIO,
  46         IMX28_GPIO,
  47 };
  48
  49 struct mxs_gpio_port {
  50         void __iomem *base;
  51         int id;
  52         int irq;
  53         struct irq_domain *domain;
  54         struct gpio_chip gc;
  55         struct device *dev;
  56         enum mxs_gpio_id devid;
  57         u32 both_edges;
  58 };
  59
  60 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
  61 {
  62         return port->devid == IMX23_GPIO;
  63 }
  64
  65 static inline int is_imx28_gpio(struct mxs_gpio_port *port)
  66 {
  67         return port->devid == IMX28_GPIO;
  68 }
  69
  70 /* Note: This driver assumes 32 GPIOs are handled in one register */
  71
  72 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  73 {
  74         u32 val;
  75         u32 pin_mask = 1 << d->hwirq;
  76         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  77         struct irq_chip_type *ct = irq_data_get_chip_type(d);
  78         struct mxs_gpio_port *port = gc->private;
  79         void __iomem *pin_addr;
  80         int edge;
  81
  82         if (!(ct->type & type))
  83                 if (irq_setup_alt_chip(d, type))
  84                         return -EINVAL;
  85
  86         port->both_edges &= ~pin_mask;
  87         switch (type) {
  88         case IRQ_TYPE_EDGE_BOTH:
  89                 val = gpio_get_value(port->gc.base + d->hwirq);
  90                 if (val)
  91                         edge = GPIO_INT_FALL_EDGE;
  92                 else
  93                         edge = GPIO_INT_RISE_EDGE;
  94                 port->both_edges |= pin_mask;
  95                 break;
  96         case IRQ_TYPE_EDGE_RISING:
  97                 edge = GPIO_INT_RISE_EDGE;
  98                 break;
  99         case IRQ_TYPE_EDGE_FALLING:
 100                 edge = GPIO_INT_FALL_EDGE;
 101                 break;
 102         case IRQ_TYPE_LEVEL_LOW:
 103                 edge = GPIO_INT_LOW_LEV;
 104                 break;
 105         case IRQ_TYPE_LEVEL_HIGH:
 106                 edge = GPIO_INT_HIGH_LEV;
 107                 break;
 108         default:
 109                 return -EINVAL;
 110         }
 111
 112         /* set level or edge */
 113         pin_addr = port->base + PINCTRL_IRQLEV(port);
 114         if (edge & GPIO_INT_LEV_MASK) {
 115                 writel(pin_mask, pin_addr + MXS_SET);
 116                 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
 117         } else {
 118                 writel(pin_mask, pin_addr + MXS_CLR);
 119                 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
 120         }
 121
 122         /* set polarity */
 123         pin_addr = port->base + PINCTRL_IRQPOL(port);
 124         if (edge & GPIO_INT_POL_MASK)
 125                 writel(pin_mask, pin_addr + MXS_SET);
 126         else
 127                 writel(pin_mask, pin_addr + MXS_CLR);
 128
 129         writel(pin_mask,
 130                port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 131
 132         return 0;
 133 }
 134
 135 static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
 136 {
 137         u32 bit, val, edge;
 138         void __iomem *pin_addr;
 139
 140         bit = 1 << gpio;
 141
 142         pin_addr = port->base + PINCTRL_IRQPOL(port);
 143         val = readl(pin_addr);
 144         edge = val & bit;
 145
 146         if (edge)
 147                 writel(bit, pin_addr + MXS_CLR);
 148         else
 149                 writel(bit, pin_addr + MXS_SET);
 150 }
 151
 152 /* MXS has one interrupt *per* gpio port */
 153 static void mxs_gpio_irq_handler(struct irq_desc *desc)
 154 {
 155         u32 irq_stat;
 156         struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
 157
 158         desc->irq_data.chip->irq_ack(&desc->irq_data);
 159
 160         irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
 161                         readl(port->base + PINCTRL_IRQEN(port));
 162
 163         while (irq_stat != 0) {
 164                 int irqoffset = fls(irq_stat) - 1;
 165                 if (port->both_edges & (1 << irqoffset))
 166                         mxs_flip_edge(port, irqoffset);
 167
 168                 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
 169                 irq_stat &= ~(1 << irqoffset);
 170         }
 171 }
 172
 173 /*
 174  * Set interrupt number "irq" in the GPIO as a wake-up source.
 175  * While system is running, all registered GPIO interrupts need to have
 176  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 177  * need to have wake-up enabled.
 178  * @param  irq          interrupt source number
 179  * @param  enable       enable as wake-up if equal to non-zero
 180  * @return       This function returns 0 on success.
 181  */
 182 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 183 {
 184         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 185         struct mxs_gpio_port *port = gc->private;
 186
 187         if (enable)
 188                 enable_irq_wake(port->irq);
 189         else
 190                 disable_irq_wake(port->irq);
 191
 192         return 0;
 193 }
 194
 195 static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
 196 {
 197         struct irq_chip_generic *gc;
 198         struct irq_chip_type *ct;
 199         int rv;
 200
 201         gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
 202                                          port->base, handle_level_irq);
 203         if (!gc)
 204                 return -ENOMEM;
 205
 206         gc->private = port;
 207
 208         ct = &gc->chip_types[0];
 209         ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
 210         ct->chip.irq_ack = irq_gc_ack_set_bit;
 211         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 212         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 213         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 214         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 215         ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
 216         ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
 217         ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
 218         ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
 219
 220         ct = &gc->chip_types[1];
 221         ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 222         ct->chip.irq_ack = irq_gc_ack_set_bit;
 223         ct->chip.irq_mask = irq_gc_mask_disable_reg;
 224         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 225         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 226         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 227         ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
 228         ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
 229         ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
 230         ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
 231         ct->handler = handle_level_irq;
 232
 233         rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
 234                                          IRQ_GC_INIT_NESTED_LOCK,
 235                                          IRQ_NOREQUEST, 0);
 236
 237         return rv;
 238 }
 239
 240 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 241 {
 242         struct mxs_gpio_port *port = gpiochip_get_data(gc);
 243
 244         return irq_find_mapping(port->domain, offset);
 245 }
 246
 247 static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
 248 {
 249         struct mxs_gpio_port *port = gpiochip_get_data(gc);
 250         u32 mask = 1 << offset;
 251         u32 dir;
 252
 253         dir = readl(port->base + PINCTRL_DOE(port));
 254         return !(dir & mask);
 255 }
 256
 257 static const struct platform_device_id mxs_gpio_ids[] = {
 258         {
 259                 .name = "imx23-gpio",
 260                 .driver_data = IMX23_GPIO,
 261         }, {
 262                 .name = "imx28-gpio",
 263                 .driver_data = IMX28_GPIO,
 264         }, {
 265                 /* sentinel */
 266         }
 267 };
 268 MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
 269
 270 static const struct of_device_id mxs_gpio_dt_ids[] = {
 271         { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
 272         { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
 273         { /* sentinel */ }
 274 };
 275 MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
 276
 277 static int mxs_gpio_probe(struct platform_device *pdev)
 278 {
 279         struct device_node *np = pdev->dev.of_node;
 280         struct device_node *parent;
 281         static void __iomem *base;
 282         struct mxs_gpio_port *port;
 283         int irq_base;
 284         int err;
 285
 286         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
 287         if (!port)
 288                 return -ENOMEM;
 289
 290         port->id = of_alias_get_id(np, "gpio");
 291         if (port->id < 0)
 292                 return port->id;
 293         port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev);
 294         port->dev = &pdev->dev;
 295         port->irq = platform_get_irq(pdev, 0);
 296         if (port->irq < 0)
 297                 return port->irq;
 298
 299         /*
 300          * map memory region only once, as all the gpio ports
 301          * share the same one
 302          */
 303         if (!base) {
 304                 parent = of_get_parent(np);
 305                 base = of_iomap(parent, 0);
 306                 of_node_put(parent);
 307                 if (!base)
 308                         return -EADDRNOTAVAIL;
 309         }
 310         port->base = base;
 311
 312         /* initially disable the interrupts */
 313         writel(0, port->base + PINCTRL_PIN2IRQ(port));
 314         writel(0, port->base + PINCTRL_IRQEN(port));
 315
 316         /* clear address has to be used to clear IRQSTAT bits */
 317         writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 318
 319         irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
 320         if (irq_base < 0) {
 321                 err = irq_base;
 322                 goto out_iounmap;
 323         }
 324
 325         port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
 326                                              &irq_domain_simple_ops, NULL);
 327         if (!port->domain) {
 328                 err = -ENODEV;
 329                 goto out_iounmap;
 330         }
 331
 332         /* gpio-mxs can be a generic irq chip */
 333         err = mxs_gpio_init_gc(port, irq_base);
 334         if (err < 0)
 335                 goto out_irqdomain_remove;
 336
 337         /* setup one handler for each entry */
 338         irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
 339                                          port);
 340
 341         err = bgpio_init(&port->gc, &pdev->dev, 4,
 342                          port->base + PINCTRL_DIN(port),
 343                          port->base + PINCTRL_DOUT(port) + MXS_SET,
 344                          port->base + PINCTRL_DOUT(port) + MXS_CLR,
 345                          port->base + PINCTRL_DOE(port), NULL, 0);
 346         if (err)
 347                 goto out_irqdomain_remove;
 348
 349         port->gc.to_irq = mxs_gpio_to_irq;
 350         port->gc.get_direction = mxs_gpio_get_direction;
 351         port->gc.base = port->id * 32;
 352
 353         err = gpiochip_add_data(&port->gc, port);
 354         if (err)
 355                 goto out_irqdomain_remove;
 356
 357         return 0;
 358
 359 out_irqdomain_remove:
 360         irq_domain_remove(port->domain);
 361 out_iounmap:
 362         iounmap(port->base);
 363         return err;
 364 }
 365
 366 static struct platform_driver mxs_gpio_driver = {
 367         .driver         = {
 368                 .name   = "gpio-mxs",
 369                 .of_match_table = mxs_gpio_dt_ids,
 370                 .suppress_bind_attrs = true,
 371         },
 372         .probe          = mxs_gpio_probe,
 373         .id_table       = mxs_gpio_ids,
 374 };
 375
 376 static int __init mxs_gpio_init(void)
 377 {
 378         return platform_driver_register(&mxs_gpio_driver);
 379 }
 380 postcore_initcall(mxs_gpio_init);
 381
 382 MODULE_AUTHOR("Freescale Semiconductor, "
 383               "Daniel Mack <danielncaiaq.de>, "
 384               "Juergen Beisert <kernel@pengutronix.de>");
 385 MODULE_DESCRIPTION("Freescale MXS GPIO");
 386 MODULE_LICENSE("GPL");