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arm64: dts: exynos: Move pmu and timer nodes out of soc
[linux/fpc-iii.git] / include / uapi / drm / amdgpu_drm.h
blob4a53f6cfa0341590c3be9b84bb88d49b2d5d4994
1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2014 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #ifndef __AMDGPU_DRM_H__
33 #define __AMDGPU_DRM_H__
34
35 #include "drm.h"
36
37 #if defined(__cplusplus)
38 extern "C" {
39 #endif
40
41 #define DRM_AMDGPU_GEM_CREATE 0x00
42 #define DRM_AMDGPU_GEM_MMAP 0x01
43 #define DRM_AMDGPU_CTX 0x02
44 #define DRM_AMDGPU_BO_LIST 0x03
45 #define DRM_AMDGPU_CS 0x04
46 #define DRM_AMDGPU_INFO 0x05
47 #define DRM_AMDGPU_GEM_METADATA 0x06
48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49 #define DRM_AMDGPU_GEM_VA 0x08
50 #define DRM_AMDGPU_WAIT_CS 0x09
51 #define DRM_AMDGPU_GEM_OP 0x10
52 #define DRM_AMDGPU_GEM_USERPTR 0x11
53 #define DRM_AMDGPU_WAIT_FENCES 0x12
54 #define DRM_AMDGPU_VM 0x13
55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56 #define DRM_AMDGPU_SCHED 0x15
57
58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
74
75 /**
76 * DOC: memory domains
77 *
78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
79 * Memory in this pool could be swapped out to disk if there is pressure.
80 *
81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
83 * pages of system memory, allows GPU access system memory in a linezrized
84 * fashion.
85 *
86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
87 * carved out by the BIOS.
88 *
89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
90 * across shader threads.
91 *
92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
93 * execution of all the waves on a device.
94 *
95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
96 * for appending data.
97 */
98 #define AMDGPU_GEM_DOMAIN_CPU 0x1
99 #define AMDGPU_GEM_DOMAIN_GTT 0x2
100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
101 #define AMDGPU_GEM_DOMAIN_GDS 0x8
102 #define AMDGPU_GEM_DOMAIN_GWS 0x10
103 #define AMDGPU_GEM_DOMAIN_OA 0x20
104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
105 AMDGPU_GEM_DOMAIN_GTT | \
106 AMDGPU_GEM_DOMAIN_VRAM | \
107 AMDGPU_GEM_DOMAIN_GDS | \
108 AMDGPU_GEM_DOMAIN_GWS | \
109 AMDGPU_GEM_DOMAIN_OA)
110
111 /* Flag that CPU access will be required for the case of VRAM domain */
112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
113 /* Flag that CPU access will not work, this VRAM domain is invisible */
114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
115 /* Flag that USWC attributes should be used for GTT */
116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
117 /* Flag that the memory should be in VRAM and cleared */
118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
119 /* Flag that create shadow bo(GTT) while allocating vram bo */
120 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
121 /* Flag that allocating the BO should use linear VRAM */
122 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
123 /* Flag that BO is always valid in this VM */
124 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
125 /* Flag that BO sharing will be explicitly synchronized */
126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype
128 * for the second page onward should be set to NC.
129 */
130 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
131
132 struct drm_amdgpu_gem_create_in {
133 /** the requested memory size */
134 __u64 bo_size;
135 /** physical start_addr alignment in bytes for some HW requirements */
136 __u64 alignment;
137 /** the requested memory domains */
138 __u64 domains;
139 /** allocation flags */
140 __u64 domain_flags;
141 };
142
143 struct drm_amdgpu_gem_create_out {
144 /** returned GEM object handle */
145 __u32 handle;
146 __u32 _pad;
147 };
148
149 union drm_amdgpu_gem_create {
150 struct drm_amdgpu_gem_create_in in;
151 struct drm_amdgpu_gem_create_out out;
152 };
153
154 /** Opcode to create new residency list. */
155 #define AMDGPU_BO_LIST_OP_CREATE 0
156 /** Opcode to destroy previously created residency list */
157 #define AMDGPU_BO_LIST_OP_DESTROY 1
158 /** Opcode to update resource information in the list */
159 #define AMDGPU_BO_LIST_OP_UPDATE 2
160
161 struct drm_amdgpu_bo_list_in {
162 /** Type of operation */
163 __u32 operation;
164 /** Handle of list or 0 if we want to create one */
165 __u32 list_handle;
166 /** Number of BOs in list */
167 __u32 bo_number;
168 /** Size of each element describing BO */
169 __u32 bo_info_size;
170 /** Pointer to array describing BOs */
171 __u64 bo_info_ptr;
172 };
173
174 struct drm_amdgpu_bo_list_entry {
175 /** Handle of BO */
176 __u32 bo_handle;
177 /** New (if specified) BO priority to be used during migration */
178 __u32 bo_priority;
179 };
180
181 struct drm_amdgpu_bo_list_out {
182 /** Handle of resource list */
183 __u32 list_handle;
184 __u32 _pad;
185 };
186
187 union drm_amdgpu_bo_list {
188 struct drm_amdgpu_bo_list_in in;
189 struct drm_amdgpu_bo_list_out out;
190 };
191
192 /* context related */
193 #define AMDGPU_CTX_OP_ALLOC_CTX 1
194 #define AMDGPU_CTX_OP_FREE_CTX 2
195 #define AMDGPU_CTX_OP_QUERY_STATE 3
196 #define AMDGPU_CTX_OP_QUERY_STATE2 4
197
198 /* GPU reset status */
199 #define AMDGPU_CTX_NO_RESET 0
200 /* this the context caused it */
201 #define AMDGPU_CTX_GUILTY_RESET 1
202 /* some other context caused it */
203 #define AMDGPU_CTX_INNOCENT_RESET 2
204 /* unknown cause */
205 #define AMDGPU_CTX_UNKNOWN_RESET 3
206
207 /* indicate gpu reset occured after ctx created */
208 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
209 /* indicate vram lost occured after ctx created */
210 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
211 /* indicate some job from this context once cause gpu hang */
212 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
213
214 /* Context priority level */
215 #define AMDGPU_CTX_PRIORITY_UNSET -2048
216 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
217 #define AMDGPU_CTX_PRIORITY_LOW -512
218 #define AMDGPU_CTX_PRIORITY_NORMAL 0
219 /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
220 #define AMDGPU_CTX_PRIORITY_HIGH 512
221 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
222
223 struct drm_amdgpu_ctx_in {
224 /** AMDGPU_CTX_OP_* */
225 __u32 op;
226 /** For future use, no flags defined so far */
227 __u32 flags;
228 __u32 ctx_id;
229 __s32 priority;
230 };
231
232 union drm_amdgpu_ctx_out {
233 struct {
234 __u32 ctx_id;
235 __u32 _pad;
236 } alloc;
237
238 struct {
239 /** For future use, no flags defined so far */
240 __u64 flags;
241 /** Number of resets caused by this context so far. */
242 __u32 hangs;
243 /** Reset status since the last call of the ioctl. */
244 __u32 reset_status;
245 } state;
246 };
247
248 union drm_amdgpu_ctx {
249 struct drm_amdgpu_ctx_in in;
250 union drm_amdgpu_ctx_out out;
251 };
252
253 /* vm ioctl */
254 #define AMDGPU_VM_OP_RESERVE_VMID 1
255 #define AMDGPU_VM_OP_UNRESERVE_VMID 2
256
257 struct drm_amdgpu_vm_in {
258 /** AMDGPU_VM_OP_* */
259 __u32 op;
260 __u32 flags;
261 };
262
263 struct drm_amdgpu_vm_out {
264 /** For future use, no flags defined so far */
265 __u64 flags;
266 };
267
268 union drm_amdgpu_vm {
269 struct drm_amdgpu_vm_in in;
270 struct drm_amdgpu_vm_out out;
271 };
272
273 /* sched ioctl */
274 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
275 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
276
277 struct drm_amdgpu_sched_in {
278 /* AMDGPU_SCHED_OP_* */
279 __u32 op;
280 __u32 fd;
281 __s32 priority;
282 __u32 ctx_id;
283 };
284
285 union drm_amdgpu_sched {
286 struct drm_amdgpu_sched_in in;
287 };
288
289 /*
290 * This is not a reliable API and you should expect it to fail for any
291 * number of reasons and have fallback path that do not use userptr to
292 * perform any operation.
293 */
294 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
295 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
296 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
297 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
298
299 struct drm_amdgpu_gem_userptr {
300 __u64 addr;
301 __u64 size;
302 /* AMDGPU_GEM_USERPTR_* */
303 __u32 flags;
304 /* Resulting GEM handle */
305 __u32 handle;
306 };
307
308 /* SI-CI-VI: */
309 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
310 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
311 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
312 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
313 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
314 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
315 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
316 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
317 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
318 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
319 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
320 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
321 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
322 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
323 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
324 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21
325 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3
326
327 /* GFX9 and later: */
328 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
329 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
330 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
331 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
332 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
333 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
334 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
335 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
336
337 /* Set/Get helpers for tiling flags. */
338 #define AMDGPU_TILING_SET(field, value) \
339 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
340 #define AMDGPU_TILING_GET(value, field) \
341 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
342
343 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
344 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
345
346 /** The same structure is shared for input/output */
347 struct drm_amdgpu_gem_metadata {
348 /** GEM Object handle */
349 __u32 handle;
350 /** Do we want get or set metadata */
351 __u32 op;
352 struct {
353 /** For future use, no flags defined so far */
354 __u64 flags;
355 /** family specific tiling info */
356 __u64 tiling_info;
357 __u32 data_size_bytes;
358 __u32 data[64];
359 } data;
360 };
361
362 struct drm_amdgpu_gem_mmap_in {
363 /** the GEM object handle */
364 __u32 handle;
365 __u32 _pad;
366 };
367
368 struct drm_amdgpu_gem_mmap_out {
369 /** mmap offset from the vma offset manager */
370 __u64 addr_ptr;
371 };
372
373 union drm_amdgpu_gem_mmap {
374 struct drm_amdgpu_gem_mmap_in in;
375 struct drm_amdgpu_gem_mmap_out out;
376 };
377
378 struct drm_amdgpu_gem_wait_idle_in {
379 /** GEM object handle */
380 __u32 handle;
381 /** For future use, no flags defined so far */
382 __u32 flags;
383 /** Absolute timeout to wait */
384 __u64 timeout;
385 };
386
387 struct drm_amdgpu_gem_wait_idle_out {
388 /** BO status: 0 - BO is idle, 1 - BO is busy */
389 __u32 status;
390 /** Returned current memory domain */
391 __u32 domain;
392 };
393
394 union drm_amdgpu_gem_wait_idle {
395 struct drm_amdgpu_gem_wait_idle_in in;
396 struct drm_amdgpu_gem_wait_idle_out out;
397 };
398
399 struct drm_amdgpu_wait_cs_in {
400 /* Command submission handle
401 * handle equals 0 means none to wait for
402 * handle equals ~0ull means wait for the latest sequence number
403 */
404 __u64 handle;
405 /** Absolute timeout to wait */
406 __u64 timeout;
407 __u32 ip_type;
408 __u32 ip_instance;
409 __u32 ring;
410 __u32 ctx_id;
411 };
412
413 struct drm_amdgpu_wait_cs_out {
414 /** CS status: 0 - CS completed, 1 - CS still busy */
415 __u64 status;
416 };
417
418 union drm_amdgpu_wait_cs {
419 struct drm_amdgpu_wait_cs_in in;
420 struct drm_amdgpu_wait_cs_out out;
421 };
422
423 struct drm_amdgpu_fence {
424 __u32 ctx_id;
425 __u32 ip_type;
426 __u32 ip_instance;
427 __u32 ring;
428 __u64 seq_no;
429 };
430
431 struct drm_amdgpu_wait_fences_in {
432 /** This points to uint64_t * which points to fences */
433 __u64 fences;
434 __u32 fence_count;
435 __u32 wait_all;
436 __u64 timeout_ns;
437 };
438
439 struct drm_amdgpu_wait_fences_out {
440 __u32 status;
441 __u32 first_signaled;
442 };
443
444 union drm_amdgpu_wait_fences {
445 struct drm_amdgpu_wait_fences_in in;
446 struct drm_amdgpu_wait_fences_out out;
447 };
448
449 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
450 #define AMDGPU_GEM_OP_SET_PLACEMENT 1
451
452 /* Sets or returns a value associated with a buffer. */
453 struct drm_amdgpu_gem_op {
454 /** GEM object handle */
455 __u32 handle;
456 /** AMDGPU_GEM_OP_* */
457 __u32 op;
458 /** Input or return value */
459 __u64 value;
460 };
461
462 #define AMDGPU_VA_OP_MAP 1
463 #define AMDGPU_VA_OP_UNMAP 2
464 #define AMDGPU_VA_OP_CLEAR 3
465 #define AMDGPU_VA_OP_REPLACE 4
466
467 /* Delay the page table update till the next CS */
468 #define AMDGPU_VM_DELAY_UPDATE (1 << 0)
469
470 /* Mapping flags */
471 /* readable mapping */
472 #define AMDGPU_VM_PAGE_READABLE (1 << 1)
473 /* writable mapping */
474 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
475 /* executable mapping, new for VI */
476 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
477 /* partially resident texture */
478 #define AMDGPU_VM_PAGE_PRT (1 << 4)
479 /* MTYPE flags use bit 5 to 8 */
480 #define AMDGPU_VM_MTYPE_MASK (0xf << 5)
481 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
482 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
483 /* Use NC MTYPE instead of default MTYPE */
484 #define AMDGPU_VM_MTYPE_NC (1 << 5)
485 /* Use WC MTYPE instead of default MTYPE */
486 #define AMDGPU_VM_MTYPE_WC (2 << 5)
487 /* Use CC MTYPE instead of default MTYPE */
488 #define AMDGPU_VM_MTYPE_CC (3 << 5)
489 /* Use UC MTYPE instead of default MTYPE */
490 #define AMDGPU_VM_MTYPE_UC (4 << 5)
491
492 struct drm_amdgpu_gem_va {
493 /** GEM object handle */
494 __u32 handle;
495 __u32 _pad;
496 /** AMDGPU_VA_OP_* */
497 __u32 operation;
498 /** AMDGPU_VM_PAGE_* */
499 __u32 flags;
500 /** va address to assign . Must be correctly aligned.*/
501 __u64 va_address;
502 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
503 __u64 offset_in_bo;
504 /** Specify mapping size. Must be correctly aligned. */
505 __u64 map_size;
506 };
507
508 #define AMDGPU_HW_IP_GFX 0
509 #define AMDGPU_HW_IP_COMPUTE 1
510 #define AMDGPU_HW_IP_DMA 2
511 #define AMDGPU_HW_IP_UVD 3
512 #define AMDGPU_HW_IP_VCE 4
513 #define AMDGPU_HW_IP_UVD_ENC 5
514 #define AMDGPU_HW_IP_VCN_DEC 6
515 #define AMDGPU_HW_IP_VCN_ENC 7
516 #define AMDGPU_HW_IP_VCN_JPEG 8
517 #define AMDGPU_HW_IP_NUM 9
518
519 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
520
521 #define AMDGPU_CHUNK_ID_IB 0x01
522 #define AMDGPU_CHUNK_ID_FENCE 0x02
523 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
524 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
525 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
526 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
527 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
528
529 struct drm_amdgpu_cs_chunk {
530 __u32 chunk_id;
531 __u32 length_dw;
532 __u64 chunk_data;
533 };
534
535 struct drm_amdgpu_cs_in {
536 /** Rendering context id */
537 __u32 ctx_id;
538 /** Handle of resource list associated with CS */
539 __u32 bo_list_handle;
540 __u32 num_chunks;
541 __u32 _pad;
542 /** this points to __u64 * which point to cs chunks */
543 __u64 chunks;
544 };
545
546 struct drm_amdgpu_cs_out {
547 __u64 handle;
548 };
549
550 union drm_amdgpu_cs {
551 struct drm_amdgpu_cs_in in;
552 struct drm_amdgpu_cs_out out;
553 };
554
555 /* Specify flags to be used for IB */
556
557 /* This IB should be submitted to CE */
558 #define AMDGPU_IB_FLAG_CE (1<<0)
559
560 /* Preamble flag, which means the IB could be dropped if no context switch */
561 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
562
563 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
564 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
565
566 /* The IB fence should do the L2 writeback but not invalidate any shader
567 * caches (L2/vL1/sL1/I$). */
568 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
569
570 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
571 * This will reset wave ID counters for the IB.
572 */
573 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
574
575 struct drm_amdgpu_cs_chunk_ib {
576 __u32 _pad;
577 /** AMDGPU_IB_FLAG_* */
578 __u32 flags;
579 /** Virtual address to begin IB execution */
580 __u64 va_start;
581 /** Size of submission */
582 __u32 ib_bytes;
583 /** HW IP to submit to */
584 __u32 ip_type;
585 /** HW IP index of the same type to submit to */
586 __u32 ip_instance;
587 /** Ring index to submit to */
588 __u32 ring;
589 };
590
591 struct drm_amdgpu_cs_chunk_dep {
592 __u32 ip_type;
593 __u32 ip_instance;
594 __u32 ring;
595 __u32 ctx_id;
596 __u64 handle;
597 };
598
599 struct drm_amdgpu_cs_chunk_fence {
600 __u32 handle;
601 __u32 offset;
602 };
603
604 struct drm_amdgpu_cs_chunk_sem {
605 __u32 handle;
606 };
607
608 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
609 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
610 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
611
612 union drm_amdgpu_fence_to_handle {
613 struct {
614 struct drm_amdgpu_fence fence;
615 __u32 what;
616 __u32 pad;
617 } in;
618 struct {
619 __u32 handle;
620 } out;
621 };
622
623 struct drm_amdgpu_cs_chunk_data {
624 union {
625 struct drm_amdgpu_cs_chunk_ib ib_data;
626 struct drm_amdgpu_cs_chunk_fence fence_data;
627 };
628 };
629
630 /**
631 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
632 *
633 */
634 #define AMDGPU_IDS_FLAGS_FUSION 0x1
635 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
636
637 /* indicate if acceleration can be working */
638 #define AMDGPU_INFO_ACCEL_WORKING 0x00
639 /* get the crtc_id from the mode object id? */
640 #define AMDGPU_INFO_CRTC_FROM_ID 0x01
641 /* query hw IP info */
642 #define AMDGPU_INFO_HW_IP_INFO 0x02
643 /* query hw IP instance count for the specified type */
644 #define AMDGPU_INFO_HW_IP_COUNT 0x03
645 /* timestamp for GL_ARB_timer_query */
646 #define AMDGPU_INFO_TIMESTAMP 0x05
647 /* Query the firmware version */
648 #define AMDGPU_INFO_FW_VERSION 0x0e
649 /* Subquery id: Query VCE firmware version */
650 #define AMDGPU_INFO_FW_VCE 0x1
651 /* Subquery id: Query UVD firmware version */
652 #define AMDGPU_INFO_FW_UVD 0x2
653 /* Subquery id: Query GMC firmware version */
654 #define AMDGPU_INFO_FW_GMC 0x03
655 /* Subquery id: Query GFX ME firmware version */
656 #define AMDGPU_INFO_FW_GFX_ME 0x04
657 /* Subquery id: Query GFX PFP firmware version */
658 #define AMDGPU_INFO_FW_GFX_PFP 0x05
659 /* Subquery id: Query GFX CE firmware version */
660 #define AMDGPU_INFO_FW_GFX_CE 0x06
661 /* Subquery id: Query GFX RLC firmware version */
662 #define AMDGPU_INFO_FW_GFX_RLC 0x07
663 /* Subquery id: Query GFX MEC firmware version */
664 #define AMDGPU_INFO_FW_GFX_MEC 0x08
665 /* Subquery id: Query SMC firmware version */
666 #define AMDGPU_INFO_FW_SMC 0x0a
667 /* Subquery id: Query SDMA firmware version */
668 #define AMDGPU_INFO_FW_SDMA 0x0b
669 /* Subquery id: Query PSP SOS firmware version */
670 #define AMDGPU_INFO_FW_SOS 0x0c
671 /* Subquery id: Query PSP ASD firmware version */
672 #define AMDGPU_INFO_FW_ASD 0x0d
673 /* Subquery id: Query VCN firmware version */
674 #define AMDGPU_INFO_FW_VCN 0x0e
675 /* Subquery id: Query GFX RLC SRLC firmware version */
676 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
677 /* Subquery id: Query GFX RLC SRLG firmware version */
678 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
679 /* Subquery id: Query GFX RLC SRLS firmware version */
680 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
681 /* Subquery id: Query DMCU firmware version */
682 #define AMDGPU_INFO_FW_DMCU 0x12
683 /* number of bytes moved for TTM migration */
684 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
685 /* the used VRAM size */
686 #define AMDGPU_INFO_VRAM_USAGE 0x10
687 /* the used GTT size */
688 #define AMDGPU_INFO_GTT_USAGE 0x11
689 /* Information about GDS, etc. resource configuration */
690 #define AMDGPU_INFO_GDS_CONFIG 0x13
691 /* Query information about VRAM and GTT domains */
692 #define AMDGPU_INFO_VRAM_GTT 0x14
693 /* Query information about register in MMR address space*/
694 #define AMDGPU_INFO_READ_MMR_REG 0x15
695 /* Query information about device: rev id, family, etc. */
696 #define AMDGPU_INFO_DEV_INFO 0x16
697 /* visible vram usage */
698 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
699 /* number of TTM buffer evictions */
700 #define AMDGPU_INFO_NUM_EVICTIONS 0x18
701 /* Query memory about VRAM and GTT domains */
702 #define AMDGPU_INFO_MEMORY 0x19
703 /* Query vce clock table */
704 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
705 /* Query vbios related information */
706 #define AMDGPU_INFO_VBIOS 0x1B
707 /* Subquery id: Query vbios size */
708 #define AMDGPU_INFO_VBIOS_SIZE 0x1
709 /* Subquery id: Query vbios image */
710 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
711 /* Query UVD handles */
712 #define AMDGPU_INFO_NUM_HANDLES 0x1C
713 /* Query sensor related information */
714 #define AMDGPU_INFO_SENSOR 0x1D
715 /* Subquery id: Query GPU shader clock */
716 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
717 /* Subquery id: Query GPU memory clock */
718 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
719 /* Subquery id: Query GPU temperature */
720 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
721 /* Subquery id: Query GPU load */
722 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
723 /* Subquery id: Query average GPU power */
724 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
725 /* Subquery id: Query northbridge voltage */
726 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
727 /* Subquery id: Query graphics voltage */
728 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
729 /* Subquery id: Query GPU stable pstate shader clock */
730 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
731 /* Subquery id: Query GPU stable pstate memory clock */
732 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
733 /* Number of VRAM page faults on CPU access. */
734 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
735 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
736
737 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
738 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
739 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
740 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
741
742 struct drm_amdgpu_query_fw {
743 /** AMDGPU_INFO_FW_* */
744 __u32 fw_type;
745 /**
746 * Index of the IP if there are more IPs of
747 * the same type.
748 */
749 __u32 ip_instance;
750 /**
751 * Index of the engine. Whether this is used depends
752 * on the firmware type. (e.g. MEC, SDMA)
753 */
754 __u32 index;
755 __u32 _pad;
756 };
757
758 /* Input structure for the INFO ioctl */
759 struct drm_amdgpu_info {
760 /* Where the return value will be stored */
761 __u64 return_pointer;
762 /* The size of the return value. Just like "size" in "snprintf",
763 * it limits how many bytes the kernel can write. */
764 __u32 return_size;
765 /* The query request id. */
766 __u32 query;
767
768 union {
769 struct {
770 __u32 id;
771 __u32 _pad;
772 } mode_crtc;
773
774 struct {
775 /** AMDGPU_HW_IP_* */
776 __u32 type;
777 /**
778 * Index of the IP if there are more IPs of the same
779 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
780 */
781 __u32 ip_instance;
782 } query_hw_ip;
783
784 struct {
785 __u32 dword_offset;
786 /** number of registers to read */
787 __u32 count;
788 __u32 instance;
789 /** For future use, no flags defined so far */
790 __u32 flags;
791 } read_mmr_reg;
792
793 struct drm_amdgpu_query_fw query_fw;
794
795 struct {
796 __u32 type;
797 __u32 offset;
798 } vbios_info;
799
800 struct {
801 __u32 type;
802 } sensor_info;
803 };
804 };
805
806 struct drm_amdgpu_info_gds {
807 /** GDS GFX partition size */
808 __u32 gds_gfx_partition_size;
809 /** GDS compute partition size */
810 __u32 compute_partition_size;
811 /** total GDS memory size */
812 __u32 gds_total_size;
813 /** GWS size per GFX partition */
814 __u32 gws_per_gfx_partition;
815 /** GSW size per compute partition */
816 __u32 gws_per_compute_partition;
817 /** OA size per GFX partition */
818 __u32 oa_per_gfx_partition;
819 /** OA size per compute partition */
820 __u32 oa_per_compute_partition;
821 __u32 _pad;
822 };
823
824 struct drm_amdgpu_info_vram_gtt {
825 __u64 vram_size;
826 __u64 vram_cpu_accessible_size;
827 __u64 gtt_size;
828 };
829
830 struct drm_amdgpu_heap_info {
831 /** max. physical memory */
832 __u64 total_heap_size;
833
834 /** Theoretical max. available memory in the given heap */
835 __u64 usable_heap_size;
836
837 /**
838 * Number of bytes allocated in the heap. This includes all processes
839 * and private allocations in the kernel. It changes when new buffers
840 * are allocated, freed, and moved. It cannot be larger than
841 * heap_size.
842 */
843 __u64 heap_usage;
844
845 /**
846 * Theoretical possible max. size of buffer which
847 * could be allocated in the given heap
848 */
849 __u64 max_allocation;
850 };
851
852 struct drm_amdgpu_memory_info {
853 struct drm_amdgpu_heap_info vram;
854 struct drm_amdgpu_heap_info cpu_accessible_vram;
855 struct drm_amdgpu_heap_info gtt;
856 };
857
858 struct drm_amdgpu_info_firmware {
859 __u32 ver;
860 __u32 feature;
861 };
862
863 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
864 #define AMDGPU_VRAM_TYPE_GDDR1 1
865 #define AMDGPU_VRAM_TYPE_DDR2 2
866 #define AMDGPU_VRAM_TYPE_GDDR3 3
867 #define AMDGPU_VRAM_TYPE_GDDR4 4
868 #define AMDGPU_VRAM_TYPE_GDDR5 5
869 #define AMDGPU_VRAM_TYPE_HBM 6
870 #define AMDGPU_VRAM_TYPE_DDR3 7
871 #define AMDGPU_VRAM_TYPE_DDR4 8
872
873 struct drm_amdgpu_info_device {
874 /** PCI Device ID */
875 __u32 device_id;
876 /** Internal chip revision: A0, A1, etc.) */
877 __u32 chip_rev;
878 __u32 external_rev;
879 /** Revision id in PCI Config space */
880 __u32 pci_rev;
881 __u32 family;
882 __u32 num_shader_engines;
883 __u32 num_shader_arrays_per_engine;
884 /* in KHz */
885 __u32 gpu_counter_freq;
886 __u64 max_engine_clock;
887 __u64 max_memory_clock;
888 /* cu information */
889 __u32 cu_active_number;
890 /* NOTE: cu_ao_mask is INVALID, DON'T use it */
891 __u32 cu_ao_mask;
892 __u32 cu_bitmap[4][4];
893 /** Render backend pipe mask. One render backend is CB+DB. */
894 __u32 enabled_rb_pipes_mask;
895 __u32 num_rb_pipes;
896 __u32 num_hw_gfx_contexts;
897 __u32 _pad;
898 __u64 ids_flags;
899 /** Starting virtual address for UMDs. */
900 __u64 virtual_address_offset;
901 /** The maximum virtual address */
902 __u64 virtual_address_max;
903 /** Required alignment of virtual addresses. */
904 __u32 virtual_address_alignment;
905 /** Page table entry - fragment size */
906 __u32 pte_fragment_size;
907 __u32 gart_page_size;
908 /** constant engine ram size*/
909 __u32 ce_ram_size;
910 /** video memory type info*/
911 __u32 vram_type;
912 /** video memory bit width*/
913 __u32 vram_bit_width;
914 /* vce harvesting instance */
915 __u32 vce_harvest_config;
916 /* gfx double offchip LDS buffers */
917 __u32 gc_double_offchip_lds_buf;
918 /* NGG Primitive Buffer */
919 __u64 prim_buf_gpu_addr;
920 /* NGG Position Buffer */
921 __u64 pos_buf_gpu_addr;
922 /* NGG Control Sideband */
923 __u64 cntl_sb_buf_gpu_addr;
924 /* NGG Parameter Cache */
925 __u64 param_buf_gpu_addr;
926 __u32 prim_buf_size;
927 __u32 pos_buf_size;
928 __u32 cntl_sb_buf_size;
929 __u32 param_buf_size;
930 /* wavefront size*/
931 __u32 wave_front_size;
932 /* shader visible vgprs*/
933 __u32 num_shader_visible_vgprs;
934 /* CU per shader array*/
935 __u32 num_cu_per_sh;
936 /* number of tcc blocks*/
937 __u32 num_tcc_blocks;
938 /* gs vgt table depth*/
939 __u32 gs_vgt_table_depth;
940 /* gs primitive buffer depth*/
941 __u32 gs_prim_buffer_depth;
942 /* max gs wavefront per vgt*/
943 __u32 max_gs_waves_per_vgt;
944 __u32 _pad1;
945 /* always on cu bitmap */
946 __u32 cu_ao_bitmap[4][4];
947 /** Starting high virtual address for UMDs. */
948 __u64 high_va_offset;
949 /** The maximum high virtual address */
950 __u64 high_va_max;
951 };
952
953 struct drm_amdgpu_info_hw_ip {
954 /** Version of h/w IP */
955 __u32 hw_ip_version_major;
956 __u32 hw_ip_version_minor;
957 /** Capabilities */
958 __u64 capabilities_flags;
959 /** command buffer address start alignment*/
960 __u32 ib_start_alignment;
961 /** command buffer size alignment*/
962 __u32 ib_size_alignment;
963 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
964 __u32 available_rings;
965 __u32 _pad;
966 };
967
968 struct drm_amdgpu_info_num_handles {
969 /** Max handles as supported by firmware for UVD */
970 __u32 uvd_max_handles;
971 /** Handles currently in use for UVD */
972 __u32 uvd_used_handles;
973 };
974
975 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
976
977 struct drm_amdgpu_info_vce_clock_table_entry {
978 /** System clock */
979 __u32 sclk;
980 /** Memory clock */
981 __u32 mclk;
982 /** VCE clock */
983 __u32 eclk;
984 __u32 pad;
985 };
986
987 struct drm_amdgpu_info_vce_clock_table {
988 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
989 __u32 num_valid_entries;
990 __u32 pad;
991 };
992
993 /*
994 * Supported GPU families
995 */
996 #define AMDGPU_FAMILY_UNKNOWN 0
997 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
998 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
999 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
1000 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
1001 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
1002 #define AMDGPU_FAMILY_AI 141 /* Vega10 */
1003 #define AMDGPU_FAMILY_RV 142 /* Raven */
1004
1005 #if defined(__cplusplus)
1006 }
1007 #endif
1008
1009 #endif
Linux with added FPC-III support