include/uapi/drm/etnaviv_drm.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Copyright (C) 2015 Etnaviv Project
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __ETNAVIV_DRM_H__
  19 #define __ETNAVIV_DRM_H__
  20
  21 #include "drm.h"
  22
  23 #if defined(__cplusplus)
  24 extern "C" {
  25 #endif
  26
  27 /* Please note that modifications to all structs defined here are
  28  * subject to backwards-compatibility constraints:
  29  *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
  30  *     user/kernel compatibility
  31  *  2) Keep fields aligned to their size
  32  *  3) Because of how drm_ioctl() works, we can add new fields at
  33  *     the end of an ioctl if some care is taken: drm_ioctl() will
  34  *     zero out the new fields at the tail of the ioctl, so a zero
  35  *     value should have a backwards compatible meaning.  And for
  36  *     output params, userspace won't see the newly added output
  37  *     fields.. so that has to be somehow ok.
  38  */
  39
  40 /* timeouts are specified in clock-monotonic absolute times (to simplify
  41  * restarting interrupted ioctls).  The following struct is logically the
  42  * same as 'struct timespec' but 32/64b ABI safe.
  43  */
  44 struct drm_etnaviv_timespec {
  45         __s64 tv_sec;          /* seconds */
  46         __s64 tv_nsec;         /* nanoseconds */
  47 };
  48
  49 #define ETNAVIV_PARAM_GPU_MODEL                     0x01
  50 #define ETNAVIV_PARAM_GPU_REVISION                  0x02
  51 #define ETNAVIV_PARAM_GPU_FEATURES_0                0x03
  52 #define ETNAVIV_PARAM_GPU_FEATURES_1                0x04
  53 #define ETNAVIV_PARAM_GPU_FEATURES_2                0x05
  54 #define ETNAVIV_PARAM_GPU_FEATURES_3                0x06
  55 #define ETNAVIV_PARAM_GPU_FEATURES_4                0x07
  56 #define ETNAVIV_PARAM_GPU_FEATURES_5                0x08
  57 #define ETNAVIV_PARAM_GPU_FEATURES_6                0x09
  58 #define ETNAVIV_PARAM_GPU_FEATURES_7                0x0a
  59 #define ETNAVIV_PARAM_GPU_FEATURES_8                0x0b
  60 #define ETNAVIV_PARAM_GPU_FEATURES_9                0x0c
  61 #define ETNAVIV_PARAM_GPU_FEATURES_10               0x0d
  62 #define ETNAVIV_PARAM_GPU_FEATURES_11               0x0e
  63 #define ETNAVIV_PARAM_GPU_FEATURES_12               0x0f
  64
  65 #define ETNAVIV_PARAM_GPU_STREAM_COUNT              0x10
  66 #define ETNAVIV_PARAM_GPU_REGISTER_MAX              0x11
  67 #define ETNAVIV_PARAM_GPU_THREAD_COUNT              0x12
  68 #define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE         0x13
  69 #define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT         0x14
  70 #define ETNAVIV_PARAM_GPU_PIXEL_PIPES               0x15
  71 #define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
  72 #define ETNAVIV_PARAM_GPU_BUFFER_SIZE               0x17
  73 #define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT         0x18
  74 #define ETNAVIV_PARAM_GPU_NUM_CONSTANTS             0x19
  75 #define ETNAVIV_PARAM_GPU_NUM_VARYINGS              0x1a
  76
  77 #define ETNA_MAX_PIPES 4
  78
  79 struct drm_etnaviv_param {
  80         __u32 pipe;           /* in */
  81         __u32 param;          /* in, ETNAVIV_PARAM_x */
  82         __u64 value;          /* out (get_param) or in (set_param) */
  83 };
  84
  85 /*
  86  * GEM buffers:
  87  */
  88
  89 #define ETNA_BO_CACHE_MASK   0x000f0000
  90 /* cache modes */
  91 #define ETNA_BO_CACHED       0x00010000
  92 #define ETNA_BO_WC           0x00020000
  93 #define ETNA_BO_UNCACHED     0x00040000
  94 /* map flags */
  95 #define ETNA_BO_FORCE_MMU    0x00100000
  96
  97 struct drm_etnaviv_gem_new {
  98         __u64 size;           /* in */
  99         __u32 flags;          /* in, mask of ETNA_BO_x */
 100         __u32 handle;         /* out */
 101 };
 102
 103 struct drm_etnaviv_gem_info {
 104         __u32 handle;         /* in */
 105         __u32 pad;
 106         __u64 offset;         /* out, offset to pass to mmap() */
 107 };
 108
 109 #define ETNA_PREP_READ        0x01
 110 #define ETNA_PREP_WRITE       0x02
 111 #define ETNA_PREP_NOSYNC      0x04
 112
 113 struct drm_etnaviv_gem_cpu_prep {
 114         __u32 handle;         /* in */
 115         __u32 op;             /* in, mask of ETNA_PREP_x */
 116         struct drm_etnaviv_timespec timeout;   /* in */
 117 };
 118
 119 struct drm_etnaviv_gem_cpu_fini {
 120         __u32 handle;         /* in */
 121         __u32 flags;          /* in, placeholder for now, no defined values */
 122 };
 123
 124 /*
 125  * Cmdstream Submission:
 126  */
 127
 128 /* The value written into the cmdstream is logically:
 129  * relocbuf->gpuaddr + reloc_offset
 130  *
 131  * NOTE that reloc's must be sorted by order of increasing submit_offset,
 132  * otherwise EINVAL.
 133  */
 134 struct drm_etnaviv_gem_submit_reloc {
 135         __u32 submit_offset;  /* in, offset from submit_bo */
 136         __u32 reloc_idx;      /* in, index of reloc_bo buffer */
 137         __u64 reloc_offset;   /* in, offset from start of reloc_bo */
 138         __u32 flags;          /* in, placeholder for now, no defined values */
 139 };
 140
 141 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
 142  * cmdstream buffer(s) themselves or reloc entries) has one (and only
 143  * one) entry in the submit->bos[] table.
 144  *
 145  * As a optimization, the current buffer (gpu virtual address) can be
 146  * passed back through the 'presumed' field.  If on a subsequent reloc,
 147  * userspace passes back a 'presumed' address that is still valid,
 148  * then patching the cmdstream for this entry is skipped.  This can
 149  * avoid kernel needing to map/access the cmdstream bo in the common
 150  * case.
 151  */
 152 #define ETNA_SUBMIT_BO_READ             0x0001
 153 #define ETNA_SUBMIT_BO_WRITE            0x0002
 154 struct drm_etnaviv_gem_submit_bo {
 155         __u32 flags;          /* in, mask of ETNA_SUBMIT_BO_x */
 156         __u32 handle;         /* in, GEM handle */
 157         __u64 presumed;       /* in/out, presumed buffer address */
 158 };
 159
 160 /* performance monitor request (pmr) */
 161 #define ETNA_PM_PROCESS_PRE             0x0001
 162 #define ETNA_PM_PROCESS_POST            0x0002
 163 struct drm_etnaviv_gem_submit_pmr {
 164         __u32 flags;          /* in, when to process request (ETNA_PM_PROCESS_x) */
 165         __u8  domain;         /* in, pm domain */
 166         __u8  pad;
 167         __u16 signal;         /* in, pm signal */
 168         __u32 sequence;       /* in, sequence number */
 169         __u32 read_offset;    /* in, offset from read_bo */
 170         __u32 read_idx;       /* in, index of read_bo buffer */
 171 };
 172
 173 /* Each cmdstream submit consists of a table of buffers involved, and
 174  * one or more cmdstream buffers.  This allows for conditional execution
 175  * (context-restore), and IB buffers needed for per tile/bin draw cmds.
 176  */
 177 #define ETNA_SUBMIT_NO_IMPLICIT         0x0001
 178 #define ETNA_SUBMIT_FENCE_FD_IN         0x0002
 179 #define ETNA_SUBMIT_FENCE_FD_OUT        0x0004
 180 #define ETNA_SUBMIT_FLAGS               (ETNA_SUBMIT_NO_IMPLICIT | \
 181                                          ETNA_SUBMIT_FENCE_FD_IN | \
 182                                          ETNA_SUBMIT_FENCE_FD_OUT)
 183 #define ETNA_PIPE_3D      0x00
 184 #define ETNA_PIPE_2D      0x01
 185 #define ETNA_PIPE_VG      0x02
 186 struct drm_etnaviv_gem_submit {
 187         __u32 fence;          /* out */
 188         __u32 pipe;           /* in */
 189         __u32 exec_state;     /* in, initial execution state (ETNA_PIPE_x) */
 190         __u32 nr_bos;         /* in, number of submit_bo's */
 191         __u32 nr_relocs;      /* in, number of submit_reloc's */
 192         __u32 stream_size;    /* in, cmdstream size */
 193         __u64 bos;            /* in, ptr to array of submit_bo's */
 194         __u64 relocs;         /* in, ptr to array of submit_reloc's */
 195         __u64 stream;         /* in, ptr to cmdstream */
 196         __u32 flags;          /* in, mask of ETNA_SUBMIT_x */
 197         __s32 fence_fd;       /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
 198         __u64 pmrs;           /* in, ptr to array of submit_pmr's */
 199         __u32 nr_pmrs;        /* in, number of submit_pmr's */
 200         __u32 pad;
 201 };
 202
 203 /* The normal way to synchronize with the GPU is just to CPU_PREP on
 204  * a buffer if you need to access it from the CPU (other cmdstream
 205  * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
 206  * handle the required synchronization under the hood).  This ioctl
 207  * mainly just exists as a way to implement the gallium pipe_fence
 208  * APIs without requiring a dummy bo to synchronize on.
 209  */
 210 #define ETNA_WAIT_NONBLOCK      0x01
 211 struct drm_etnaviv_wait_fence {
 212         __u32 pipe;           /* in */
 213         __u32 fence;          /* in */
 214         __u32 flags;          /* in, mask of ETNA_WAIT_x */
 215         __u32 pad;
 216         struct drm_etnaviv_timespec timeout;   /* in */
 217 };
 218
 219 #define ETNA_USERPTR_READ       0x01
 220 #define ETNA_USERPTR_WRITE      0x02
 221 struct drm_etnaviv_gem_userptr {
 222         __u64 user_ptr; /* in, page aligned user pointer */
 223         __u64 user_size;        /* in, page aligned user size */
 224         __u32 flags;            /* in, flags */
 225         __u32 handle;   /* out, non-zero handle */
 226 };
 227
 228 struct drm_etnaviv_gem_wait {
 229         __u32 pipe;                             /* in */
 230         __u32 handle;                           /* in, bo to be waited for */
 231         __u32 flags;                            /* in, mask of ETNA_WAIT_x  */
 232         __u32 pad;
 233         struct drm_etnaviv_timespec timeout;    /* in */
 234 };
 235
 236 /*
 237  * Performance Monitor (PM):
 238  */
 239
 240 struct drm_etnaviv_pm_domain {
 241         __u32 pipe;       /* in */
 242         __u8  iter;       /* in/out, select pm domain at index iter */
 243         __u8  id;         /* out, id of domain */
 244         __u16 nr_signals; /* out, how many signals does this domain provide */
 245         char  name[64];   /* out, name of domain */
 246 };
 247
 248 struct drm_etnaviv_pm_signal {
 249         __u32 pipe;       /* in */
 250         __u8  domain;     /* in, pm domain index */
 251         __u8  pad;
 252         __u16 iter;       /* in/out, select pm source at index iter */
 253         __u16 id;         /* out, id of signal */
 254         char  name[64];   /* out, name of domain */
 255 };
 256
 257 #define DRM_ETNAVIV_GET_PARAM          0x00
 258 /* placeholder:
 259 #define DRM_ETNAVIV_SET_PARAM          0x01
 260  */
 261 #define DRM_ETNAVIV_GEM_NEW            0x02
 262 #define DRM_ETNAVIV_GEM_INFO           0x03
 263 #define DRM_ETNAVIV_GEM_CPU_PREP       0x04
 264 #define DRM_ETNAVIV_GEM_CPU_FINI       0x05
 265 #define DRM_ETNAVIV_GEM_SUBMIT         0x06
 266 #define DRM_ETNAVIV_WAIT_FENCE         0x07
 267 #define DRM_ETNAVIV_GEM_USERPTR        0x08
 268 #define DRM_ETNAVIV_GEM_WAIT           0x09
 269 #define DRM_ETNAVIV_PM_QUERY_DOM       0x0a
 270 #define DRM_ETNAVIV_PM_QUERY_SIG       0x0b
 271 #define DRM_ETNAVIV_NUM_IOCTLS         0x0c
 272
 273 #define DRM_IOCTL_ETNAVIV_GET_PARAM    DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
 274 #define DRM_IOCTL_ETNAVIV_GEM_NEW      DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
 275 #define DRM_IOCTL_ETNAVIV_GEM_INFO     DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
 276 #define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
 277 #define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
 278 #define DRM_IOCTL_ETNAVIV_GEM_SUBMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
 279 #define DRM_IOCTL_ETNAVIV_WAIT_FENCE   DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
 280 #define DRM_IOCTL_ETNAVIV_GEM_USERPTR  DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
 281 #define DRM_IOCTL_ETNAVIV_GEM_WAIT     DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
 282 #define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
 283 #define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
 284
 285 #if defined(__cplusplus)
 286 }
 287 #endif
 288
 289 #endif /* __ETNAVIV_DRM_H__ */