include/uapi/drm/v3d_drm.h

   1 /*
   2  * Copyright © 2014-2018 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef _V3D_DRM_H_
  25 #define _V3D_DRM_H_
  26
  27 #include "drm.h"
  28
  29 #if defined(__cplusplus)
  30 extern "C" {
  31 #endif
  32
  33 #define DRM_V3D_SUBMIT_CL                         0x00
  34 #define DRM_V3D_WAIT_BO                           0x01
  35 #define DRM_V3D_CREATE_BO                         0x02
  36 #define DRM_V3D_MMAP_BO                           0x03
  37 #define DRM_V3D_GET_PARAM                         0x04
  38 #define DRM_V3D_GET_BO_OFFSET                     0x05
  39 #define DRM_V3D_SUBMIT_TFU                        0x06
  40
  41 #define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
  42 #define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
  43 #define DRM_IOCTL_V3D_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
  44 #define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
  45 #define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
  46 #define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
  47 #define DRM_IOCTL_V3D_SUBMIT_TFU          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
  48
  49 /**
  50  * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
  51  * engine.
  52  *
  53  * This asks the kernel to have the GPU execute an optional binner
  54  * command list, and a render command list.
  55  *
  56  * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
  57  * each CL executes.  The VCD cache should be flushed (if necessary)
  58  * by the submitted CLs.  The TLB writes are guaranteed to have been
  59  * flushed by the time the render done IRQ happens, which is the
  60  * trigger for out_sync.  Any dirtying of cachelines by the job (only
  61  * possible using TMU writes) must be flushed by the caller using the
  62  * CL's cache flush commands.
  63  */
  64 struct drm_v3d_submit_cl {
  65         /* Pointer to the binner command list.
  66          *
  67          * This is the first set of commands executed, which runs the
  68          * coordinate shader to determine where primitives land on the screen,
  69          * then writes out the state updates and draw calls necessary per tile
  70          * to the tile allocation BO.
  71          *
  72          * This BCL will block on any previous BCL submitted on the
  73          * same FD, but not on any RCL or BCLs submitted by other
  74          * clients -- that is left up to the submitter to control
  75          * using in_sync_bcl if necessary.
  76          */
  77         __u32 bcl_start;
  78
  79         /** End address of the BCL (first byte after the BCL) */
  80         __u32 bcl_end;
  81
  82         /* Offset of the render command list.
  83          *
  84          * This is the second set of commands executed, which will either
  85          * execute the tiles that have been set up by the BCL, or a fixed set
  86          * of tiles (in the case of RCL-only blits).
  87          *
  88          * This RCL will block on this submit's BCL, and any previous
  89          * RCL submitted on the same FD, but not on any RCL or BCLs
  90          * submitted by other clients -- that is left up to the
  91          * submitter to control using in_sync_rcl if necessary.
  92          */
  93         __u32 rcl_start;
  94
  95         /** End address of the RCL (first byte after the RCL) */
  96         __u32 rcl_end;
  97
  98         /** An optional sync object to wait on before starting the BCL. */
  99         __u32 in_sync_bcl;
 100         /** An optional sync object to wait on before starting the RCL. */
 101         __u32 in_sync_rcl;
 102         /** An optional sync object to place the completion fence in. */
 103         __u32 out_sync;
 104
 105         /* Offset of the tile alloc memory
 106          *
 107          * This is optional on V3D 3.3 (where the CL can set the value) but
 108          * required on V3D 4.1.
 109          */
 110         __u32 qma;
 111
 112         /** Size of the tile alloc memory. */
 113         __u32 qms;
 114
 115         /** Offset of the tile state data array. */
 116         __u32 qts;
 117
 118         /* Pointer to a u32 array of the BOs that are referenced by the job.
 119          */
 120         __u64 bo_handles;
 121
 122         /* Number of BO handles passed in (size is that times 4). */
 123         __u32 bo_handle_count;
 124
 125         /* Pad, must be zero-filled. */
 126         __u32 pad;
 127 };
 128
 129 /**
 130  * struct drm_v3d_wait_bo - ioctl argument for waiting for
 131  * completion of the last DRM_V3D_SUBMIT_CL on a BO.
 132  *
 133  * This is useful for cases where multiple processes might be
 134  * rendering to a BO and you want to wait for all rendering to be
 135  * completed.
 136  */
 137 struct drm_v3d_wait_bo {
 138         __u32 handle;
 139         __u32 pad;
 140         __u64 timeout_ns;
 141 };
 142
 143 /**
 144  * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
 145  *
 146  * There are currently no values for the flags argument, but it may be
 147  * used in a future extension.
 148  */
 149 struct drm_v3d_create_bo {
 150         __u32 size;
 151         __u32 flags;
 152         /** Returned GEM handle for the BO. */
 153         __u32 handle;
 154         /**
 155          * Returned offset for the BO in the V3D address space.  This offset
 156          * is private to the DRM fd and is valid for the lifetime of the GEM
 157          * handle.
 158          *
 159          * This offset value will always be nonzero, since various HW
 160          * units treat 0 specially.
 161          */
 162         __u32 offset;
 163 };
 164
 165 /**
 166  * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
 167  *
 168  * This doesn't actually perform an mmap.  Instead, it returns the
 169  * offset you need to use in an mmap on the DRM device node.  This
 170  * means that tools like valgrind end up knowing about the mapped
 171  * memory.
 172  *
 173  * There are currently no values for the flags argument, but it may be
 174  * used in a future extension.
 175  */
 176 struct drm_v3d_mmap_bo {
 177         /** Handle for the object being mapped. */
 178         __u32 handle;
 179         __u32 flags;
 180         /** offset into the drm node to use for subsequent mmap call. */
 181         __u64 offset;
 182 };
 183
 184 enum drm_v3d_param {
 185         DRM_V3D_PARAM_V3D_UIFCFG,
 186         DRM_V3D_PARAM_V3D_HUB_IDENT1,
 187         DRM_V3D_PARAM_V3D_HUB_IDENT2,
 188         DRM_V3D_PARAM_V3D_HUB_IDENT3,
 189         DRM_V3D_PARAM_V3D_CORE0_IDENT0,
 190         DRM_V3D_PARAM_V3D_CORE0_IDENT1,
 191         DRM_V3D_PARAM_V3D_CORE0_IDENT2,
 192         DRM_V3D_PARAM_SUPPORTS_TFU,
 193 };
 194
 195 struct drm_v3d_get_param {
 196         __u32 param;
 197         __u32 pad;
 198         __u64 value;
 199 };
 200
 201 /**
 202  * Returns the offset for the BO in the V3D address space for this DRM fd.
 203  * This is the same value returned by drm_v3d_create_bo, if that was called
 204  * from this DRM fd.
 205  */
 206 struct drm_v3d_get_bo_offset {
 207         __u32 handle;
 208         __u32 offset;
 209 };
 210
 211 struct drm_v3d_submit_tfu {
 212         __u32 icfg;
 213         __u32 iia;
 214         __u32 iis;
 215         __u32 ica;
 216         __u32 iua;
 217         __u32 ioa;
 218         __u32 ios;
 219         __u32 coef[4];
 220         /* First handle is the output BO, following are other inputs.
 221          * 0 for unused.
 222          */
 223         __u32 bo_handles[4];
 224         /* sync object to block on before running the TFU job.  Each TFU
 225          * job will execute in the order submitted to its FD.  Synchronization
 226          * against rendering jobs requires using sync objects.
 227          */
 228         __u32 in_sync;
 229         /* Sync object to signal when the TFU job is done. */
 230         __u32 out_sync;
 231 };
 232
 233 #if defined(__cplusplus)
 234 }
 235 #endif
 236
 237 #endif /* _V3D_DRM_H_ */