1 /* SPDX-License-Identifier: GPL-2.0 */
3 * skl-tplg-interface.h - Intel DSP FW private data interface
5 * Copyright (C) 2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * Nilofer, Samreen <samreen.nilofer@intel.com>
10 #ifndef __HDA_TPLG_INTERFACE_H__
11 #define __HDA_TPLG_INTERFACE_H__
13 #include <linux/types.h>
16 * Default types range from 0~12. type can range from 0 to 0xff
17 * SST types start at higher to avoid any overlapping in future
19 #define SKL_CONTROL_TYPE_BYTE_TLV 0x100
20 #define SKL_CONTROL_TYPE_MIC_SELECT 0x102
22 #define HDA_SST_CFG_MAX 900 /* size of copier cfg*/
23 #define MAX_IN_QUEUE 8
24 #define MAX_OUT_QUEUE 8
26 #define SKL_UUID_STR_SZ 40
27 /* Event types goes here */
28 /* Reserve event type 0 for no event handlers */
29 enum skl_event_types
{
38 * enum skl_ch_cfg - channel configuration
40 * @SKL_CH_CFG_MONO: One channel only
41 * @SKL_CH_CFG_STEREO: L & R
42 * @SKL_CH_CFG_2_1: L, R & LFE
43 * @SKL_CH_CFG_3_0: L, C & R
44 * @SKL_CH_CFG_3_1: L, C, R & LFE
45 * @SKL_CH_CFG_QUATRO: L, R, Ls & Rs
46 * @SKL_CH_CFG_4_0: L, C, R & Cs
47 * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs
48 * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE
49 * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
50 * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
51 * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
52 * @SKL_CH_CFG_INVALID: Invalid
56 SKL_CH_CFG_STEREO
= 1,
60 SKL_CH_CFG_QUATRO
= 5,
64 SKL_CH_CFG_DUAL_MONO
= 9,
65 SKL_CH_CFG_I2S_DUAL_STEREO_0
= 10,
66 SKL_CH_CFG_I2S_DUAL_STEREO_1
= 11,
67 SKL_CH_CFG_4_CHANNEL
= 12,
71 enum skl_module_type
{
72 SKL_MODULE_TYPE_MIXER
= 0,
73 SKL_MODULE_TYPE_COPIER
,
74 SKL_MODULE_TYPE_UPDWMIX
,
75 SKL_MODULE_TYPE_SRCINT
,
77 SKL_MODULE_TYPE_BASE_OUTFMT
,
79 SKL_MODULE_TYPE_MIC_SELECT
,
82 enum skl_core_affinity
{
83 SKL_AFFINITY_CORE_0
= 0,
88 enum skl_pipe_conn_type
{
89 SKL_PIPE_CONN_TYPE_NONE
= 0,
90 SKL_PIPE_CONN_TYPE_FE
,
94 enum skl_hw_conn_type
{
102 SKL_DEVICE_DMIC
= 0x1,
103 SKL_DEVICE_I2S
= 0x2,
104 SKL_DEVICE_SLIMBUS
= 0x3,
105 SKL_DEVICE_HDALINK
= 0x4,
106 SKL_DEVICE_HDAHOST
= 0x5,
111 * enum skl_interleaving - interleaving style
113 * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN]
114 * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN]
116 enum skl_interleaving
{
117 SKL_INTERLEAVING_PER_CHANNEL
= 0,
118 SKL_INTERLEAVING_PER_SAMPLE
= 1,
121 enum skl_sample_type
{
122 SKL_SAMPLE_TYPE_INT_MSB
= 0,
123 SKL_SAMPLE_TYPE_INT_LSB
= 1,
124 SKL_SAMPLE_TYPE_INT_SIGNED
= 2,
125 SKL_SAMPLE_TYPE_INT_UNSIGNED
= 3,
126 SKL_SAMPLE_TYPE_FLOAT
= 4
129 enum module_pin_type
{
130 /* All pins of the module takes same PCM inputs or outputs
133 SKL_PIN_TYPE_HOMOGENEOUS
,
134 /* All pins of the module takes different PCM inputs or outputs
137 SKL_PIN_TYPE_HETEROGENEOUS
,
140 enum skl_module_param_type
{
141 SKL_PARAM_DEFAULT
= 0,
147 struct skl_dfw_algo_data
{
160 enum skl_tuple_type
{
165 /* v4 configuration data */
167 struct skl_dfw_v4_module_pin
{
172 struct skl_dfw_v4_module_fmt
{
176 __u32 valid_bit_depth
;
178 __u32 interleaving_style
;
183 struct skl_dfw_v4_module_caps
{
188 __u32 caps
[HDA_SST_CFG_MAX
];
191 struct skl_dfw_v4_pipe
{
196 __u16 memory_pages
:8;
199 struct skl_dfw_v4_module
{
200 char uuid
[SKL_UUID_STR_SZ
];
210 __u32 max_in_queue
:8;
211 __u32 max_out_queue
:8;
219 __u32 hw_conn_type
:4;
222 __u32 params_fixup
:8;
224 __u32 input_pin_type
:1;
225 __u32 output_pin_type
:1;
226 __u32 is_dynamic_in_pin
:1;
227 __u32 is_dynamic_out_pin
:1;
231 struct skl_dfw_v4_pipe pipe
;
232 struct skl_dfw_v4_module_fmt in_fmt
[MAX_IN_QUEUE
];
233 struct skl_dfw_v4_module_fmt out_fmt
[MAX_OUT_QUEUE
];
234 struct skl_dfw_v4_module_pin in_pin
[MAX_IN_QUEUE
];
235 struct skl_dfw_v4_module_pin out_pin
[MAX_OUT_QUEUE
];
236 struct skl_dfw_v4_module_caps caps
;