drivers/i2c/busses/i2c-sirf.c

   1 /*
   2  * I2C bus driver for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/interrupt.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/slab.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/i2c.h>
  15 #include <linux/of_i2c.h>
  16 #include <linux/clk.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19
  20 #define SIRFSOC_I2C_CLK_CTRL            0x00
  21 #define SIRFSOC_I2C_STATUS              0x0C
  22 #define SIRFSOC_I2C_CTRL                0x10
  23 #define SIRFSOC_I2C_IO_CTRL             0x14
  24 #define SIRFSOC_I2C_SDA_DELAY           0x18
  25 #define SIRFSOC_I2C_CMD_START           0x1C
  26 #define SIRFSOC_I2C_CMD_BUF             0x30
  27 #define SIRFSOC_I2C_DATA_BUF            0x80
  28
  29 #define SIRFSOC_I2C_CMD_BUF_MAX         16
  30 #define SIRFSOC_I2C_DATA_BUF_MAX        16
  31
  32 #define SIRFSOC_I2C_CMD(x)              (SIRFSOC_I2C_CMD_BUF + (x)*0x04)
  33 #define SIRFSOC_I2C_DATA_MASK(x)        (0xFF<<(((x)&3)*8))
  34 #define SIRFSOC_I2C_DATA_SHIFT(x)       (((x)&3)*8)
  35
  36 #define SIRFSOC_I2C_DIV_MASK            (0xFFFF)
  37
  38 /* I2C status flags */
  39 #define SIRFSOC_I2C_STAT_BUSY           BIT(0)
  40 #define SIRFSOC_I2C_STAT_TIP            BIT(1)
  41 #define SIRFSOC_I2C_STAT_NACK           BIT(2)
  42 #define SIRFSOC_I2C_STAT_TR_INT         BIT(4)
  43 #define SIRFSOC_I2C_STAT_STOP           BIT(6)
  44 #define SIRFSOC_I2C_STAT_CMD_DONE       BIT(8)
  45 #define SIRFSOC_I2C_STAT_ERR            BIT(9)
  46 #define SIRFSOC_I2C_CMD_INDEX           (0x1F<<16)
  47
  48 /* I2C control flags */
  49 #define SIRFSOC_I2C_RESET               BIT(0)
  50 #define SIRFSOC_I2C_CORE_EN             BIT(1)
  51 #define SIRFSOC_I2C_MASTER_MODE         BIT(2)
  52 #define SIRFSOC_I2C_CMD_DONE_EN         BIT(11)
  53 #define SIRFSOC_I2C_ERR_INT_EN          BIT(12)
  54
  55 #define SIRFSOC_I2C_SDA_DELAY_MASK      (0xFF)
  56 #define SIRFSOC_I2C_SCLF_FILTER         (3<<8)
  57
  58 #define SIRFSOC_I2C_START_CMD           BIT(0)
  59
  60 #define SIRFSOC_I2C_CMD_RP(x)           ((x)&0x7)
  61 #define SIRFSOC_I2C_NACK                BIT(3)
  62 #define SIRFSOC_I2C_WRITE               BIT(4)
  63 #define SIRFSOC_I2C_READ                BIT(5)
  64 #define SIRFSOC_I2C_STOP                BIT(6)
  65 #define SIRFSOC_I2C_START               BIT(7)
  66
  67 #define SIRFSOC_I2C_DEFAULT_SPEED 100000
  68
  69 struct sirfsoc_i2c {
  70         void __iomem *base;
  71         struct clk *clk;
  72         u32 cmd_ptr;            /* Current position in CMD buffer */
  73         u8 *buf;                /* Buffer passed by user */
  74         u32 msg_len;            /* Message length */
  75         u32 finished_len;       /* number of bytes read/written */
  76         u32 read_cmd_len;       /* number of read cmd sent */
  77         int msg_read;           /* 1 indicates a read message */
  78         int err_status;         /* 1 indicates an error on bus */
  79
  80         u32 sda_delay;          /* For suspend/resume */
  81         u32 clk_div;
  82         int last;               /* Last message in transfer, STOP cmd can be sent */
  83
  84         struct completion done; /* indicates completion of message transfer */
  85         struct i2c_adapter adapter;
  86 };
  87
  88 static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
  89 {
  90         u32 data = 0;
  91         int i;
  92
  93         for (i = 0; i < siic->read_cmd_len; i++) {
  94                 if (!(i & 0x3))
  95                         data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
  96                 siic->buf[siic->finished_len++] =
  97                         (u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
  98                                 SIRFSOC_I2C_DATA_SHIFT(i));
  99         }
 100 }
 101
 102 static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
 103 {
 104         u32 regval;
 105         int i = 0;
 106
 107         if (siic->msg_read) {
 108                 while (((siic->finished_len + i) < siic->msg_len)
 109                                 && (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
 110                         regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0);
 111                         if (((siic->finished_len + i) ==
 112                                         (siic->msg_len - 1)) && siic->last)
 113                                 regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK;
 114                         writel(regval,
 115                                 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 116                         i++;
 117                 }
 118
 119                 siic->read_cmd_len = i;
 120         } else {
 121                 while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
 122                                 && (siic->finished_len < siic->msg_len)) {
 123                         regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0);
 124                         if ((siic->finished_len == (siic->msg_len - 1))
 125                                 && siic->last)
 126                                 regval |= SIRFSOC_I2C_STOP;
 127                         writel(regval,
 128                                 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 129                         writel(siic->buf[siic->finished_len++],
 130                                 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 131                 }
 132         }
 133         siic->cmd_ptr = 0;
 134
 135         /* Trigger the transfer */
 136         writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
 137 }
 138
 139 static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
 140 {
 141         struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id;
 142         u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);
 143
 144         if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
 145                 /* Error conditions */
 146                 siic->err_status = 1;
 147                 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
 148
 149                 if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
 150                         dev_err(&siic->adapter.dev, "ACK not received\n");
 151                 else
 152                         dev_err(&siic->adapter.dev, "I2C error\n");
 153
 154                 complete(&siic->done);
 155         } else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
 156                 /* CMD buffer execution complete */
 157                 if (siic->msg_read)
 158                         i2c_sirfsoc_read_data(siic);
 159                 if (siic->finished_len == siic->msg_len)
 160                         complete(&siic->done);
 161                 else /* Fill a new CMD buffer for left data */
 162                         i2c_sirfsoc_queue_cmd(siic);
 163
 164                 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
 165         }
 166
 167         return IRQ_HANDLED;
 168 }
 169
 170 static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
 171         struct i2c_msg *msg)
 172 {
 173         unsigned char addr;
 174         u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE;
 175
 176         /* no data and last message -> add STOP */
 177         if (siic->last && (msg->len == 0))
 178                 regval |= SIRFSOC_I2C_STOP;
 179
 180         writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 181
 182         addr = msg->addr << 1;  /* Generate address */
 183         if (msg->flags & I2C_M_RD)
 184                 addr |= 1;
 185
 186         writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
 187 }
 188
 189 static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg)
 190 {
 191         u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
 192         /* timeout waiting for the xfer to finish or fail */
 193         int timeout = msecs_to_jiffies((msg->len + 1) * 50);
 194         int ret = 0;
 195
 196         i2c_sirfsoc_set_address(siic, msg);
 197
 198         writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN,
 199                 siic->base + SIRFSOC_I2C_CTRL);
 200         i2c_sirfsoc_queue_cmd(siic);
 201
 202         if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
 203                 siic->err_status = 1;
 204                 dev_err(&siic->adapter.dev, "Transfer timeout\n");
 205         }
 206
 207         writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN),
 208                 siic->base + SIRFSOC_I2C_CTRL);
 209         writel(0, siic->base + SIRFSOC_I2C_CMD_START);
 210
 211         if (siic->err_status) {
 212                 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
 213                         siic->base + SIRFSOC_I2C_CTRL);
 214                 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
 215                         cpu_relax();
 216
 217                 ret = -EIO;
 218         }
 219
 220         return ret;
 221 }
 222
 223 static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
 224 {
 225         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 226 }
 227
 228 static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 229         int num)
 230 {
 231         struct sirfsoc_i2c *siic = adap->algo_data;
 232         int i, ret;
 233
 234         clk_enable(siic->clk);
 235
 236         for (i = 0; i < num; i++) {
 237                 siic->buf = msgs[i].buf;
 238                 siic->msg_len = msgs[i].len;
 239                 siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
 240                 siic->err_status = 0;
 241                 siic->cmd_ptr = 0;
 242                 siic->finished_len = 0;
 243                 siic->last = (i == (num - 1));
 244
 245                 ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
 246                 if (ret) {
 247                         clk_disable(siic->clk);
 248                         return ret;
 249                 }
 250         }
 251
 252         clk_disable(siic->clk);
 253         return num;
 254 }
 255
 256 /* I2C algorithms associated with this master controller driver */
 257 static const struct i2c_algorithm i2c_sirfsoc_algo = {
 258         .master_xfer = i2c_sirfsoc_xfer,
 259         .functionality = i2c_sirfsoc_func,
 260 };
 261
 262 static int i2c_sirfsoc_probe(struct platform_device *pdev)
 263 {
 264         struct sirfsoc_i2c *siic;
 265         struct i2c_adapter *adap;
 266         struct resource *mem_res;
 267         struct clk *clk;
 268         int bitrate;
 269         int ctrl_speed;
 270         int irq;
 271
 272         int err;
 273         u32 regval;
 274
 275         clk = clk_get(&pdev->dev, NULL);
 276         if (IS_ERR(clk)) {
 277                 err = PTR_ERR(clk);
 278                 dev_err(&pdev->dev, "Clock get failed\n");
 279                 goto err_get_clk;
 280         }
 281
 282         err = clk_prepare(clk);
 283         if (err) {
 284                 dev_err(&pdev->dev, "Clock prepare failed\n");
 285                 goto err_clk_prep;
 286         }
 287
 288         err = clk_enable(clk);
 289         if (err) {
 290                 dev_err(&pdev->dev, "Clock enable failed\n");
 291                 goto err_clk_en;
 292         }
 293
 294         ctrl_speed = clk_get_rate(clk);
 295
 296         siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
 297         if (!siic) {
 298                 dev_err(&pdev->dev, "Can't allocate driver data\n");
 299                 err = -ENOMEM;
 300                 goto out;
 301         }
 302         adap = &siic->adapter;
 303         adap->class = I2C_CLASS_HWMON;
 304
 305         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 306         if (mem_res == NULL) {
 307                 dev_err(&pdev->dev, "Unable to get MEM resource\n");
 308                 err = -EINVAL;
 309                 goto out;
 310         }
 311
 312         siic->base = devm_ioremap_resource(&pdev->dev, mem_res);
 313         if (IS_ERR(siic->base)) {
 314                 err = PTR_ERR(siic->base);
 315                 goto out;
 316         }
 317
 318         irq = platform_get_irq(pdev, 0);
 319         if (irq < 0) {
 320                 err = irq;
 321                 goto out;
 322         }
 323         err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
 324                 dev_name(&pdev->dev), siic);
 325         if (err)
 326                 goto out;
 327
 328         adap->algo = &i2c_sirfsoc_algo;
 329         adap->algo_data = siic;
 330
 331         adap->dev.of_node = pdev->dev.of_node;
 332         adap->dev.parent = &pdev->dev;
 333         adap->nr = pdev->id;
 334
 335         strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));
 336
 337         platform_set_drvdata(pdev, adap);
 338         init_completion(&siic->done);
 339
 340         /* Controller Initalisation */
 341
 342         writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
 343         while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
 344                 cpu_relax();
 345         writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
 346                 siic->base + SIRFSOC_I2C_CTRL);
 347
 348         siic->clk = clk;
 349
 350         err = of_property_read_u32(pdev->dev.of_node,
 351                 "clock-frequency", &bitrate);
 352         if (err < 0)
 353                 bitrate = SIRFSOC_I2C_DEFAULT_SPEED;
 354
 355         if (bitrate < 100000)
 356                 regval =
 357                         (2 * ctrl_speed) / (2 * bitrate * 11);
 358         else
 359                 regval = ctrl_speed / (bitrate * 5);
 360
 361         writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
 362         if (regval > 0xFF)
 363                 writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
 364         else
 365                 writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);
 366
 367         err = i2c_add_numbered_adapter(adap);
 368         if (err < 0) {
 369                 dev_err(&pdev->dev, "Can't add new i2c adapter\n");
 370                 goto out;
 371         }
 372
 373         clk_disable(clk);
 374
 375         of_i2c_register_devices(adap);
 376
 377         dev_info(&pdev->dev, " I2C adapter ready to operate\n");
 378
 379         return 0;
 380
 381 out:
 382         clk_disable(clk);
 383 err_clk_en:
 384         clk_unprepare(clk);
 385 err_clk_prep:
 386         clk_put(clk);
 387 err_get_clk:
 388         return err;
 389 }
 390
 391 static int i2c_sirfsoc_remove(struct platform_device *pdev)
 392 {
 393         struct i2c_adapter *adapter = platform_get_drvdata(pdev);
 394         struct sirfsoc_i2c *siic = adapter->algo_data;
 395
 396         writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
 397         i2c_del_adapter(adapter);
 398         clk_unprepare(siic->clk);
 399         clk_put(siic->clk);
 400         return 0;
 401 }
 402
 403 #ifdef CONFIG_PM
 404 static int i2c_sirfsoc_suspend(struct device *dev)
 405 {
 406         struct platform_device *pdev = to_platform_device(dev);
 407         struct i2c_adapter *adapter = platform_get_drvdata(pdev);
 408         struct sirfsoc_i2c *siic = adapter->algo_data;
 409
 410         clk_enable(siic->clk);
 411         siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
 412         siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
 413         clk_disable(siic->clk);
 414         return 0;
 415 }
 416
 417 static int i2c_sirfsoc_resume(struct device *dev)
 418 {
 419         struct platform_device *pdev = to_platform_device(dev);
 420         struct i2c_adapter *adapter = platform_get_drvdata(pdev);
 421         struct sirfsoc_i2c *siic = adapter->algo_data;
 422
 423         clk_enable(siic->clk);
 424         writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
 425         writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
 426                 siic->base + SIRFSOC_I2C_CTRL);
 427         writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
 428         writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
 429         clk_disable(siic->clk);
 430         return 0;
 431 }
 432
 433 static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
 434         .suspend = i2c_sirfsoc_suspend,
 435         .resume = i2c_sirfsoc_resume,
 436 };
 437 #endif
 438
 439 static const struct of_device_id sirfsoc_i2c_of_match[] = {
 440         { .compatible = "sirf,prima2-i2c", },
 441         {},
 442 };
 443 MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);
 444
 445 static struct platform_driver i2c_sirfsoc_driver = {
 446         .driver = {
 447                 .name = "sirfsoc_i2c",
 448                 .owner = THIS_MODULE,
 449 #ifdef CONFIG_PM
 450                 .pm = &i2c_sirfsoc_pm_ops,
 451 #endif
 452                 .of_match_table = sirfsoc_i2c_of_match,
 453         },
 454         .probe = i2c_sirfsoc_probe,
 455         .remove = i2c_sirfsoc_remove,
 456 };
 457 module_platform_driver(i2c_sirfsoc_driver);
 458
 459 MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
 460 MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
 461         "Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
 462 MODULE_LICENSE("GPL v2");